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Searched refs:safe_to_lower (Results 1 – 24 of 24) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hubbub.c151 bool safe_to_lower) in hubbub21_program_urgent_watermarks() argument
159 if (safe_to_lower || watermarks->a.urgent_ns > hubbub1->watermarks.a.urgent_ns) { in hubbub21_program_urgent_watermarks()
174 if (safe_to_lower || watermarks->a.frac_urg_bw_flip in hubbub21_program_urgent_watermarks()
184 if (safe_to_lower || watermarks->a.frac_urg_bw_nom in hubbub21_program_urgent_watermarks()
194 if (safe_to_lower || watermarks->a.urgent_latency_ns > hubbub1->watermarks.a.urgent_latency_ns) { in hubbub21_program_urgent_watermarks()
204 if (safe_to_lower || watermarks->b.urgent_ns > hubbub1->watermarks.b.urgent_ns) { in hubbub21_program_urgent_watermarks()
219 if (safe_to_lower || watermarks->a.frac_urg_bw_flip in hubbub21_program_urgent_watermarks()
229 if (safe_to_lower || watermarks->a.frac_urg_bw_nom in hubbub21_program_urgent_watermarks()
239 if (safe_to_lower || watermarks->b.urgent_latency_ns > hubbub1->watermarks.b.urgent_latency_ns) { in hubbub21_program_urgent_watermarks()
249 if (safe_to_lower || watermarks->c.urgent_ns > hubbub1->watermarks.c.urgent_ns) { in hubbub21_program_urgent_watermarks()
[all …]
Ddcn21_hubbub.h132 bool safe_to_lower);
137 bool safe_to_lower);
142 bool safe_to_lower);
147 bool safe_to_lower);
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_hubbub.c155 bool safe_to_lower) in hubbub31_program_urgent_watermarks() argument
163 if (safe_to_lower || watermarks->a.urgent_ns > hubbub2->watermarks.a.urgent_ns) { in hubbub31_program_urgent_watermarks()
177 if (safe_to_lower || watermarks->a.frac_urg_bw_flip in hubbub31_program_urgent_watermarks()
187 if (safe_to_lower || watermarks->a.frac_urg_bw_nom in hubbub31_program_urgent_watermarks()
197 if (safe_to_lower || watermarks->a.urgent_latency_ns > hubbub2->watermarks.a.urgent_latency_ns) { in hubbub31_program_urgent_watermarks()
207 if (safe_to_lower || watermarks->b.urgent_ns > hubbub2->watermarks.b.urgent_ns) { in hubbub31_program_urgent_watermarks()
221 if (safe_to_lower || watermarks->b.frac_urg_bw_flip in hubbub31_program_urgent_watermarks()
231 if (safe_to_lower || watermarks->b.frac_urg_bw_nom in hubbub31_program_urgent_watermarks()
241 if (safe_to_lower || watermarks->b.urgent_latency_ns > hubbub2->watermarks.b.urgent_latency_ns) { in hubbub31_program_urgent_watermarks()
251 if (safe_to_lower || watermarks->c.urgent_ns > hubbub2->watermarks.c.urgent_ns) { in hubbub31_program_urgent_watermarks()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c104 struct dc_state *context, bool safe_to_lower) in dcn20_update_clocks_update_dpp_dto() argument
120 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) in dcn20_update_clocks_update_dpp_dto()
209 bool safe_to_lower) in dcn2_update_clocks() argument
244 if (enter_display_off == safe_to_lower) { in dcn2_update_clocks()
253 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn2_update_clocks()
259 if (should_set_clock(safe_to_lower, in dcn2_update_clocks()
266 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) { in dcn2_update_clocks()
274 …if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state… in dcn2_update_clocks()
281 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { in dcn2_update_clocks()
287 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in dcn2_update_clocks()
[all …]
Ddcn20_clk_mgr.h31 bool safe_to_lower);
35 bool safe_to_lower);
37 struct dc_state *context, bool safe_to_lower);
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hubbub.c249 bool safe_to_lower) in hubbub1_program_urgent_watermarks() argument
257 if (safe_to_lower || watermarks->a.urgent_ns > hubbub1->watermarks.a.urgent_ns) { in hubbub1_program_urgent_watermarks()
270 if (safe_to_lower || watermarks->a.pte_meta_urgent_ns > hubbub1->watermarks.a.pte_meta_urgent_ns) { in hubbub1_program_urgent_watermarks()
282 if (safe_to_lower || watermarks->b.urgent_ns > hubbub1->watermarks.b.urgent_ns) { in hubbub1_program_urgent_watermarks()
295 if (safe_to_lower || watermarks->b.pte_meta_urgent_ns > hubbub1->watermarks.b.pte_meta_urgent_ns) { in hubbub1_program_urgent_watermarks()
307 if (safe_to_lower || watermarks->c.urgent_ns > hubbub1->watermarks.c.urgent_ns) { in hubbub1_program_urgent_watermarks()
320 if (safe_to_lower || watermarks->c.pte_meta_urgent_ns > hubbub1->watermarks.c.pte_meta_urgent_ns) { in hubbub1_program_urgent_watermarks()
332 if (safe_to_lower || watermarks->d.urgent_ns > hubbub1->watermarks.d.urgent_ns) { in hubbub1_program_urgent_watermarks()
345 if (safe_to_lower || watermarks->d.pte_meta_urgent_ns > hubbub1->watermarks.d.pte_meta_urgent_ns) { in hubbub1_program_urgent_watermarks()
363 bool safe_to_lower) in hubbub1_program_stutter_watermarks() argument
[all …]
Ddcn10_hubbub.h373 bool safe_to_lower);
396 bool safe_to_lower);
401 bool safe_to_lower);
406 bool safe_to_lower);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr.c92 bool safe_to_lower) in ramp_up_dispclk_with_dpp() argument
156 if (!safe_to_lower) in ramp_up_dispclk_with_dpp()
192 bool safe_to_lower) in rv1_update_clocks() argument
217 if (enter_display_off == safe_to_lower) { in rv1_update_clocks()
233 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { in rv1_update_clocks()
242 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) { in rv1_update_clocks()
248 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in rv1_update_clocks()
253 if (should_set_clock(safe_to_lower, in rv1_update_clocks()
275 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) in rv1_update_clocks()
277 ramp_up_dispclk_with_dpp(clk_mgr, dc, new_clocks, safe_to_lower); in rv1_update_clocks()
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dclk_mgr_internal.h304 static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk) in should_set_clock() argument
306 return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk); in should_set_clock()
309 static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_sup… in should_update_pstate_support() argument
312 if (calc_support && safe_to_lower) in should_update_pstate_support()
314 else if (!calc_support && !safe_to_lower) in should_update_pstate_support()
Ddchubbub.h152 bool safe_to_lower);
Dclk_mgr.h234 bool safe_to_lower);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr.c245 bool safe_to_lower) in dcn3_update_clocks() argument
278 if (enter_display_off == safe_to_lower) in dcn3_update_clocks()
285 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn3_update_clocks()
290 …if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_d… in dcn3_update_clocks()
295 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) in dcn3_update_clocks()
302 …if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state… in dcn3_update_clocks()
312 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { in dcn3_update_clocks()
322 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { in dcn3_update_clocks()
331 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn3_update_clocks()
337 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { in dcn3_update_clocks()
[all …]
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clk_mgr.c672 bool safe_to_lower) in dce_update_clocks() argument
684 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce_update_clocks()
690 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { in dce_update_clocks()
699 bool safe_to_lower) in dce11_update_clocks() argument
711 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce11_update_clocks()
717 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { in dce11_update_clocks()
726 bool safe_to_lower) in dce112_update_clocks() argument
738 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce112_update_clocks()
744 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { in dce112_update_clocks()
753 bool safe_to_lower) in dce12_update_clocks() argument
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
Ddce120_clk_mgr.c86 bool safe_to_lower) in dce12_update_clocks() argument
97 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce12_update_clocks()
112 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) { in dce12_update_clocks()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/
Ddce60_clk_mgr.c122 bool safe_to_lower) in dce60_update_clocks() argument
134 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce60_update_clocks()
140 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce60_update_clocks()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr.c102 struct dc_state *context, int ref_dpp_clk, bool safe_to_lower) in rn_update_clocks_update_dpp_dto() argument
119 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) in rn_update_clocks_update_dpp_dto()
128 bool safe_to_lower) in rn_update_clocks() argument
147 if (safe_to_lower && !dc->debug.disable_48mhz_pwrdwn) { in rn_update_clocks()
168 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in rn_update_clocks()
173 if (should_set_clock(safe_to_lower, in rn_update_clocks()
193 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { in rn_update_clocks()
200 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in rn_update_clocks()
213 safe_to_lower); in rn_update_clocks()
223 safe_to_lower); in rn_update_clocks()
[all …]
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
Ddce112_clk_mgr.c197 bool safe_to_lower) in dce112_update_clocks() argument
209 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce112_update_clocks()
215 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce112_update_clocks()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Dvg_clk_mgr.c94 bool safe_to_lower) in vg_update_clocks() argument
111 if (safe_to_lower) { in vg_update_clocks()
139 …if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc-… in vg_update_clocks()
144 if (should_set_clock(safe_to_lower, in vg_update_clocks()
156 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in vg_update_clocks()
163 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in vg_update_clocks()
172 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); in vg_update_clocks()
180 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); in vg_update_clocks()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hubbub.c575 bool safe_to_lower) in hubbub2_program_watermarks() argument
583 if (hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub2_program_watermarks()
586 if (hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub2_program_watermarks()
596 safe_to_lower = true; in hubbub2_program_watermarks()
598 hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); in hubbub2_program_watermarks()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hubbub.c100 bool safe_to_lower) in hubbub3_program_watermarks() argument
105 if (hubbub21_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub3_program_watermarks()
108 if (hubbub21_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub3_program_watermarks()
111 if (hubbub21_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower)) in hubbub3_program_watermarks()
Ddcn30_hubbub.h129 bool safe_to_lower);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
Ddcn31_clk_mgr.c128 bool safe_to_lower) in dcn31_update_clocks() argument
146 if (safe_to_lower) { in dcn31_update_clocks()
192 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn31_update_clocks()
197 if (should_set_clock(safe_to_lower, in dcn31_update_clocks()
209 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in dcn31_update_clocks()
216 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn31_update_clocks()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.c251 bool safe_to_lower) in dce11_update_clocks() argument
263 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce11_update_clocks()
269 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce11_update_clocks()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
Ddce_clk_mgr.c397 bool safe_to_lower) in dce_update_clocks() argument
409 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) in dce_update_clocks()
415 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce_update_clocks()