| /drivers/soc/samsung/ |
| D | s3c-pm-debug.c | 49 struct pm_uart_save *save = &uart_save; in s3c_pm_save_uarts() local
51 save->ulcon = __raw_readl(regs + S3C2410_ULCON); in s3c_pm_save_uarts()
52 save->ucon = __raw_readl(regs + S3C2410_UCON); in s3c_pm_save_uarts()
53 save->ufcon = __raw_readl(regs + S3C2410_UFCON); in s3c_pm_save_uarts()
54 save->umcon = __raw_readl(regs + S3C2410_UMCON); in s3c_pm_save_uarts()
55 save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); in s3c_pm_save_uarts()
58 save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT); in s3c_pm_save_uarts()
61 regs, save->ulcon, save->ucon, save->ufcon, save->ubrdiv); in s3c_pm_save_uarts()
67 struct pm_uart_save *save = &uart_save; in s3c_pm_restore_uarts() local
69 s3c_pm_arch_update_uart(regs, save); in s3c_pm_restore_uarts()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/subdev/pci/ |
| D | agp.c | 60 u32 save[2]; in nvkm_agp_preinit() local
72 save[0] = nvkm_pci_rd32(pci, 0x0004); in nvkm_agp_preinit()
73 nvkm_pci_wr32(pci, 0x0004, save[0] & ~0x00000004); in nvkm_agp_preinit()
77 save[1] = nvkm_mask(device, 0x000200, 0x00011100, 0x00000000); in nvkm_agp_preinit()
78 nvkm_mask(device, 0x000200, 0x00011100, save[1]); in nvkm_agp_preinit()
81 nvkm_pci_wr32(pci, 0x0004, save[0]); in nvkm_agp_preinit()
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| /drivers/pinctrl/samsung/ |
| D | pinctrl-exynos.c | 637 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynos_pinctrl_suspend_bank() local
640 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET in exynos_pinctrl_suspend_bank()
642 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET in exynos_pinctrl_suspend_bank()
644 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET in exynos_pinctrl_suspend_bank()
646 save->eint_mask = readl(regs + bank->irq_chip->eint_mask in exynos_pinctrl_suspend_bank()
649 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); in exynos_pinctrl_suspend_bank()
650 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); in exynos_pinctrl_suspend_bank()
651 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); in exynos_pinctrl_suspend_bank()
652 pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); in exynos_pinctrl_suspend_bank()
678 struct exynos_eint_gpio_save *save = bank->soc_priv; in exynos_pinctrl_resume_bank() local
[all …]
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| /drivers/pci/ |
| D | vc.c | 27 u32 *buf, int dwords, bool save) in pci_vc_save_restore_dwords() argument
32 if (save) in pci_vc_save_restore_dwords()
186 bool save) in pci_vc_do_save_buffer() argument
195 pci_vc_do_save_buffer(dev, pos, NULL, save)) { in pci_vc_do_save_buffer()
215 if (save) in pci_vc_do_save_buffer()
253 size / 4, save); in pci_vc_do_save_buffer()
258 if (!save) in pci_vc_do_save_buffer()
300 size / 4, save); in pci_vc_do_save_buffer()
310 if (save) in pci_vc_do_save_buffer()
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| /drivers/iio/dac/ |
| D | m62332.c | 29 u8 save[M62332_CHANNELS]; member
135 data->save[0] = data->raw[0]; in m62332_suspend()
136 data->save[1] = data->raw[1]; in m62332_suspend()
152 ret = m62332_set_value(indio_dev, data->save[0], 0); in m62332_resume()
156 return m62332_set_value(indio_dev, data->save[1], 1); in m62332_resume()
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| D | ds4424.c | 58 uint8_t save[DS4424_MAX_DAC_CHANNELS]; member
183 data->save[i] = data->raw[i]; in ds4424_suspend()
201 ret = ds4424_set_value(indio_dev, data->save[i], in ds4424_resume()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | ramgp100.c | 58 u32 save = nvkm_rd32(device, 0x9a065c) & 0x000000f0; in gp100_ram_init() local
60 if (i != save >> 4) { in gp100_ram_init()
65 nvkm_mask(device, 0x9a065c, 0x000000f0, save); in gp100_ram_init()
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| /drivers/clk/samsung/ |
| D | clk-exynos5-subcmu.c | 25 rd->save = readl(base + rd->offset); in exynos5_subcmu_clk_save()
26 writel((rd->save & ~rd->mask) | rd->value, base + rd->offset); in exynos5_subcmu_clk_save()
27 rd->save &= rd->mask; in exynos5_subcmu_clk_save()
36 writel((readl(base + rd->offset) & ~rd->mask) | rd->save, in exynos5_subcmu_clk_restore()
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| D | clk-exynos5-subcmu.h | 10 u32 save; member
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| /drivers/video/fbdev/aty/ |
| D | radeon_base.c | 302 u32 save, tmp; in radeon_pll_errata_after_data_slow() local
303 save = INREG(CLOCK_CNTL_INDEX); in radeon_pll_errata_after_data_slow()
304 tmp = save & ~(0x3f | PLL_WR_EN); in radeon_pll_errata_after_data_slow()
307 OUTREG(CLOCK_CNTL_INDEX, save); in radeon_pll_errata_after_data_slow()
1310 struct radeon_regs *save) in radeon_save_state() argument
1313 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL); in radeon_save_state()
1314 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL); in radeon_save_state()
1315 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL); in radeon_save_state()
1316 save->dac_cntl = INREG(DAC_CNTL); in radeon_save_state()
1317 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP); in radeon_save_state()
[all …]
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| /drivers/misc/sgi-gru/ |
| D | grumain.c | 479 static void gru_load_context_data(void *save, void *grubase, int ctxnum, in gru_load_context_data() argument
495 save += gru_copy_handle(cb, save); in gru_load_context_data()
496 save += gru_copy_handle(cbe + i * GRU_HANDLE_STRIDE, in gru_load_context_data()
497 save); in gru_load_context_data()
510 memcpy(gseg + GRU_DS_BASE, save, length); in gru_load_context_data()
515 static void gru_unload_context_data(void *save, void *grubase, int ctxnum, in gru_unload_context_data() argument
535 save += gru_copy_handle(save, cb); in gru_unload_context_data()
536 save += gru_copy_handle(save, cbe + i * GRU_HANDLE_STRIDE); in gru_unload_context_data()
539 memcpy(save, gseg + GRU_DS_BASE, length); in gru_unload_context_data()
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| /drivers/gpu/drm/radeon/ |
| D | rv515.c | 268 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) in rv515_mc_stop() argument
273 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL); in rv515_mc_stop()
274 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL); in rv515_mc_stop()
282 save->crtc_enabled[i] = true; in rv515_mc_stop()
305 save->crtc_enabled[i] = false; in rv515_mc_stop()
308 save->crtc_enabled[i] = false; in rv515_mc_stop()
335 if (save->crtc_enabled[i]) { in rv515_mc_stop()
350 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) in rv515_mc_resume() argument
379 if (save->crtc_enabled[i]) { in rv515_mc_resume()
421 if (save->crtc_enabled[i]) { in rv515_mc_resume()
[all …]
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| D | evergreen.h | 35 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
36 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
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| D | r520.c | 135 struct rv515_mc_save save; in r520_mc_program() local
138 rv515_mc_stop(rdev, &save); in r520_mc_program()
164 rv515_mc_resume(rdev, &save); in r520_mc_program()
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| D | r100.c | 2565 struct r100_mc_save save; in r100_asic_reset() local
2573 r100_mc_stop(rdev, &save); in r100_asic_reset()
2615 r100_mc_resume(rdev, &save); in r100_asic_reset()
2876 uint32_t save, tmp; in r100_pll_errata_after_data() local
2878 save = RREG32(RADEON_CLOCK_CNTL_INDEX); in r100_pll_errata_after_data()
2879 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); in r100_pll_errata_after_data()
2882 WREG32(RADEON_CLOCK_CNTL_INDEX, save); in r100_pll_errata_after_data()
3767 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) in r100_mc_stop() argument
3776 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); in r100_mc_stop()
3777 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); in r100_mc_stop()
[all …]
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| /drivers/mfd/ |
| D | sm501.c | 258 unsigned long save; in sm501_misc_control() local
261 spin_lock_irqsave(&sm->reg_lock, save); in sm501_misc_control()
273 spin_unlock_irqrestore(&sm->reg_lock, save); in sm501_misc_control()
292 unsigned long save; in sm501_modify_reg() local
294 spin_lock_irqsave(&sm->reg_lock, save); in sm501_modify_reg()
303 spin_unlock_irqrestore(&sm->reg_lock, save); in sm501_modify_reg()
925 unsigned long save; in sm501_gpio_set() local
931 spin_lock_irqsave(&smgpio->lock, save); in sm501_gpio_set()
941 spin_unlock_irqrestore(&smgpio->lock, save); in sm501_gpio_set()
950 unsigned long save; in sm501_gpio_input() local
[all …]
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| /drivers/spi/ |
| D | spidev.c | 417 u32 save = spi->mode; in spidev_ioctl() local
432 spi->mode = save; in spidev_ioctl()
440 u32 save = spi->mode; in spidev_ioctl() local
448 spi->mode = save; in spidev_ioctl()
457 u8 save = spi->bits_per_word; in spidev_ioctl() local
462 spi->bits_per_word = save; in spidev_ioctl()
470 u32 save = spi->max_speed_hz; in spidev_ioctl() local
479 spi->max_speed_hz = save; in spidev_ioctl()
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| /drivers/char/tpm/ |
| D | tpm-interface.c | 157 u8 save[TPM_HEADER_SIZE + 3*sizeof(u32)]; in tpm_transmit() local
161 const size_t save_size = min(sizeof(save), bufsiz); in tpm_transmit()
170 memcpy(save, buf, save_size); in tpm_transmit()
196 memcpy(buf, save, save_size); in tpm_transmit()
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| /drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| D | chang84.c | 77 u32 engn, save; in g84_fifo_chan_engine_fini() local
86 save = nvkm_mask(device, 0x002520, 0x0000003f, 1 << engn); in g84_fifo_chan_engine_fini()
92 nvkm_wr32(device, 0x002520, save); in g84_fifo_chan_engine_fini()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | cik.c | 1244 struct kv_reset_save_regs *save) in kv_save_regs_for_reset() argument
1246 save->gmcon_reng_execute = RREG32(mmGMCON_RENG_EXECUTE); in kv_save_regs_for_reset()
1247 save->gmcon_misc = RREG32(mmGMCON_MISC); in kv_save_regs_for_reset()
1248 save->gmcon_misc3 = RREG32(mmGMCON_MISC3); in kv_save_regs_for_reset()
1250 WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute & in kv_save_regs_for_reset()
1252 WREG32(mmGMCON_MISC, save->gmcon_misc & in kv_save_regs_for_reset()
1258 struct kv_reset_save_regs *save) in kv_restore_regs_for_reset() argument
1325 WREG32(mmGMCON_MISC3, save->gmcon_misc3); in kv_restore_regs_for_reset()
1326 WREG32(mmGMCON_MISC, save->gmcon_misc); in kv_restore_regs_for_reset()
1327 WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute); in kv_restore_regs_for_reset()
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| /drivers/net/wireless/broadcom/b43/ |
| D | phy_lcn.c | 64 u16 save[2]; in b43_radio_2064_channel_setup() local
79 save[0] = b43_radio_read(dev, 0x044); in b43_radio_2064_channel_setup()
80 save[1] = b43_radio_read(dev, 0x12b); in b43_radio_2064_channel_setup()
98 b43_radio_write(dev, 0x044, save[0]); in b43_radio_2064_channel_setup()
99 b43_radio_write(dev, 0x12b, save[1]); in b43_radio_2064_channel_setup()
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| /drivers/media/pci/bt8xx/ |
| D | bttv-gpio.c | 98 struct bttv_sub_device *sub, *save; in bttv_sub_del_devices() local
100 list_for_each_entry_safe(sub, save, &core->subs, list) { in bttv_sub_del_devices()
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| /drivers/comedi/drivers/ni_routing/tools/ |
| D | convert_csv_to_c.py | 277 def save(self): member in DeviceRoutes
466 def save(self): member in RouteValues
496 doc.save()
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| /drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/ |
| D | gpc.fuc | 285 // save context size, and tell HUB we're done
398 // $p1 clear on save, set on load
400 // on save it means: "a load will follow this save"
401 // on load it means: "a save preceeded this load"
477 // if load, or a save without a load following, do some
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| /drivers/memory/ |
| D | ti-emif-sram-pm.S | 50 stmfd sp!, {r4 - r11, lr} @ save registers on stack
296 stmfd sp!, {r4 - r11, lr} @ save registers on stack
353 stmfd sp!, {r4 - r11, lr} @ save registers on stack
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