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Searched refs:sdhci_readl (Results 1 – 24 of 24) sorted by relevance

/drivers/mmc/host/
Dsdhci-of-esdhc.c536 value = sdhci_readl(host, ESDHC_DMA_SYSCTL); in esdhc_of_enable_dma()
588 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_clock_enable()
605 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE) in esdhc_clock_enable()
621 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); in esdhc_flush_async_fifo()
630 if (!(sdhci_readl(host, ESDHC_DMA_SYSCTL) & in esdhc_flush_async_fifo()
712 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_of_set_clock()
726 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE) in esdhc_of_set_clock()
739 temp = sdhci_readl(host, ESDHC_TBCTL); in esdhc_of_set_clock()
741 temp = sdhci_readl(host, ESDHC_SDCLKCTL); in esdhc_of_set_clock()
745 temp = sdhci_readl(host, ESDHC_DLLCFG0); in esdhc_of_set_clock()
[all …]
Dsdhci-xenon-phy.c235 reg = sdhci_readl(host, phy_regs->timing_adj); in xenon_emmc_phy_init()
265 reg = sdhci_readl(host, phy_regs->timing_adj); in xenon_emmc_phy_init()
331 reg = sdhci_readl(host, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
336 reg = sdhci_readl(host, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
392 reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL); in xenon_emmc_phy_config_tuning()
402 reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL); in xenon_emmc_phy_config_tuning()
420 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_disable_strobe()
426 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL); in xenon_emmc_phy_disable_strobe()
430 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1); in xenon_emmc_phy_disable_strobe()
454 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_strobe_delay_adj()
[all …]
Dsdhci-xenon.c30 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_enable_internal_clk()
58 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_set_sdclk_off_idle()
74 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_set_acg()
88 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_enable_sdhc()
106 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_disable_sdhc()
117 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); in xenon_enable_sdhc_parallel_tran()
127 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); in xenon_mask_cmd_conflict_err()
139 reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL); in xenon_retune_setup()
144 reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); in xenon_retune_setup()
147 reg = sdhci_readl(host, SDHCI_INT_ENABLE); in xenon_retune_setup()
[all …]
Dsdhci-bcm-kona.c67 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
71 while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) { in sdhci_bcm_kona_sd_reset()
79 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
99 val = sdhci_readl(host, KONA_SDHOST_COREIMR); in sdhci_bcm_kona_sd_init()
104 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_init()
138 val = sdhci_readl(host, KONA_SDHOST_CORESTAT); in sdhci_bcm_kona_sd_card_emulate()
Dsdhci_f_sdh30.c42 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
54 ctrl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_soft_voltage_switch()
59 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING); in sdhci_f_sdh30_soft_voltage_switch()
80 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_reset()
159 reg = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_probe()
164 reg = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_f_sdh30_probe()
Dsdhci-pci-gli.c154 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); in gl9750_wt_on()
171 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); in gl9750_wt_off()
195 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); in gli_set_9750()
196 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gli_set_9750()
197 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); in gli_set_9750()
198 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); in gli_set_9750()
199 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); in gli_set_9750()
200 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); in gli_set_9750()
283 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); in gli_set_9750_rx_inv()
355 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gl9750_disable_ssc_pll()
[all …]
Dsdhci-pci-dwc-mshc.c39 reg = sdhci_readl(host, (SDHC_AT_CTRL_R + vendor_ptr)); in sdhci_snps_set_clock()
47 reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
63 reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
Dsdhci-milbeaut.c65 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_soft_voltage_switch()
75 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING); in sdhci_milbeaut_soft_voltage_switch()
118 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_milbeaut_reset()
149 val = sdhci_readl(host, MLB_CR_SET); in sdhci_milbeaut_bridge_init()
181 ctl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_vendor_init()
196 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_milbeaut_vendor_init()
Dsdhci-brcmstb.c47 reg = sdhci_readl(host, SDHCI_VENDOR); in enable_clock_gating()
134 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_brcmstb_cqe_enable()
136 sdhci_readl(host, SDHCI_BUFFER); in sdhci_brcmstb_cqe_enable()
137 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_brcmstb_cqe_enable()
323 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_brcmstb_probe()
326 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); in sdhci_brcmstb_probe()
Dsdhci-tegra.c347 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_set_tap()
374 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); in tegra_sdhci_reset()
375 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_reset()
406 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); in tegra_sdhci_reset()
425 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); in tegra_sdhci_configure_cal_pad()
443 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_set_pad_autocal_offset()
488 reg = sdhci_readl(host, in tegra_sdhci_set_padctrl()
552 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
570 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
786 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); in tegra_sdhci_hs400_enhanced_strobe()
[all …]
Dsdhci-pci-o2micro.c84 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_o2_wait_card_detect_stable()
106 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
140 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
154 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); in sdhci_o2_get_cd()
173 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_pll_dll_wdt_control()
253 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_dll_recovery()
572 caps = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_pci_o2_probe_slot()
587 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); in sdhci_pci_o2_probe_slot()
623 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); in sdhci_pci_o2_probe_slot()
Dsdhci-sprd.c109 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); in sdhci_sprd_init_config()
183 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); in sdhci_sprd_set_dll_invert()
227 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); in _sdhci_sprd_set_clock()
247 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
253 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
260 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
665 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_sprd_probe()
666 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); in sdhci_sprd_probe()
Dsdhci.c61 sdhci_readl(host, SDHCI_DMA_ADDRESS), in sdhci_dumpregs()
67 sdhci_readl(host, SDHCI_ARGUMENT), in sdhci_dumpregs()
70 sdhci_readl(host, SDHCI_PRESENT_STATE), in sdhci_dumpregs()
80 sdhci_readl(host, SDHCI_INT_STATUS)); in sdhci_dumpregs()
82 sdhci_readl(host, SDHCI_INT_ENABLE), in sdhci_dumpregs()
83 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); in sdhci_dumpregs()
88 sdhci_readl(host, SDHCI_CAPABILITIES), in sdhci_dumpregs()
89 sdhci_readl(host, SDHCI_CAPABILITIES_1)); in sdhci_dumpregs()
92 sdhci_readl(host, SDHCI_MAX_CURRENT)); in sdhci_dumpregs()
94 sdhci_readl(host, SDHCI_RESPONSE), in sdhci_dumpregs()
[all …]
Dsdhci-of-sparx5.c236 mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_VERSION)); in sdhci_sparx5_probe()
238 mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_TYPE)); in sdhci_sparx5_probe()
Dsdhci-of-arasan.c348 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); in sdhci_arasan_hs400_enhanced_strobe()
427 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_arasan_cqe_enable()
429 sdhci_readl(host, SDHCI_BUFFER); in sdhci_arasan_cqe_enable()
430 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_arasan_cqe_enable()
796 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER); in sdhci_versal_sdcardclk_set_phase()
863 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
Dsdhci-of-dwcmshc.c168 vendor = sdhci_readl(host, reg); in dwcmshc_hs400_enhanced_strobe()
212 extra = sdhci_readl(host, reg); in dwcmshc_rk3568_set_clock()
436 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK; in dwcmshc_probe()
Dsdhci-acpi.c377 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); in bxt_get_cd()
391 sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 && in intel_probe_slot()
392 sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807) in intel_probe_slot()
1016 dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0); in sdhci_acpi_remove()
Dsdhci-of-at91.c126 u32 calcr = sdhci_readl(host, SDMMC_CALCR); in sdhci_at91_reset()
131 if (read_poll_timeout(sdhci_readl, tmp, !(tmp & SDMMC_CALCR_EN), in sdhci_at91_reset()
Dsdhci-pxav3.c129 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); in armada_38x_quirks()
130 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); in armada_38x_quirks()
Dsdhci-esdhc-imx.c915 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_pltfm_set_clock()
943 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_pltfm_set_clock()
1476 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in esdhc_cqe_enable()
1478 sdhci_readl(host, SDHCI_BUFFER); in esdhc_cqe_enable()
1479 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in esdhc_cqe_enable()
Dsdhci.h708 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function
749 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function
Dsdhci-pci-core.c630 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); in sdhci_get_cd_nogpio()
714 val = sdhci_readl(host, INTEL_HS400_ES_REG); in intel_hs400_enhanced_strobe()
1073 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); in glk_rpm_retune_wa()
1074 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); in glk_rpm_retune_wa()
1831 return sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_read_present_state()
Dsdhci-of-aspeed.c102 cap_val = sdhci_readl(host, 0x40 + (cap_reg * 4)); in aspeed_sdc_set_slot_capability()
Dsdhci-msm.c2083 ctrl = sdhci_readl(host, SDHCI_INT_ENABLE); in sdhci_msm_cqe_disable()