1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2019 Genesys Logic, Inc.
4 *
5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw>
6 *
7 * Version: v0.9.0 (2019-08-08)
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/pci.h>
13 #include <linux/mmc/mmc.h>
14 #include <linux/delay.h>
15 #include <linux/of.h>
16 #include "sdhci.h"
17 #include "sdhci-pci.h"
18 #include "cqhci.h"
19
20 /* Genesys Logic extra registers */
21 #define SDHCI_GLI_9750_WT 0x800
22 #define SDHCI_GLI_9750_WT_EN BIT(0)
23 #define GLI_9750_WT_EN_ON 0x1
24 #define GLI_9750_WT_EN_OFF 0x0
25
26 #define PCI_GLI_9750_PM_CTRL 0xFC
27 #define PCI_GLI_9750_PM_STATE GENMASK(1, 0)
28
29 #define PCI_GLI_9750_CORRERR_MASK 0x214
30 #define PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT BIT(12)
31
32 #define SDHCI_GLI_9750_CFG2 0x848
33 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24)
34 #define GLI_9750_CFG2_L1DLY_VALUE 0x1F
35
36 #define SDHCI_GLI_9750_DRIVING 0x860
37 #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0)
38 #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26)
39 #define GLI_9750_DRIVING_1_VALUE 0xFFF
40 #define GLI_9750_DRIVING_2_VALUE 0x3
41 #define SDHCI_GLI_9750_SEL_1 BIT(29)
42 #define SDHCI_GLI_9750_SEL_2 BIT(31)
43 #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30))
44
45 #define SDHCI_GLI_9750_PLL 0x864
46 #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0)
47 #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12)
48 #define SDHCI_GLI_9750_PLL_DIR BIT(15)
49 #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23)
50 #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20)
51 #define GLI_9750_PLL_TX2_INV_VALUE 0x1
52 #define GLI_9750_PLL_TX2_DLY_VALUE 0x0
53 #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24)
54 #define SDHCI_GLI_9750_PLLSSC_EN BIT(31)
55
56 #define SDHCI_GLI_9750_PLLSSC 0x86C
57 #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16)
58
59 #define SDHCI_GLI_9750_SW_CTRL 0x874
60 #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6)
61 #define GLI_9750_SW_CTRL_4_VALUE 0x3
62
63 #define SDHCI_GLI_9750_MISC 0x878
64 #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2)
65 #define SDHCI_GLI_9750_MISC_RX_INV BIT(3)
66 #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4)
67 #define GLI_9750_MISC_TX1_INV_VALUE 0x0
68 #define GLI_9750_MISC_RX_INV_ON 0x1
69 #define GLI_9750_MISC_RX_INV_OFF 0x0
70 #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF
71 #define GLI_9750_MISC_TX1_DLY_VALUE 0x5
72
73 #define SDHCI_GLI_9750_TUNING_CONTROL 0x540
74 #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4)
75 #define GLI_9750_TUNING_CONTROL_EN_ON 0x1
76 #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0
77 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16)
78 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19)
79 #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1
80 #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2
81
82 #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544
83 #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0)
84 #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1
85
86 #define SDHCI_GLI_9763E_CTRL_HS400 0x7
87
88 #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C
89 #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8)
90
91 #define PCIE_GLI_9763E_VHS 0x884
92 #define GLI_9763E_VHS_REV GENMASK(19, 16)
93 #define GLI_9763E_VHS_REV_R 0x0
94 #define GLI_9763E_VHS_REV_M 0x1
95 #define GLI_9763E_VHS_REV_W 0x2
96 #define PCIE_GLI_9763E_MB 0x888
97 #define GLI_9763E_MB_CMDQ_OFF BIT(19)
98 #define GLI_9763E_MB_ERP_ON BIT(7)
99 #define PCIE_GLI_9763E_SCR 0x8E0
100 #define GLI_9763E_SCR_AXI_REQ BIT(9)
101
102 #define PCIE_GLI_9763E_CFG2 0x8A4
103 #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19)
104 #define GLI_9763E_CFG2_L1DLY_MID 0x54
105
106 #define PCIE_GLI_9763E_MMC_CTRL 0x960
107 #define GLI_9763E_HS400_SLOW BIT(3)
108
109 #define PCIE_GLI_9763E_CLKRXDLY 0x934
110 #define GLI_9763E_HS400_RXDLY GENMASK(31, 28)
111 #define GLI_9763E_HS400_RXDLY_5 0x5
112
113 #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200
114 #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
115 SDHCI_TRNS_BLK_CNT_EN | \
116 SDHCI_TRNS_DMA)
117
118 #define PCI_GLI_9755_WT 0x800
119 #define PCI_GLI_9755_WT_EN BIT(0)
120 #define GLI_9755_WT_EN_ON 0x1
121 #define GLI_9755_WT_EN_OFF 0x0
122
123 #define PCI_GLI_9755_PECONF 0x44
124 #define PCI_GLI_9755_LFCLK GENMASK(14, 12)
125 #define PCI_GLI_9755_DMACLK BIT(29)
126 #define PCI_GLI_9755_INVERT_CD BIT(30)
127 #define PCI_GLI_9755_INVERT_WP BIT(31)
128
129 #define PCI_GLI_9755_CFG2 0x48
130 #define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24)
131 #define GLI_9755_CFG2_L1DLY_VALUE 0x1F
132
133 #define PCI_GLI_9755_PLL 0x64
134 #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0)
135 #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12)
136 #define PCI_GLI_9755_PLL_DIR BIT(15)
137 #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24)
138 #define PCI_GLI_9755_PLLSSC_EN BIT(31)
139
140 #define PCI_GLI_9755_PLLSSC 0x68
141 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0)
142
143 #define PCI_GLI_9755_SerDes 0x70
144 #define PCI_GLI_9755_SCP_DIS BIT(19)
145
146 #define GLI_MAX_TUNING_LOOP 40
147
148 /* Genesys Logic chipset */
gl9750_wt_on(struct sdhci_host * host)149 static inline void gl9750_wt_on(struct sdhci_host *host)
150 {
151 u32 wt_value;
152 u32 wt_enable;
153
154 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
155 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
156
157 if (wt_enable == GLI_9750_WT_EN_ON)
158 return;
159
160 wt_value &= ~SDHCI_GLI_9750_WT_EN;
161 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON);
162
163 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
164 }
165
gl9750_wt_off(struct sdhci_host * host)166 static inline void gl9750_wt_off(struct sdhci_host *host)
167 {
168 u32 wt_value;
169 u32 wt_enable;
170
171 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
172 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
173
174 if (wt_enable == GLI_9750_WT_EN_OFF)
175 return;
176
177 wt_value &= ~SDHCI_GLI_9750_WT_EN;
178 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF);
179
180 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
181 }
182
gli_set_9750(struct sdhci_host * host)183 static void gli_set_9750(struct sdhci_host *host)
184 {
185 u32 driving_value;
186 u32 pll_value;
187 u32 sw_ctrl_value;
188 u32 misc_value;
189 u32 parameter_value;
190 u32 control_value;
191 u16 ctrl2;
192
193 gl9750_wt_on(host);
194
195 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
196 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
197 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);
198 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
199 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);
200 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
201
202 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1);
203 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2);
204 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1,
205 GLI_9750_DRIVING_1_VALUE);
206 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2,
207 GLI_9750_DRIVING_2_VALUE);
208 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST);
209 driving_value |= SDHCI_GLI_9750_SEL_2;
210 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);
211
212 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4;
213 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4,
214 GLI_9750_SW_CTRL_4_VALUE);
215 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);
216
217 /* reset the tuning flow after reinit and before starting tuning */
218 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV;
219 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY;
220 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV,
221 GLI_9750_PLL_TX2_INV_VALUE);
222 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY,
223 GLI_9750_PLL_TX2_DLY_VALUE);
224
225 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV;
226 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
227 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY;
228 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV,
229 GLI_9750_MISC_TX1_INV_VALUE);
230 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
231 GLI_9750_MISC_RX_INV_VALUE);
232 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY,
233 GLI_9750_MISC_TX1_DLY_VALUE);
234
235 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY;
236 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY,
237 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE);
238
239 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1;
240 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2;
241 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1,
242 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE);
243 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2,
244 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE);
245
246 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);
247 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
248
249 /* disable tuned clk */
250 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
251 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
252 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
253
254 /* enable tuning parameters control */
255 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
256 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
257 GLI_9750_TUNING_CONTROL_EN_ON);
258 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
259
260 /* write tuning parameters */
261 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);
262
263 /* disable tuning parameters control */
264 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
265 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
266 GLI_9750_TUNING_CONTROL_EN_OFF);
267 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
268
269 /* clear tuned clk */
270 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
271 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
272 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
273
274 gl9750_wt_off(host);
275 }
276
gli_set_9750_rx_inv(struct sdhci_host * host,bool b)277 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)
278 {
279 u32 misc_value;
280
281 gl9750_wt_on(host);
282
283 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
284 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
285 if (b) {
286 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
287 GLI_9750_MISC_RX_INV_ON);
288 } else {
289 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
290 GLI_9750_MISC_RX_INV_OFF);
291 }
292 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
293
294 gl9750_wt_off(host);
295 }
296
__sdhci_execute_tuning_9750(struct sdhci_host * host,u32 opcode)297 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)
298 {
299 int i;
300 int rx_inv;
301
302 for (rx_inv = 0; rx_inv < 2; rx_inv++) {
303 gli_set_9750_rx_inv(host, !!rx_inv);
304 sdhci_start_tuning(host);
305
306 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) {
307 u16 ctrl;
308
309 sdhci_send_tuning(host, opcode);
310
311 if (!host->tuning_done) {
312 sdhci_abort_tuning(host, opcode);
313 break;
314 }
315
316 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
317 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
318 if (ctrl & SDHCI_CTRL_TUNED_CLK)
319 return 0; /* Success! */
320 break;
321 }
322 }
323 }
324 if (!host->tuning_done) {
325 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
326 mmc_hostname(host->mmc));
327 return -ETIMEDOUT;
328 }
329
330 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
331 mmc_hostname(host->mmc));
332 sdhci_reset_tuning(host);
333
334 return -EAGAIN;
335 }
336
gl9750_execute_tuning(struct sdhci_host * host,u32 opcode)337 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
338 {
339 host->mmc->retune_period = 0;
340 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
341 host->mmc->retune_period = host->tuning_count;
342
343 gli_set_9750(host);
344 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);
345 sdhci_end_tuning(host);
346
347 return 0;
348 }
349
gl9750_disable_ssc_pll(struct sdhci_host * host)350 static void gl9750_disable_ssc_pll(struct sdhci_host *host)
351 {
352 u32 pll;
353
354 gl9750_wt_on(host);
355 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
356 pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN);
357 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
358 gl9750_wt_off(host);
359 }
360
gl9750_set_pll(struct sdhci_host * host,u8 dir,u16 ldiv,u8 pdiv)361 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
362 {
363 u32 pll;
364
365 gl9750_wt_on(host);
366 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
367 pll &= ~(SDHCI_GLI_9750_PLL_LDIV |
368 SDHCI_GLI_9750_PLL_PDIV |
369 SDHCI_GLI_9750_PLL_DIR);
370 pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) |
371 FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) |
372 FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir);
373 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
374 gl9750_wt_off(host);
375
376 /* wait for pll stable */
377 mdelay(1);
378 }
379
gl9750_set_ssc(struct sdhci_host * host,u8 enable,u8 step,u16 ppm)380 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
381 {
382 u32 pll;
383 u32 ssc;
384
385 gl9750_wt_on(host);
386 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
387 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);
388 pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP |
389 SDHCI_GLI_9750_PLLSSC_EN);
390 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;
391 pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) |
392 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable);
393 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);
394 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);
395 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
396 gl9750_wt_off(host);
397 }
398
gl9750_set_ssc_pll_205mhz(struct sdhci_host * host)399 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
400 {
401 /* set pll to 205MHz and enable ssc */
402 gl9750_set_ssc(host, 0x1, 0x1F, 0xFFE7);
403 gl9750_set_pll(host, 0x1, 0x246, 0x0);
404 }
405
sdhci_gl9750_set_clock(struct sdhci_host * host,unsigned int clock)406 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)
407 {
408 struct mmc_ios *ios = &host->mmc->ios;
409 u16 clk;
410
411 host->mmc->actual_clock = 0;
412
413 gl9750_disable_ssc_pll(host);
414 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
415
416 if (clock == 0)
417 return;
418
419 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
420 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
421 host->mmc->actual_clock = 205000000;
422 gl9750_set_ssc_pll_205mhz(host);
423 }
424
425 sdhci_enable_clk(host, clk);
426 }
427
gl9750_hw_setting(struct sdhci_host * host)428 static void gl9750_hw_setting(struct sdhci_host *host)
429 {
430 struct sdhci_pci_slot *slot = sdhci_priv(host);
431 struct pci_dev *pdev;
432 u32 value;
433
434 pdev = slot->chip->pdev;
435
436 gl9750_wt_on(host);
437
438 value = sdhci_readl(host, SDHCI_GLI_9750_CFG2);
439 value &= ~SDHCI_GLI_9750_CFG2_L1DLY;
440 /* set ASPM L1 entry delay to 7.9us */
441 value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY,
442 GLI_9750_CFG2_L1DLY_VALUE);
443 sdhci_writel(host, value, SDHCI_GLI_9750_CFG2);
444
445 /* toggle PM state to allow GL9750 to enter ASPM L1.2 */
446 pci_read_config_dword(pdev, PCI_GLI_9750_PM_CTRL, &value);
447 value |= PCI_GLI_9750_PM_STATE;
448 pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
449 value &= ~PCI_GLI_9750_PM_STATE;
450 pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
451
452 /* mask the replay timer timeout of AER */
453 pci_read_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, &value);
454 value |= PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;
455 pci_write_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, value);
456
457 gl9750_wt_off(host);
458 }
459
gli_pcie_enable_msi(struct sdhci_pci_slot * slot)460 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
461 {
462 int ret;
463
464 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1,
465 PCI_IRQ_MSI | PCI_IRQ_MSIX);
466 if (ret < 0) {
467 pr_warn("%s: enable PCI MSI failed, error=%d\n",
468 mmc_hostname(slot->host->mmc), ret);
469 return;
470 }
471
472 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
473 }
474
gl9755_wt_on(struct pci_dev * pdev)475 static inline void gl9755_wt_on(struct pci_dev *pdev)
476 {
477 u32 wt_value;
478 u32 wt_enable;
479
480 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
481 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
482
483 if (wt_enable == GLI_9755_WT_EN_ON)
484 return;
485
486 wt_value &= ~PCI_GLI_9755_WT_EN;
487 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON);
488
489 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
490 }
491
gl9755_wt_off(struct pci_dev * pdev)492 static inline void gl9755_wt_off(struct pci_dev *pdev)
493 {
494 u32 wt_value;
495 u32 wt_enable;
496
497 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
498 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
499
500 if (wt_enable == GLI_9755_WT_EN_OFF)
501 return;
502
503 wt_value &= ~PCI_GLI_9755_WT_EN;
504 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF);
505
506 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
507 }
508
gl9755_disable_ssc_pll(struct pci_dev * pdev)509 static void gl9755_disable_ssc_pll(struct pci_dev *pdev)
510 {
511 u32 pll;
512
513 gl9755_wt_on(pdev);
514 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
515 pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN);
516 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
517 gl9755_wt_off(pdev);
518 }
519
gl9755_set_pll(struct pci_dev * pdev,u8 dir,u16 ldiv,u8 pdiv)520 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
521 {
522 u32 pll;
523
524 gl9755_wt_on(pdev);
525 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
526 pll &= ~(PCI_GLI_9755_PLL_LDIV |
527 PCI_GLI_9755_PLL_PDIV |
528 PCI_GLI_9755_PLL_DIR);
529 pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) |
530 FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) |
531 FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir);
532 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
533 gl9755_wt_off(pdev);
534
535 /* wait for pll stable */
536 mdelay(1);
537 }
538
gl9755_set_ssc(struct pci_dev * pdev,u8 enable,u8 step,u16 ppm)539 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
540 {
541 u32 pll;
542 u32 ssc;
543
544 gl9755_wt_on(pdev);
545 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
546 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);
547 pll &= ~(PCI_GLI_9755_PLLSSC_STEP |
548 PCI_GLI_9755_PLLSSC_EN);
549 ssc &= ~PCI_GLI_9755_PLLSSC_PPM;
550 pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) |
551 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable);
552 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);
553 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);
554 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
555 gl9755_wt_off(pdev);
556 }
557
gl9755_set_ssc_pll_205mhz(struct pci_dev * pdev)558 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)
559 {
560 /* set pll to 205MHz and enable ssc */
561 gl9755_set_ssc(pdev, 0x1, 0x1F, 0xFFE7);
562 gl9755_set_pll(pdev, 0x1, 0x246, 0x0);
563 }
564
sdhci_gl9755_set_clock(struct sdhci_host * host,unsigned int clock)565 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
566 {
567 struct sdhci_pci_slot *slot = sdhci_priv(host);
568 struct mmc_ios *ios = &host->mmc->ios;
569 struct pci_dev *pdev;
570 u16 clk;
571
572 pdev = slot->chip->pdev;
573 host->mmc->actual_clock = 0;
574
575 gl9755_disable_ssc_pll(pdev);
576 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
577
578 if (clock == 0)
579 return;
580
581 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
582 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
583 host->mmc->actual_clock = 205000000;
584 gl9755_set_ssc_pll_205mhz(pdev);
585 }
586
587 sdhci_enable_clk(host, clk);
588 }
589
gl9755_hw_setting(struct sdhci_pci_slot * slot)590 static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
591 {
592 struct pci_dev *pdev = slot->chip->pdev;
593 u32 value;
594
595 gl9755_wt_on(pdev);
596
597 pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value);
598 /*
599 * Apple ARM64 platforms using these chips may have
600 * inverted CD/WP detection.
601 */
602 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted"))
603 value |= PCI_GLI_9755_INVERT_CD;
604 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted"))
605 value |= PCI_GLI_9755_INVERT_WP;
606 value &= ~PCI_GLI_9755_LFCLK;
607 value &= ~PCI_GLI_9755_DMACLK;
608 pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value);
609
610 /* enable short circuit protection */
611 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value);
612 value &= ~PCI_GLI_9755_SCP_DIS;
613 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value);
614
615 pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value);
616 value &= ~PCI_GLI_9755_CFG2_L1DLY;
617 /* set ASPM L1 entry delay to 7.9us */
618 value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY,
619 GLI_9755_CFG2_L1DLY_VALUE);
620 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
621
622 gl9755_wt_off(pdev);
623 }
624
gli_probe_slot_gl9750(struct sdhci_pci_slot * slot)625 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
626 {
627 struct sdhci_host *host = slot->host;
628
629 gl9750_hw_setting(host);
630 gli_pcie_enable_msi(slot);
631 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
632 sdhci_enable_v4_mode(host);
633
634 return 0;
635 }
636
gli_probe_slot_gl9755(struct sdhci_pci_slot * slot)637 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot)
638 {
639 struct sdhci_host *host = slot->host;
640
641 gl9755_hw_setting(slot);
642 gli_pcie_enable_msi(slot);
643 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
644 sdhci_enable_v4_mode(host);
645
646 return 0;
647 }
648
sdhci_gli_voltage_switch(struct sdhci_host * host)649 static void sdhci_gli_voltage_switch(struct sdhci_host *host)
650 {
651 /*
652 * According to Section 3.6.1 signal voltage switch procedure in
653 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
654 * follows:
655 * (6) Set 1.8V Signal Enable in the Host Control 2 register.
656 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
657 * period.
658 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
659 * step (12).
660 *
661 * Wait 5ms after set 1.8V signal enable in Host Control 2 register
662 * to ensure 1.8V signal enable bit is set by GL9750/GL9755.
663 *
664 * ...however, the controller in the NUC10i3FNK4 (a 9755) requires
665 * slightly longer than 5ms before the control register reports that
666 * 1.8V is ready, and far longer still before the card will actually
667 * work reliably.
668 */
669 usleep_range(100000, 110000);
670 }
671
sdhci_gl9750_reset(struct sdhci_host * host,u8 mask)672 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
673 {
674 sdhci_reset(host, mask);
675 gli_set_9750(host);
676 }
677
sdhci_gl9750_readl(struct sdhci_host * host,int reg)678 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)
679 {
680 u32 value;
681
682 value = readl(host->ioaddr + reg);
683 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff)))
684 value |= 0xc8;
685
686 return value;
687 }
688
689 #ifdef CONFIG_PM_SLEEP
sdhci_pci_gli_resume(struct sdhci_pci_chip * chip)690 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip)
691 {
692 struct sdhci_pci_slot *slot = chip->slots[0];
693
694 pci_free_irq_vectors(slot->chip->pdev);
695 gli_pcie_enable_msi(slot);
696
697 return sdhci_pci_resume_host(chip);
698 }
699
sdhci_cqhci_gli_resume(struct sdhci_pci_chip * chip)700 static int sdhci_cqhci_gli_resume(struct sdhci_pci_chip *chip)
701 {
702 struct sdhci_pci_slot *slot = chip->slots[0];
703 int ret;
704
705 ret = sdhci_pci_gli_resume(chip);
706 if (ret)
707 return ret;
708
709 return cqhci_resume(slot->host->mmc);
710 }
711
sdhci_cqhci_gli_suspend(struct sdhci_pci_chip * chip)712 static int sdhci_cqhci_gli_suspend(struct sdhci_pci_chip *chip)
713 {
714 struct sdhci_pci_slot *slot = chip->slots[0];
715 int ret;
716
717 ret = cqhci_suspend(slot->host->mmc);
718 if (ret)
719 return ret;
720
721 return sdhci_suspend_host(slot->host);
722 }
723 #endif
724
gl9763e_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)725 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc,
726 struct mmc_ios *ios)
727 {
728 struct sdhci_host *host = mmc_priv(mmc);
729 u32 val;
730
731 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG);
732 if (ios->enhanced_strobe)
733 val |= SDHCI_GLI_9763E_HS400_ES_BIT;
734 else
735 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT;
736
737 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);
738 }
739
sdhci_set_gl9763e_signaling(struct sdhci_host * host,unsigned int timing)740 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,
741 unsigned int timing)
742 {
743 u16 ctrl_2;
744
745 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
746 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
747 if (timing == MMC_TIMING_MMC_HS200)
748 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
749 else if (timing == MMC_TIMING_MMC_HS)
750 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
751 else if (timing == MMC_TIMING_MMC_DDR52)
752 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
753 else if (timing == MMC_TIMING_MMC_HS400)
754 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400;
755
756 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
757 }
758
sdhci_gl9763e_dumpregs(struct mmc_host * mmc)759 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc)
760 {
761 sdhci_dumpregs(mmc_priv(mmc));
762 }
763
sdhci_gl9763e_cqe_pre_enable(struct mmc_host * mmc)764 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc)
765 {
766 struct cqhci_host *cq_host = mmc->cqe_private;
767 u32 value;
768
769 value = cqhci_readl(cq_host, CQHCI_CFG);
770 value |= CQHCI_ENABLE;
771 cqhci_writel(cq_host, value, CQHCI_CFG);
772 }
773
sdhci_gl9763e_cqe_enable(struct mmc_host * mmc)774 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc)
775 {
776 struct sdhci_host *host = mmc_priv(mmc);
777
778 sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
779 sdhci_cqe_enable(mmc);
780 }
781
sdhci_gl9763e_cqhci_irq(struct sdhci_host * host,u32 intmask)782 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask)
783 {
784 int cmd_error = 0;
785 int data_error = 0;
786
787 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
788 return intmask;
789
790 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
791
792 return 0;
793 }
794
sdhci_gl9763e_cqe_post_disable(struct mmc_host * mmc)795 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc)
796 {
797 struct sdhci_host *host = mmc_priv(mmc);
798 struct cqhci_host *cq_host = mmc->cqe_private;
799 u32 value;
800
801 value = cqhci_readl(cq_host, CQHCI_CFG);
802 value &= ~CQHCI_ENABLE;
803 cqhci_writel(cq_host, value, CQHCI_CFG);
804 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
805 }
806
807 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = {
808 .enable = sdhci_gl9763e_cqe_enable,
809 .disable = sdhci_cqe_disable,
810 .dumpregs = sdhci_gl9763e_dumpregs,
811 .pre_enable = sdhci_gl9763e_cqe_pre_enable,
812 .post_disable = sdhci_gl9763e_cqe_post_disable,
813 };
814
gl9763e_add_host(struct sdhci_pci_slot * slot)815 static int gl9763e_add_host(struct sdhci_pci_slot *slot)
816 {
817 struct device *dev = &slot->chip->pdev->dev;
818 struct sdhci_host *host = slot->host;
819 struct cqhci_host *cq_host;
820 bool dma64;
821 int ret;
822
823 ret = sdhci_setup_host(host);
824 if (ret)
825 return ret;
826
827 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
828 if (!cq_host) {
829 ret = -ENOMEM;
830 goto cleanup;
831 }
832
833 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR;
834 cq_host->ops = &sdhci_gl9763e_cqhci_ops;
835
836 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
837 if (dma64)
838 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
839
840 ret = cqhci_init(cq_host, host->mmc, dma64);
841 if (ret)
842 goto cleanup;
843
844 ret = __sdhci_add_host(host);
845 if (ret)
846 goto cleanup;
847
848 return 0;
849
850 cleanup:
851 sdhci_cleanup_host(host);
852 return ret;
853 }
854
sdhci_gl9763e_reset(struct sdhci_host * host,u8 mask)855 static void sdhci_gl9763e_reset(struct sdhci_host *host, u8 mask)
856 {
857 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) &&
858 host->mmc->cqe_private)
859 cqhci_deactivate(host->mmc);
860 sdhci_reset(host, mask);
861 }
862
gli_set_gl9763e(struct sdhci_pci_slot * slot)863 static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
864 {
865 struct pci_dev *pdev = slot->chip->pdev;
866 u32 value;
867
868 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
869 value &= ~GLI_9763E_VHS_REV;
870 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
871 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
872
873 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value);
874 value |= GLI_9763E_SCR_AXI_REQ;
875 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value);
876
877 pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value);
878 value &= ~GLI_9763E_HS400_SLOW;
879 pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value);
880
881 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);
882 value &= ~GLI_9763E_CFG2_L1DLY;
883 /* set ASPM L1 entry delay to 21us */
884 value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);
885 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
886
887 pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value);
888 value &= ~GLI_9763E_HS400_RXDLY;
889 value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5);
890 pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value);
891
892 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
893 value &= ~GLI_9763E_VHS_REV;
894 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
895 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
896 }
897
gli_probe_slot_gl9763e(struct sdhci_pci_slot * slot)898 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
899 {
900 struct pci_dev *pdev = slot->chip->pdev;
901 struct sdhci_host *host = slot->host;
902 u32 value;
903
904 host->mmc->caps |= MMC_CAP_8_BIT_DATA |
905 MMC_CAP_1_8V_DDR |
906 MMC_CAP_NONREMOVABLE;
907 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR |
908 MMC_CAP2_HS400_1_8V |
909 MMC_CAP2_HS400_ES |
910 MMC_CAP2_NO_SDIO |
911 MMC_CAP2_NO_SD;
912
913 pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value);
914 if (!(value & GLI_9763E_MB_CMDQ_OFF))
915 if (value & GLI_9763E_MB_ERP_ON)
916 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
917
918 gli_pcie_enable_msi(slot);
919 host->mmc_host_ops.hs400_enhanced_strobe =
920 gl9763e_hs400_enhanced_strobe;
921 gli_set_gl9763e(slot);
922 sdhci_enable_v4_mode(host);
923
924 return 0;
925 }
926
927 static const struct sdhci_ops sdhci_gl9755_ops = {
928 .set_clock = sdhci_gl9755_set_clock,
929 .enable_dma = sdhci_pci_enable_dma,
930 .set_bus_width = sdhci_set_bus_width,
931 .reset = sdhci_reset,
932 .set_uhs_signaling = sdhci_set_uhs_signaling,
933 .voltage_switch = sdhci_gli_voltage_switch,
934 };
935
936 const struct sdhci_pci_fixes sdhci_gl9755 = {
937 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
938 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
939 .probe_slot = gli_probe_slot_gl9755,
940 .ops = &sdhci_gl9755_ops,
941 #ifdef CONFIG_PM_SLEEP
942 .resume = sdhci_pci_gli_resume,
943 #endif
944 };
945
946 static const struct sdhci_ops sdhci_gl9750_ops = {
947 .read_l = sdhci_gl9750_readl,
948 .set_clock = sdhci_gl9750_set_clock,
949 .enable_dma = sdhci_pci_enable_dma,
950 .set_bus_width = sdhci_set_bus_width,
951 .reset = sdhci_gl9750_reset,
952 .set_uhs_signaling = sdhci_set_uhs_signaling,
953 .voltage_switch = sdhci_gli_voltage_switch,
954 .platform_execute_tuning = gl9750_execute_tuning,
955 };
956
957 const struct sdhci_pci_fixes sdhci_gl9750 = {
958 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
959 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
960 .probe_slot = gli_probe_slot_gl9750,
961 .ops = &sdhci_gl9750_ops,
962 #ifdef CONFIG_PM_SLEEP
963 .resume = sdhci_pci_gli_resume,
964 #endif
965 };
966
967 static const struct sdhci_ops sdhci_gl9763e_ops = {
968 .set_clock = sdhci_set_clock,
969 .enable_dma = sdhci_pci_enable_dma,
970 .set_bus_width = sdhci_set_bus_width,
971 .reset = sdhci_gl9763e_reset,
972 .set_uhs_signaling = sdhci_set_gl9763e_signaling,
973 .voltage_switch = sdhci_gli_voltage_switch,
974 .irq = sdhci_gl9763e_cqhci_irq,
975 };
976
977 const struct sdhci_pci_fixes sdhci_gl9763e = {
978 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
979 .probe_slot = gli_probe_slot_gl9763e,
980 .ops = &sdhci_gl9763e_ops,
981 #ifdef CONFIG_PM_SLEEP
982 .resume = sdhci_cqhci_gli_resume,
983 .suspend = sdhci_cqhci_gli_suspend,
984 #endif
985 .add_host = gl9763e_add_host,
986 };
987