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/drivers/soc/qcom/
Dqcom-geni-se.c184 u32 geni_se_get_qup_hw_version(struct geni_se *se) in geni_se_get_qup_hw_version() argument
186 struct geni_wrapper *wrapper = se->wrapper; in geni_se_get_qup_hw_version()
225 static void geni_se_irq_clear(struct geni_se *se) in geni_se_irq_clear() argument
227 writel_relaxed(0, se->base + SE_GSI_EVENT_EN); in geni_se_irq_clear()
228 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR); in geni_se_irq_clear()
229 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR); in geni_se_irq_clear()
230 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR); in geni_se_irq_clear()
231 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR); in geni_se_irq_clear()
232 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN); in geni_se_irq_clear()
244 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr) in geni_se_init() argument
[all …]
DMakefile4 obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
/drivers/i2c/busses/
Di2c-qcom-geni.c76 struct geni_se se; member
157 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); in qcom_geni_i2c_conf()
160 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG); in qcom_geni_i2c_conf()
165 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); in qcom_geni_i2c_conf()
170 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0); in geni_i2c_err_misc()
171 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); in geni_i2c_err_misc()
172 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS); in geni_i2c_err_misc()
173 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS); in geni_i2c_err_misc()
174 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN); in geni_i2c_err_misc()
178 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); in geni_i2c_err_misc()
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/drivers/spi/
Dspi-geni-qcom.c67 struct geni_se se; member
98 ret = geni_se_clk_freq_match(&mas->se, in get_spi_clk_cfg()
126 struct geni_se *se = &mas->se; in handle_fifo_timeout() local
130 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in handle_fifo_timeout()
132 geni_se_cancel_m_cmd(se); in handle_fifo_timeout()
141 geni_se_abort_m_cmd(se); in handle_fifo_timeout()
158 struct geni_se *se = &mas->se; in spi_geni_is_abort_still_pending() local
171 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); in spi_geni_is_abort_still_pending()
172 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); in spi_geni_is_abort_still_pending()
194 struct geni_se *se = &mas->se; in spi_geni_set_cs() local
[all …]
/drivers/gpu/drm/amd/amdkfd/
Dkfd_mqd_manager.c102 int i, se, sh, cu; in mqd_symmetrically_map_cu_mask() local
131 for (se = 0; se < cu_info.num_shader_engines; se++) in mqd_symmetrically_map_cu_mask()
133 cu_per_sh[se][sh] = hweight32(cu_info.cu_bitmap[se % 4][sh + (se / 4)]); in mqd_symmetrically_map_cu_mask()
164 for (se = 0; se < cu_info.num_shader_engines; se++) { in mqd_symmetrically_map_cu_mask()
165 if (cu_per_sh[se][sh] > cu) { in mqd_symmetrically_map_cu_mask()
167 se_mask[se] |= 1 << (cu + sh * 16); in mqd_symmetrically_map_cu_mask()
/drivers/tty/serial/
Dqcom_geni_serial.c133 struct geni_se se; member
218 port->se.base = uport->membase; in qcom_geni_serial_request_port()
506 geni_se_cancel_m_cmd(&port->se); in qcom_geni_serial_console_write()
509 geni_se_abort_m_cmd(&port->se); in qcom_geni_serial_console_write()
642 geni_se_cancel_m_cmd(&port->se); in qcom_geni_serial_stop_tx()
645 geni_se_abort_m_cmd(&port->se); in qcom_geni_serial_stop_tx()
663 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); in qcom_geni_serial_start_rx()
694 geni_se_cancel_s_cmd(&port->se); in qcom_geni_serial_stop_rx()
888 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); in setup_fifos()
889 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); in setup_fifos()
[all …]
/drivers/gpu/drm/i915/gvt/
Dgtt.c1136 static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se, in ppgtt_generate_shadow_entry() argument
1141 se->type = ge->type; in ppgtt_generate_shadow_entry()
1142 se->val64 = ge->val64; in ppgtt_generate_shadow_entry()
1145 if (se->type == GTT_TYPE_PPGTT_PDE_ENTRY) in ppgtt_generate_shadow_entry()
1146 ops->clear_ips(se); in ppgtt_generate_shadow_entry()
1148 ops->set_pfn(se, s->shadow_page.mfn); in ppgtt_generate_shadow_entry()
1177 struct intel_gvt_gtt_entry *se) in split_2MB_gtt_entry() argument
1189 start_gfn = ops->get_pfn(se); in split_2MB_gtt_entry()
1200 sub_se.val64 = se->val64; in split_2MB_gtt_entry()
1204 sub_se.val64 |= (se->val64 & _PAGE_PAT_LARGE) >> 5; in split_2MB_gtt_entry()
[all …]
/drivers/infiniband/hw/hfi1/
Dtrace_ibhdrs.h76 u8 *se, u8 *pad, u8 *opcode, u8 *tver,
83 u8 *pad, u8 *se, u8 *tver,
99 u8 se, u8 pad, u8 opcode, const char *opname,
135 __field(u8, se)
182 &__entry->se,
203 &__entry->se,
249 __entry->se,
294 __field(u8, se)
347 &__entry->se,
371 &__entry->se,
[all …]
Dtrace.c119 u8 *se, u8 *pad, u8 *opcode, u8 *tver, in hfi1_trace_parse_9b_bth() argument
126 *se = ib_bth_get_se(ohdr); in hfi1_trace_parse_9b_bth()
137 u8 *pad, u8 *se, u8 *tver, in hfi1_trace_parse_16b_bth() argument
144 *se = ib_bth_get_se(ohdr); in hfi1_trace_parse_16b_bth()
223 u8 se, u8 pad, u8 opcode, const char *opname, in hfi1_trace_fmt_rest() argument
236 se, mig, pad, tver, qpn, ack, psn); in hfi1_trace_fmt_rest()
241 se, mig, pad, tver, pkey, fecn, becn, in hfi1_trace_fmt_rest()
/drivers/s390/net/
Dsmsgiucv_app.c123 struct smsg_app_event *se; in smsg_app_callback() local
138 se = smsg_app_event_alloc(from, msg); in smsg_app_callback()
139 if (!se) in smsg_app_callback()
144 list_add_tail(&se->list, &smsg_event_queue); in smsg_app_callback()
/drivers/infiniband/sw/rxe/
Drxe_hdr.h105 static inline void __bth_set_se(void *arg, int se) in __bth_set_se() argument
109 if (se) in __bth_set_se()
295 static inline void bth_set_se(struct rxe_pkt_info *pkt, int se) in bth_set_se() argument
297 __bth_set_se(pkt->hdr, se); in bth_set_se()
405 static inline void bth_init(struct rxe_pkt_info *pkt, u8 opcode, int se, in bth_init() argument
413 if (se) in bth_init()
/drivers/nfc/pn544/
Dpn544.c811 const struct nfc_se *se; in pn544_hci_enable_se() local
828 se = nfc_find_se(hdev->ndev, se_idx); in pn544_hci_enable_se()
830 switch (se->type) { in pn544_hci_enable_se()
866 const struct nfc_se *se; in pn544_hci_disable_se() local
869 se = nfc_find_se(hdev->ndev, se_idx); in pn544_hci_disable_se()
871 switch (se->type) { in pn544_hci_disable_se()
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_gfx.c149 unsigned se, sh, cu; in amdgpu_gfx_parse_disable_cu() local
160 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu); in amdgpu_gfx_parse_disable_cu()
166 if (se < max_se && sh < max_sh && cu < 16) { in amdgpu_gfx_parse_disable_cu()
167 DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu); in amdgpu_gfx_parse_disable_cu()
168 mask[se * max_sh + sh] |= 1u << cu; in amdgpu_gfx_parse_disable_cu()
171 se, sh, cu); in amdgpu_gfx_parse_disable_cu()
Damdgpu_debugfs.c763 uint32_t offset, se, sh, cu, wave, simd, data[32]; in amdgpu_debugfs_wave_read() local
770 se = (*pos & GENMASK_ULL(14, 7)) >> 7; in amdgpu_debugfs_wave_read()
790 amdgpu_gfx_select_se_sh(adev, se, sh, cu); in amdgpu_debugfs_wave_read()
855 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; in amdgpu_debugfs_gpr_read() local
862 se = (*pos & GENMASK_ULL(19, 12)) >> 12; in amdgpu_debugfs_gpr_read()
884 amdgpu_gfx_select_se_sh(adev, se, sh, cu); in amdgpu_debugfs_gpr_read()
Dgfx_v9_4_2.c422 uint32_t se, cu, simd, wave; in gfx_v9_4_2_log_wave_assignment() local
433 for (se = 0; se < adev->gfx.config.max_shader_engines; se++) { in gfx_v9_4_2_log_wave_assignment()
436 size = sprintf(str, "SE[%02d]CU[%02d]: ", se, cu); in gfx_v9_4_2_log_wave_assignment()
456 uint32_t se, cu, simd, wave; in gfx_v9_4_2_wait_for_waves_assigned() local
465 for (se = 0; se < adev->gfx.config.max_shader_engines; se++) in gfx_v9_4_2_wait_for_waves_assigned()
Damdgpu_gfx.h345 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se… argument
Dgfx_v6_0.c1382 unsigned se; in gfx_v6_0_write_harvested_raster_configs() local
1393 for (se = 0; se < num_se; se++) { in gfx_v6_0_write_harvested_raster_configs()
1395 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); in gfx_v6_0_write_harvested_raster_configs()
1397 int idx = (se / 2) * 2; in gfx_v6_0_write_harvested_raster_configs()
1420 unsigned rb0_mask = 1 << (se * rb_per_se); in gfx_v6_0_write_harvested_raster_configs()
1437 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); in gfx_v6_0_write_harvested_raster_configs()
1455 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); in gfx_v6_0_write_harvested_raster_configs()
/drivers/nfc/st21nfca/
DMakefile6 st21nfca_hci-objs = core.o dep.o se.o vendor_cmds.o
/drivers/crypto/cavium/cpt/
Dcpt_hw_types.h196 u64 se:8; member
200 u64 se:8;
/drivers/nfc/st-nci/
DMakefile6 st-nci-objs = ndlc.o core.o se.o vendor_cmds.o
/drivers/crypto/marvell/octeontx/
Dotx_cpt_hw_types.h334 u64 se:8; member
338 u64 se:8;
Dotx_cptpf_main.c47 cpt->eng_grps.avail.max_se_cnt = pf_cnsts.s.se; in otx_cpt_find_max_enabled_cores()
/drivers/gpu/drm/arm/
Dmalidp_hw.c1292 const struct malidp_irq_map *se = &hw->map.se_irq_map; in malidp_se_irq() local
1304 if (!(status & (se->irq_mask | se->err_mask))) in malidp_se_irq()
1308 if (status & se->err_mask) in malidp_se_irq()
1315 if (status & se->vsync_irq) { in malidp_se_irq()
/drivers/crypto/marvell/octeontx2/
Dotx2_cpt_hw_types.h299 u64 se:16; member
/drivers/net/wireless/intel/iwlwifi/mvm/
Dftm-initiator.c178 struct iwl_mvm_smooth_entry *se, *st; in iwl_mvm_ftm_initiator_smooth_stop() local
180 list_for_each_entry_safe(se, st, &mvm->ftm_initiator.smooth.resp, in iwl_mvm_ftm_initiator_smooth_stop()
182 list_del(&se->list); in iwl_mvm_ftm_initiator_smooth_stop()
183 kfree(se); in iwl_mvm_ftm_initiator_smooth_stop()

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