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Searched refs:skl (Results 1 – 10 of 10) sorted by relevance

/drivers/edac/
Die31200_edac.c169 #define IE31200_PAGES(n, skl) \ argument
170 (n << (28 + (2 * skl) - PAGE_SHIFT))
387 bool skl) in populate_dimm_info() argument
389 if (skl) in populate_dimm_info()
410 bool skl = DEVICE_ID_SKYLAKE_OR_LATER(pdev->device); in ie31200_probe1() local
439 if (skl) in ie31200_probe1()
452 if (skl) { in ie31200_probe1()
469 skl); in ie31200_probe1()
488 nr_pages = IE31200_PAGES(dimm_info[j][i].size, skl); in ie31200_probe1()
498 if (skl) in ie31200_probe1()
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/drivers/gpu/drm/i915/display/
Dintel_atomic_plane.c449 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_next_plane_to_commit()
452 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id], in skl_next_plane_to_commit()
458 entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_next_plane_to_commit()
459 entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id]; in skl_next_plane_to_commit()
505 memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y, in skl_update_planes_on_crtc()
506 sizeof(old_crtc_state->wm.skl.plane_ddb_y)); in skl_update_planes_on_crtc()
507 memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv, in skl_update_planes_on_crtc()
508 sizeof(old_crtc_state->wm.skl.plane_ddb_uv)); in skl_update_planes_on_crtc()
Dintel_bw.c564 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_bw_calc_min_cdclk()
566 &crtc_state->wm.skl.plane_ddb_uv[plane_id]; in skl_bw_calc_min_cdclk()
Dintel_dmc.c83 #define SKL_DMC_PATH DMC_PATH(skl, 1, 27)
Dintel_display_debugfs.c1216 entry = &crtc_state->wm.skl.plane_ddb_y[plane_id]; in i915_ddb_info()
1222 entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR]; in i915_ddb_info()
Dintel_display_types.h860 } skl; member
Dintel_display.c8643 const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; in verify_wm_state()
8740 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id]; in verify_wm_state()
10347 entries[pipe] = old_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
10371 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
10375 entries[pipe] = new_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
10386 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
10387 &old_crtc_state->wm.skl.ddb) && in skl_commit_modeset_enables()
10439 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
10442 entries[pipe] = new_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
/drivers/gpu/drm/i915/
Dintel_pm.c3911 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
3933 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_crtc_can_enable_sagv()
3956 &crtc_state->wm.skl.optimal.planes[plane_id]; in tgl_crtc_can_enable_sagv()
4035 struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal; in intel_compute_sagv_mask()
4226 crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start; in skl_crtc_allocate_ddb()
4227 crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end; in skl_crtc_allocate_ddb()
5140 memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y)); in skl_allocate_plane_ddb()
5141 memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv)); in skl_allocate_plane_ddb()
5160 crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start = in skl_allocate_plane_ddb()
5162 crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end; in skl_allocate_plane_ddb()
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/drivers/platform/x86/intel/int3472/
DKconfig30 The module will be named "intel-skl-int3472".
/drivers/gpu/drm/i915/gt/uc/
Dintel_uc_fw.c64 fw_def(SKYLAKE, 0, guc_def(skl, 62, 0, 0), huc_def(skl, 2, 0, 0))