| /drivers/gpu/drm/i915/gt/ |
| D | intel_sseu.c | 10 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices, in intel_sseu_set_info() argument
13 sseu->max_slices = max_slices; in intel_sseu_set_info()
14 sseu->max_subslices = max_subslices; in intel_sseu_set_info()
15 sseu->max_eus_per_subslice = max_eus_per_subslice; in intel_sseu_set_info()
17 sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices); in intel_sseu_set_info()
18 GEM_BUG_ON(sseu->ss_stride > GEN_MAX_SUBSLICE_STRIDE); in intel_sseu_set_info()
19 sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); in intel_sseu_set_info()
20 GEM_BUG_ON(sseu->eu_stride > GEN_MAX_EU_STRIDE); in intel_sseu_set_info()
24 intel_sseu_subslice_total(const struct sseu_dev_info *sseu) in intel_sseu_subslice_total() argument
28 for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++) in intel_sseu_subslice_total()
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| D | intel_sseu_debugfs.c | 11 static void sseu_copy_subslices(const struct sseu_dev_info *sseu, in sseu_copy_subslices() argument
14 int offset = slice * sseu->ss_stride; in sseu_copy_subslices()
16 memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride); in sseu_copy_subslices()
20 struct sseu_dev_info *sseu) in cherryview_sseu_device_status() argument
40 sseu->slice_mask = BIT(0); in cherryview_sseu_device_status()
41 sseu->subslice_mask[0] |= BIT(ss); in cherryview_sseu_device_status()
46 sseu->eu_total += eu_cnt; in cherryview_sseu_device_status()
47 sseu->eu_per_subslice = max_t(unsigned int, in cherryview_sseu_device_status()
48 sseu->eu_per_subslice, eu_cnt); in cherryview_sseu_device_status()
54 struct sseu_dev_info *sseu) in gen11_sseu_device_status() argument
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| D | intel_sseu.h | 62 intel_sseu_from_device_info(const struct sseu_dev_info *sseu) in intel_sseu_from_device_info() argument
65 .slice_mask = sseu->slice_mask, in intel_sseu_from_device_info()
66 .subslice_mask = sseu->subslice_mask[0], in intel_sseu_from_device_info()
67 .min_eus_per_subslice = sseu->max_eus_per_subslice, in intel_sseu_from_device_info()
68 .max_eus_per_subslice = sseu->max_eus_per_subslice, in intel_sseu_from_device_info()
75 intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice, in intel_sseu_has_subslice() argument
81 GEM_BUG_ON(ss_idx >= sseu->ss_stride); in intel_sseu_has_subslice()
83 mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx]; in intel_sseu_has_subslice()
88 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
92 intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
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| D | intel_context_sseu.c | 17 const struct intel_sseu sseu) in gen8_emit_rpcs_config() argument
32 *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu); in gen8_emit_rpcs_config()
40 gen8_modify_rpcs(struct intel_context *ce, const struct intel_sseu sseu) in gen8_modify_rpcs() argument
65 ret = gen8_emit_rpcs_config(rq, ce, sseu); in gen8_modify_rpcs()
75 const struct intel_sseu sseu) in intel_context_reconfigure_sseu() argument
86 if (!memcmp(&ce->sseu, &sseu, sizeof(sseu))) in intel_context_reconfigure_sseu()
89 ret = gen8_modify_rpcs(ce, sseu); in intel_context_reconfigure_sseu()
91 ce->sseu = sseu; in intel_context_reconfigure_sseu()
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| D | intel_workarounds.c | 430 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) in skl_tune_iz_hashing()
439 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; in skl_tune_iz_hashing()
908 const struct sseu_dev_info *sseu = &i915->gt.info.sseu; in icl_wa_init_mcr() local
912 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); in icl_wa_init_mcr()
924 subslice = __ffs(intel_sseu_get_subslices(sseu, slice)); in icl_wa_init_mcr()
941 const struct sseu_dev_info *sseu = >->info.sseu; in xehp_init_mcr() local
974 dss_mask = intel_sseu_get_subslices(sseu, 0); in xehp_init_mcr()
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| D | intel_gt_types.h | 193 struct sseu_dev_info sseu; member
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| D | intel_context_types.h | 153 struct intel_sseu sseu; member
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| D | intel_context.c | 382 ce->sseu = engine->sseu; in intel_context_init()
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| D | intel_engine_cs.c | 784 engine->sseu = in engine_setup_common()
785 intel_sseu_from_device_info(&engine->gt->info.sseu); in engine_setup_common()
1165 const struct sseu_dev_info *sseu = &engine->gt->info.sseu; in intel_engine_get_instdone() local
1189 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) { in intel_engine_get_instdone()
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| D | intel_context.h | 45 const struct intel_sseu sseu);
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| D | intel_engine_types.h | 309 struct intel_sseu sseu; member
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| D | intel_gt.c | 116 u64 dss_mask = intel_sseu_get_subslices(>->info.sseu, 0); in slicemask()
903 intel_sseu_dump(&info->sseu, p); in intel_gt_info_print()
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| D | intel_lrc.c | 1200 intel_sseu_make_rpcs(engine->gt, &ce->sseu); in lrc_update_regs()
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| D | intel_rps.c | 1118 switch (gt->info.sseu.eu_total) { in chv_rps_max_freq()
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| /drivers/gpu/drm/i915/ |
| D | i915_query.c | 34 const struct sseu_dev_info *sseu = &dev_priv->gt.info.sseu; in query_topology_info() local
42 if (sseu->max_slices == 0) in query_topology_info()
45 BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask)); in query_topology_info()
47 slice_length = sizeof(sseu->slice_mask); in query_topology_info()
48 subslice_length = sseu->max_slices * sseu->ss_stride; in query_topology_info()
49 eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride; in query_topology_info()
62 topo.max_slices = sseu->max_slices; in query_topology_info()
63 topo.max_subslices = sseu->max_subslices; in query_topology_info()
64 topo.max_eus_per_subslice = sseu->max_eus_per_subslice; in query_topology_info()
67 topo.subslice_stride = sseu->ss_stride; in query_topology_info()
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| D | i915_getparam.c | 16 const struct sseu_dev_info *sseu = &i915->gt.info.sseu; in i915_getparam_ioctl() local
74 value = intel_sseu_subslice_total(sseu); in i915_getparam_ioctl()
79 value = sseu->eu_total; in i915_getparam_ioctl()
96 value = sseu->min_eu_in_pool; in i915_getparam_ioctl()
149 value = sseu->slice_mask; in i915_getparam_ioctl()
155 memcpy(&value, sseu->subslice_mask, in i915_getparam_ioctl()
156 min(sseu->ss_stride, (u8)sizeof(value))); in i915_getparam_ioctl()
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| D | i915_perf_types.h | 417 struct intel_sseu sseu; member
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| D | i915_perf.c | 360 struct intel_sseu sseu; member
2262 flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu); in gen8_configure_context()
2406 regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu); in oa_configure_all_contexts()
2806 const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu; in get_default_sseu_config()
2976 perf->sseu = props->sseu; in i915_oa_stream_init()
3488 get_default_sseu_config(&props->sseu, props->engine); in i915_perf_open_ioctl_locked()
3736 ret = get_sseu_config(&props->sseu, props->engine, &user_sseu); in read_properties_unlocked()
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| D | i915_gpu_error.c | 431 const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu; in error_print_instdone() local
447 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) in error_print_instdone()
452 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) in error_print_instdone()
688 intel_sseu_print_topology(>->info.sseu, &p); in err_print_gt_info()
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| /drivers/gpu/drm/i915/gem/ |
| D | i915_gem_context.c | 616 struct intel_sseu *sseu; in set_proto_ctx_sseu() local
652 sseu = &pe->sseu; in set_proto_ctx_sseu()
662 sseu = &pc->legacy_rcs_sseu; in set_proto_ctx_sseu()
665 ret = i915_gem_user_to_context_sseu(&i915->gt, &user_sseu, sseu); in set_proto_ctx_sseu()
787 struct intel_sseu sseu) in intel_context_set_gem() argument
820 if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS)) in intel_context_set_gem()
821 ret = intel_context_reconfigure_sseu(ce, sseu); in intel_context_set_gem()
905 struct intel_sseu sseu = {}; in default_engines() local
924 sseu = rcs_sseu; in default_engines()
926 ret = intel_context_set_gem(ce, ctx, sseu); in default_engines()
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| D | i915_gem_context_types.h | 115 struct intel_sseu sseu; member
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| /drivers/gpu/drm/i915/gem/selftests/ |
| D | i915_gem_context.c | 1169 unsigned int slices = hweight32(ce->engine->sseu.slice_mask); in __sseu_finish()
1210 struct intel_sseu sseu) in __sseu_test() argument
1221 ret = intel_context_reconfigure_sseu(ce, sseu); in __sseu_test()
1226 hweight32(sseu.slice_mask), spin); in __sseu_test()
1271 if (hweight32(engine->sseu.slice_mask) < 2) in __igt_ctx_sseu()
1274 if (!engine->gt->info.sseu.has_slice_pg) in __igt_ctx_sseu()
1281 pg_sseu = engine->sseu; in __igt_ctx_sseu()
1284 ~(~0 << (hweight32(engine->sseu.subslice_mask) / 2)); in __igt_ctx_sseu()
1288 hweight32(engine->sseu.slice_mask), in __igt_ctx_sseu()
1302 ret = __sseu_test(name, flags, ce, obj, engine->sseu); in __igt_ctx_sseu()
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| /drivers/gpu/drm/i915/gt/uc/ |
| D | intel_guc_ads.c | 505 hweight8(gt->info.sseu.slice_mask); in __guc_ads_init()
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