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Searched refs:tgn10 (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_resource.c779 struct optc *tgn10 = in dcn10_timing_generator_create() local
782 if (!tgn10) in dcn10_timing_generator_create()
785 tgn10->base.inst = instance; in dcn10_timing_generator_create()
786 tgn10->base.ctx = ctx; in dcn10_timing_generator_create()
788 tgn10->tg_regs = &tg_regs[instance]; in dcn10_timing_generator_create()
789 tgn10->tg_shift = &tg_shift; in dcn10_timing_generator_create()
790 tgn10->tg_mask = &tg_mask; in dcn10_timing_generator_create()
792 dcn10_timing_generator_init(tgn10); in dcn10_timing_generator_create()
794 return &tgn10->base; in dcn10_timing_generator_create()
/drivers/gpu/drm/amd/display/dc/dcn303/
Ddcn303_resource.c693 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); in dcn303_timing_generator_create() local
695 if (!tgn10) in dcn303_timing_generator_create()
698 tgn10->base.inst = instance; in dcn303_timing_generator_create()
699 tgn10->base.ctx = ctx; in dcn303_timing_generator_create()
701 tgn10->tg_regs = &optc_regs[instance]; in dcn303_timing_generator_create()
702 tgn10->tg_shift = &optc_shift; in dcn303_timing_generator_create()
703 tgn10->tg_mask = &optc_mask; in dcn303_timing_generator_create()
705 dcn30_timing_generator_init(tgn10); in dcn303_timing_generator_create()
707 return &tgn10->base; in dcn303_timing_generator_create()
/drivers/gpu/drm/amd/display/dc/dcn302/
Ddcn302_resource.c740 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL); in dcn302_timing_generator_create() local
742 if (!tgn10) in dcn302_timing_generator_create()
745 tgn10->base.inst = instance; in dcn302_timing_generator_create()
746 tgn10->base.ctx = ctx; in dcn302_timing_generator_create()
748 tgn10->tg_regs = &optc_regs[instance]; in dcn302_timing_generator_create()
749 tgn10->tg_shift = &optc_shift; in dcn302_timing_generator_create()
750 tgn10->tg_mask = &optc_mask; in dcn302_timing_generator_create()
752 dcn30_timing_generator_init(tgn10); in dcn302_timing_generator_create()
754 return &tgn10->base; in dcn302_timing_generator_create()
/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_resource.c1044 struct optc *tgn10 = in dcn301_timing_generator_create() local
1047 if (!tgn10) in dcn301_timing_generator_create()
1050 tgn10->base.inst = instance; in dcn301_timing_generator_create()
1051 tgn10->base.ctx = ctx; in dcn301_timing_generator_create()
1053 tgn10->tg_regs = &optc_regs[instance]; in dcn301_timing_generator_create()
1054 tgn10->tg_shift = &optc_shift; in dcn301_timing_generator_create()
1055 tgn10->tg_mask = &optc_mask; in dcn301_timing_generator_create()
1057 dcn30_timing_generator_init(tgn10); in dcn301_timing_generator_create()
1059 return &tgn10->base; in dcn301_timing_generator_create()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c1504 struct optc *tgn10 = in dcn21_timing_generator_create() local
1507 if (!tgn10) in dcn21_timing_generator_create()
1510 tgn10->base.inst = instance; in dcn21_timing_generator_create()
1511 tgn10->base.ctx = ctx; in dcn21_timing_generator_create()
1513 tgn10->tg_regs = &tg_regs[instance]; in dcn21_timing_generator_create()
1514 tgn10->tg_shift = &tg_shift; in dcn21_timing_generator_create()
1515 tgn10->tg_mask = &tg_mask; in dcn21_timing_generator_create()
1517 dcn20_timing_generator_init(tgn10); in dcn21_timing_generator_create()
1519 return &tgn10->base; in dcn21_timing_generator_create()
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_resource.c1133 struct optc *tgn10 = in dcn31_timing_generator_create() local
1136 if (!tgn10) in dcn31_timing_generator_create()
1139 tgn10->base.inst = instance; in dcn31_timing_generator_create()
1140 tgn10->base.ctx = ctx; in dcn31_timing_generator_create()
1142 tgn10->tg_regs = &optc_regs[instance]; in dcn31_timing_generator_create()
1143 tgn10->tg_shift = &optc_shift; in dcn31_timing_generator_create()
1144 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
1146 dcn31_timing_generator_init(tgn10); in dcn31_timing_generator_create()
1148 return &tgn10->base; in dcn31_timing_generator_create()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_resource.c1028 struct optc *tgn10 = in dcn30_timing_generator_create() local
1031 if (!tgn10) in dcn30_timing_generator_create()
1034 tgn10->base.inst = instance; in dcn30_timing_generator_create()
1035 tgn10->base.ctx = ctx; in dcn30_timing_generator_create()
1037 tgn10->tg_regs = &optc_regs[instance]; in dcn30_timing_generator_create()
1038 tgn10->tg_shift = &optc_shift; in dcn30_timing_generator_create()
1039 tgn10->tg_mask = &optc_mask; in dcn30_timing_generator_create()
1041 dcn30_timing_generator_init(tgn10); in dcn30_timing_generator_create()
1043 return &tgn10->base; in dcn30_timing_generator_create()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c1257 struct optc *tgn10 = in dcn20_timing_generator_create() local
1260 if (!tgn10) in dcn20_timing_generator_create()
1263 tgn10->base.inst = instance; in dcn20_timing_generator_create()
1264 tgn10->base.ctx = ctx; in dcn20_timing_generator_create()
1266 tgn10->tg_regs = &tg_regs[instance]; in dcn20_timing_generator_create()
1267 tgn10->tg_shift = &tg_shift; in dcn20_timing_generator_create()
1268 tgn10->tg_mask = &tg_mask; in dcn20_timing_generator_create()
1270 dcn20_timing_generator_init(tgn10); in dcn20_timing_generator_create()
1272 return &tgn10->base; in dcn20_timing_generator_create()