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Searched refs:GENMASK (Results 1 – 25 of 83) sorted by relevance

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/include/soc/mscc/
Docelot_ana.h15 #define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14))
16 #define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
17 #define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14)
19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
20 #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
24 #define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3))
25 #define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
26 #define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3)
28 #define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0))
29 #define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0)
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Docelot_qsys.h25 #define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8))
26 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)
27 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8)
28 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0))
29 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0)
33 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8))
34 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8)
35 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8)
36 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0))
37 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(7, 0)
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Docelot_hsio.h90 #define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23))
91 #define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)
92 #define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23)
93 #define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18))
94 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)
95 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18)
96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
97 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
103 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6))
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Docelot_sys.h20 #define SYS_FRM_AGING_MAX_AGE(x) ((x) & GENMASK(19, 0))
21 #define SYS_FRM_AGING_MAX_AGE_M GENMASK(19, 0)
23 #define SYS_STAT_CFG_STAT_CLEAR_SHOT(x) (((x) << 10) & GENMASK(16, 10))
24 #define SYS_STAT_CFG_STAT_CLEAR_SHOT_M GENMASK(16, 10)
25 #define SYS_STAT_CFG_STAT_CLEAR_SHOT_X(x) (((x) & GENMASK(16, 10)) >> 10)
26 #define SYS_STAT_CFG_STAT_VIEW(x) ((x) & GENMASK(9, 0))
27 #define SYS_STAT_CFG_STAT_VIEW_M GENMASK(9, 0)
40 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x) (((x) << 6) & GENMASK(21, 6))
41 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M GENMASK(21, 6)
42 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x) (((x) & GENMASK(21, 6)) >> 6)
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Docelot_dev.h17 #define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0))
18 #define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
27 #define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15))
28 #define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
29 #define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15)
30 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))
31 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
32 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)
33 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1))
34 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1)
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/include/linux/mfd/
Dtps68470.h57 #define TPS68470_REG_RESET_MASK GENMASK(7, 0)
58 #define TPS68470_VAVAL_AVOLT_MASK GENMASK(6, 0)
60 #define TPS68470_VDVAL_DVOLT_MASK GENMASK(5, 0)
61 #define TPS68470_VCMVAL_VCVOLT_MASK GENMASK(6, 0)
62 #define TPS68470_VIOVAL_IOVOLT_MASK GENMASK(6, 0)
63 #define TPS68470_VSIOVAL_IOVOLT_MASK GENMASK(6, 0)
64 #define TPS68470_VAUX1VAL_AUX1VOLT_MASK GENMASK(6, 0)
65 #define TPS68470_VAUX2VAL_AUX2VOLT_MASK GENMASK(6, 0)
67 #define TPS68470_VACTL_EN_MASK GENMASK(0, 0)
68 #define TPS68470_VDCTL_EN_MASK GENMASK(0, 0)
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Dsun4i-gpadc.h12 #define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY(x) ((GENMASK(7, 0) & (x)) << 24)
15 #define SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(x) ((GENMASK(1, 0) & (x)) << 20)
16 #define SUN4I_GPADC_CTRL0_FS_DIV(x) ((GENMASK(3, 0) & (x)) << 16)
17 #define SUN4I_GPADC_CTRL0_T_ACQ(x) (GENMASK(15, 0) & (x))
21 #define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE(x) ((GENMASK(7, 0) & (x)) << 12)
27 #define SUN4I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(2, 0) & (x))
28 #define SUN4I_GPADC_CTRL1_ADC_CHAN_MASK GENMASK(2, 0)
35 #define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(3, 0) & BIT(x))
36 #define SUN6I_GPADC_CTRL1_ADC_CHAN_MASK GENMASK(3, 0)
44 #define SUN4I_GPADC_CTRL2_TP_SENSITIVE_ADJUST(x) ((GENMASK(3, 0) & (x)) << 28)
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Dintel-m10-bmc.h25 #define M10BMC_MAC_BYTE4 GENMASK(7, 0)
26 #define M10BMC_MAC_BYTE3 GENMASK(15, 8)
27 #define M10BMC_MAC_BYTE2 GENMASK(23, 16)
28 #define M10BMC_MAC_BYTE1 GENMASK(31, 24)
30 #define M10BMC_MAC_BYTE6 GENMASK(7, 0)
31 #define M10BMC_MAC_BYTE5 GENMASK(15, 8)
32 #define M10BMC_MAC_COUNT GENMASK(23, 16)
35 #define M10BMC_VER_MAJOR_MSK GENMASK(23, 16)
36 #define M10BMC_VER_PCB_INFO_MSK GENMASK(31, 24)
47 #define DRBL_RSU_PROGRESS GENMASK(7, 4)
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Dstpmic1.h101 #define LDO_VOLTAGE_MASK GENMASK(6, 2)
102 #define BUCK_VOLTAGE_MASK GENMASK(7, 2)
113 #define BUCKS_PD_CR_REG_MASK GENMASK(7, 0)
114 #define BUCK_MASK_RANK_REGISTER_MASK GENMASK(3, 0)
115 #define BUCK_MASK_RESET_REGISTER_MASK GENMASK(3, 0)
116 #define LDO1234_PULL_DOWN_REGISTER_MASK GENMASK(7, 0)
117 #define LDO56_VREF_PD_CR_REG_MASK GENMASK(5, 0)
118 #define LDO_MASK_RANK_REGISTER_MASK GENMASK(5, 0)
119 #define LDO_MASK_RESET_REGISTER_MASK GENMASK(5, 0)
145 #define BUCKS_ICCTO_CR_REG_MASK GENMASK(6, 0)
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Dtps65086.h87 #define TPS65086_DEVICEID_PART_MASK GENMASK(3, 0)
88 #define TPS65086_DEVICEID_OTP_MASK GENMASK(5, 4)
89 #define TPS65086_DEVICEID_REV_MASK GENMASK(7, 6)
92 #define BUCK_VID_MASK GENMASK(7, 1)
93 #define VDOA1_VID_MASK GENMASK(4, 1)
94 #define VDOA23_VID_MASK GENMASK(3, 0)
Dstm32-lptimer.h25 #define STM32_LPTIM_CMPOK_ARROK GENMASK(4, 3)
31 #define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3)
45 #define STM32_LPTIM_PRESC GENMASK(11, 9)
46 #define STM32_LPTIM_CKPOL GENMASK(2, 1)
Dimx25-tsadc.h31 #define MX25_TGCR_PDBTIME_MASK GENMASK(31, 25)
37 #define MX25_TGCR_POWERMODE_MASK GENMASK(9, 8)
65 #define MX25_ADCQ_CR_RWAIT_MASK GENMASK(15, 12)
67 #define MX25_ADCQ_CR_WMRK_MASK GENMASK(11, 8)
73 #define MX25_ADCQ_CR_QSM_MASK GENMASK(1, 0)
106 #define MX25_ADCQ_CFG_NOS_MASK GENMASK(19, 16)
123 #define MX25_ADCQ_CFG_REFP_MASK GENMASK(8, 7)
138 #define MX25_ADCQ_CFG_REFN_MASK GENMASK(3, 2)
/include/linux/mfd/syscon/
Datmel-mc.h21 #define AT91_MC_ABTSZ GENMASK(9, 8)
25 #define AT91_MC_ABTTYP GENMASK(11, 10)
35 #define AT91_MPR_MSTP(n) GENMASK(2 + ((x) * 4), ((x) * 4))
47 #define AT91_MC_SMC_NWS GENMASK(6, 0)
50 #define AT91_MC_SMC_TDF GENMASK(11, 8)
54 #define AT91_MC_SMC_DBW GENMASK(14, 13)
58 #define AT91_MC_SMC_ACSS GENMASK(17, 16)
61 #define AT91_MC_SMC_RWSETUP GENMASK(26, 24)
63 #define AT91_MC_SMC_RWHOLD GENMASK(30, 28)
69 #define AT91_MC_SDRAMC_MODE GENMASK(3, 0)
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Datmel-matrix.h64 #define AT91_MATRIX_ULBT GENMASK(2, 0)
72 #define AT91_MATRIX_SLOT_CYCLE GENMASK(7, 0)
73 #define AT91_MATRIX_DEFMSTR_TYPE GENMASK(17, 16)
77 #define AT91_MATRIX_FIXED_DEFMSTR GENMASK(20, 18)
78 #define AT91_MATRIX_ARBT GENMASK(25, 24)
82 #define AT91_MATRIX_ITCM_SIZE GENMASK(3, 0)
87 #define AT91_MATRIX_DTCM_SIZE GENMASK(7, 4)
95 #define AT91_MATRIX_MPR(x) GENMASK(((x) * 0x4) + 1, ((x) * 0x4))
/include/linux/amba/
Dpl080.h70 #define PL080_LLI_ADDR_MASK GENMASK(31, 2)
75 #define PL080_CONTROL_PROT_MASK GENMASK(30, 28)
84 #define PL080_CONTROL_DWIDTH_MASK GENMASK(23, 21)
86 #define PL080_CONTROL_SWIDTH_MASK GENMASK(20, 18)
88 #define PL080_CONTROL_DB_SIZE_MASK GENMASK(17, 15)
90 #define PL080_CONTROL_SB_SIZE_MASK GENMASK(14, 12)
92 #define PL080_CONTROL_TRANSFER_SIZE_MASK GENMASK(11, 0)
93 #define PL080S_CONTROL_TRANSFER_SIZE_MASK GENMASK(24, 0)
116 #define PL080_CONFIG_FLOW_CONTROL_MASK GENMASK(13, 11)
118 #define PL080_CONFIG_DST_SEL_MASK GENMASK(9, 6)
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/include/linux/soundwire/
Dsdw_intel.h38 #define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
40 #define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
44 #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
46 #define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
50 #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
51 #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
52 #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
54 #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
55 #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
56 #define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
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Dsdw_registers.h10 #define SDW_REGADDR GENMASK(14, 0)
11 #define SDW_SCP_ADDRPAGE2_MASK GENMASK(22, 15)
12 #define SDW_SCP_ADDRPAGE1_MASK GENMASK(30, 23)
51 #define SDW_DP0_PORTCTRL_DATAMODE GENMASK(3, 2)
53 #define SDW_DP0_PORTCTRL_BPT_PAYLD GENMASK(7, 6)
71 #define SDW_SCP_INT1_PORT0_3 GENMASK(6, 3)
75 #define SDW_SCP_INTSTAT2_PORT4_10 GENMASK(6, 0)
78 #define SDW_SCP_INTSTAT3_PORT11_14 GENMASK(3, 0)
113 #define SDW_SCP_BASE_CLOCK_FREQ GENMASK(2, 0)
221 #define SDW_SCP_CLOCK_SCALE GENMASK(3, 0)
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/include/media/drv-intf/
Dcx25840.h100 #define CX25840_VCONFIG_FMT_MASK GENMASK(2, 0)
103 #define CX25840_VCONFIG_FMT_VIP11 GENMASK(1, 0)
107 #define CX25840_VCONFIG_RES_MASK GENMASK(4, 3)
112 #define CX25840_VCONFIG_VBIRAW_MASK GENMASK(6, 5)
117 #define CX25840_VCONFIG_ANCDATA_MASK GENMASK(8, 7)
122 #define CX25840_VCONFIG_TASKBIT_MASK GENMASK(10, 9)
127 #define CX25840_VCONFIG_ACTIVE_MASK GENMASK(12, 11)
132 #define CX25840_VCONFIG_VALID_MASK GENMASK(14, 13)
137 #define CX25840_VCONFIG_HRESETW_MASK GENMASK(16, 15)
142 #define CX25840_VCONFIG_CLKGATE_MASK GENMASK(18, 17)
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/include/linux/
Dpxa2xx_ssp.h49 #define SSCR0_DSS GENMASK(3, 0) /* Data Size Select (mask) */
51 #define SSCR0_FRF GENMASK(5, 4) /* FRame Format (mask) */
64 #define SSCR0_FRDC GENMASK(26, 24) /* Frame rate divider control (mask) */
77 #define SSSR_ALT_FRM_MASK GENMASK(1, 0) /* Masks the SFRM signal number */
88 #define SSSR_TFL_MASK GENMASK(11, 8) /* Transmit FIFO Level mask */
89 #define SSSR_RFL_MASK GENMASK(15, 12) /* Receive FIFO Level mask */
91 #define SSCR1_TFT GENMASK(9, 6) /* Transmit FIFO Threshold (mask) */
93 #define SSCR1_RFT GENMASK(13, 10) /* Receive FIFO Threshold (mask) */
99 #define CE4100_SSSR_TFL_MASK GENMASK(9, 8) /* Transmit FIFO Level mask */
100 #define CE4100_SSSR_RFL_MASK GENMASK(13, 12) /* Receive FIFO Level mask */
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Dqcom-geni-se.h119 #define CLK_DIV_MSK GENMASK(15, 4)
126 #define FW_REV_PROTOCOL_MSK GENMASK(15, 8)
130 #define CLK_SEL_MSK GENMASK(2, 0)
136 #define M_OPCODE_MSK GENMASK(31, 27)
138 #define M_PARAMS_MSK GENMASK(26, 0)
146 #define S_OPCODE_MSK GENMASK(31, 27)
148 #define S_PARAMS_MSK GENMASK(26, 0)
181 #define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \
207 #define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \
211 #define WATERMARK_MSK GENMASK(5, 0)
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Dif_rmnet.h19 #define MAP_PAD_LEN_MASK GENMASK(5, 0)
46 #define MAP_CSUM_UL_OFFSET_MASK GENMASK(13, 0)
68 #define MAPV5_HDRINFO_HDR_TYPE_FMASK GENMASK(7, 1)
/include/linux/dma/
Dti-cppi5.h59 #define CPPI5_INFO0_HDESC_TYPE_MASK GENMASK(31, 30)
71 #define CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK GENMASK(27, 22)
73 #define CPPI5_INFO0_HDESC_PKTLEN_MASK GENMASK(21, 0)
76 #define CPPI5_INFO1_DESC_PKTERROR_MASK GENMASK(31, 28)
78 #define CPPI5_INFO1_HDESC_PSFLGS_MASK GENMASK(27, 24)
80 #define CPPI5_INFO1_DESC_PKTID_MASK GENMASK(23, 14)
82 #define CPPI5_INFO1_DESC_FLOWID_MASK GENMASK(13, 0)
86 #define CPPI5_INFO2_HDESC_PKTTYPE_MASK GENMASK(31, 27)
102 #define CPPI5_INFO2_DESC_RETP_MASK GENMASK(18, 16)
105 #define CPPI5_INFO2_DESC_RETQ_MASK GENMASK(15, 0)
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/include/linux/usb/
Dtypec_tbt.h38 #define TBT_CABLE_SPEED(_vdo_) (((_vdo_) & GENMASK(18, 16)) >> 16)
43 (((_vdo_) & GENMASK(20, 19)) >> 19)
50 #define TBT_SET_CABLE_SPEED(_s_) (((_s_) & GENMASK(2, 0)) << 16)
51 #define TBT_SET_CABLE_ROUNDED(_g_) (((_g_) & GENMASK(1, 0)) << 19)
/include/linux/mfd/wcd934x/
Dregisters.h7 #define WCD934X_CODEC_RPM_CLK_GATE_MASK GENMASK(1, 0)
11 #define WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK GENMASK(1, 0)
17 #define WCD934X_EFUSE_SENSE_STATE_MASK GENMASK(4, 1)
34 #define WCD934X_DMIC_RATE_MASK GENMASK(3, 1)
92 #define WCD934X_ANA_BUCK_HI_ACCU_PRE_ENX_MASK GENMASK(1, 0)
128 #define WCD934X_VTH_MASK GENMASK(7, 2)
136 #define WCD934X_MBHC_BTN_VTH_MASK GENMASK(7, 2)
138 #define WCD934X_MICB_VAL_MASK GENMASK(5, 0)
139 #define WCD934X_ANA_MICB_EN_MASK GENMASK(7, 6)
149 #define WCD934X_ANA_MICB2_ENABLE_MASK GENMASK(7, 6)
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/include/asm-generic/bitops/
Dfind.h32 val = *addr & GENMASK(size - 1, offset); in find_next_bit()
62 val = *addr1 & *addr2 & GENMASK(size - 1, offset); in find_next_and_bit()
90 val = *addr | ~GENMASK(size - 1, offset); in find_next_zero_bit()
113 unsigned long val = *addr & GENMASK(size - 1, 0); in find_first_bit()
135 unsigned long val = *addr | ~GENMASK(size - 1, 0); in find_first_zero_bit()
167 unsigned long val = *addr & GENMASK(size - 1, 0); in find_last_bit()

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