Searched refs:settings (Results 1 – 4 of 4) sorted by relevance
78 struct clk_aic32x4_pll_muldiv *settings) in clk_aic32x4_pll_get_muldiv() argument87 settings->r = val & AIC32X4_PLL_R_MASK; in clk_aic32x4_pll_get_muldiv()88 settings->p = (val & AIC32X4_PLL_P_MASK) >> AIC32X4_PLL_P_SHIFT; in clk_aic32x4_pll_get_muldiv()93 settings->j = val; in clk_aic32x4_pll_get_muldiv()98 settings->d = val << 8; in clk_aic32x4_pll_get_muldiv()103 settings->d |= val; in clk_aic32x4_pll_get_muldiv()109 struct clk_aic32x4_pll_muldiv *settings) in clk_aic32x4_pll_set_muldiv() argument115 AIC32X4_PLL_R_MASK, settings->r); in clk_aic32x4_pll_set_muldiv()121 settings->p << AIC32X4_PLL_P_SHIFT); in clk_aic32x4_pll_set_muldiv()125 ret = regmap_write(pll->regmap, AIC32X4_PLLJ, settings->j); in clk_aic32x4_pll_set_muldiv()[all …]
1776 } settings[6]; /* One for each dmic divisor. */ member1782 .settings = {1793 .settings = {1804 .settings = {1815 .settings = {1826 .settings = {1899 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq; in max98090_configure_dmic()1900 dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i]; in max98090_configure_dmic()
949 struct reg_setting settings[PLL_REG_SETTINGS_COUNT]; member956 .settings = { \1076 pll_ctl->settings[i].addr, in set_pll_ctl_from_input_freq()1077 pll_ctl->settings[i].mask, in set_pll_ctl_from_input_freq()1078 pll_ctl->settings[i].val); in set_pll_ctl_from_input_freq()
511 struct reg_setting settings[PLL_REG_SETTINGS_COUNT]; member517 .settings = { \647 pll_ctl->settings[i].addr, in set_sysclk()648 pll_ctl->settings[i].val); in set_sysclk()