1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
4 *
5 * Copyright 2011-2012 Maxim Integrated Products
6 */
7
8 #include <linux/delay.h>
9 #include <linux/i2c.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/pm.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regmap.h>
15 #include <linux/slab.h>
16 #include <linux/acpi.h>
17 #include <linux/clk.h>
18 #include <sound/jack.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <sound/tlv.h>
23 #include <sound/max98090.h>
24 #include "max98090.h"
25
26 /* Allows for sparsely populated register maps */
27 static const struct reg_default max98090_reg[] = {
28 { 0x00, 0x00 }, /* 00 Software Reset */
29 { 0x03, 0x04 }, /* 03 Interrupt Masks */
30 { 0x04, 0x00 }, /* 04 System Clock Quick */
31 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
32 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
33 { 0x07, 0x00 }, /* 07 DAC Path Quick */
34 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
35 { 0x09, 0x00 }, /* 09 Line to ADC Quick */
36 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
37 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
38 { 0x0C, 0x00 }, /* 0C Reserved */
39 { 0x0D, 0x00 }, /* 0D Input Config */
40 { 0x0E, 0x1B }, /* 0E Line Input Level */
41 { 0x0F, 0x00 }, /* 0F Line Config */
42
43 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
44 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
45 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
46 { 0x13, 0x00 }, /* 13 Digital Mic Config */
47 { 0x14, 0x00 }, /* 14 Digital Mic Mode */
48 { 0x15, 0x00 }, /* 15 Left ADC Mixer */
49 { 0x16, 0x00 }, /* 16 Right ADC Mixer */
50 { 0x17, 0x03 }, /* 17 Left ADC Level */
51 { 0x18, 0x03 }, /* 18 Right ADC Level */
52 { 0x19, 0x00 }, /* 19 ADC Biquad Level */
53 { 0x1A, 0x00 }, /* 1A ADC Sidetone */
54 { 0x1B, 0x00 }, /* 1B System Clock */
55 { 0x1C, 0x00 }, /* 1C Clock Mode */
56 { 0x1D, 0x00 }, /* 1D Any Clock 1 */
57 { 0x1E, 0x00 }, /* 1E Any Clock 2 */
58 { 0x1F, 0x00 }, /* 1F Any Clock 3 */
59
60 { 0x20, 0x00 }, /* 20 Any Clock 4 */
61 { 0x21, 0x00 }, /* 21 Master Mode */
62 { 0x22, 0x00 }, /* 22 Interface Format */
63 { 0x23, 0x00 }, /* 23 TDM Format 1*/
64 { 0x24, 0x00 }, /* 24 TDM Format 2*/
65 { 0x25, 0x00 }, /* 25 I/O Configuration */
66 { 0x26, 0x80 }, /* 26 Filter Config */
67 { 0x27, 0x00 }, /* 27 DAI Playback Level */
68 { 0x28, 0x00 }, /* 28 EQ Playback Level */
69 { 0x29, 0x00 }, /* 29 Left HP Mixer */
70 { 0x2A, 0x00 }, /* 2A Right HP Mixer */
71 { 0x2B, 0x00 }, /* 2B HP Control */
72 { 0x2C, 0x1A }, /* 2C Left HP Volume */
73 { 0x2D, 0x1A }, /* 2D Right HP Volume */
74 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
75 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
76
77 { 0x30, 0x00 }, /* 30 Spk Control */
78 { 0x31, 0x2C }, /* 31 Left Spk Volume */
79 { 0x32, 0x2C }, /* 32 Right Spk Volume */
80 { 0x33, 0x00 }, /* 33 ALC Timing */
81 { 0x34, 0x00 }, /* 34 ALC Compressor */
82 { 0x35, 0x00 }, /* 35 ALC Expander */
83 { 0x36, 0x00 }, /* 36 ALC Gain */
84 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
85 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
86 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
87 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
88 { 0x3B, 0x00 }, /* 3B Line OutR Control */
89 { 0x3C, 0x15 }, /* 3C Line OutR Volume */
90 { 0x3D, 0x00 }, /* 3D Jack Detect */
91 { 0x3E, 0x00 }, /* 3E Input Enable */
92 { 0x3F, 0x00 }, /* 3F Output Enable */
93
94 { 0x40, 0x00 }, /* 40 Level Control */
95 { 0x41, 0x00 }, /* 41 DSP Filter Enable */
96 { 0x42, 0x00 }, /* 42 Bias Control */
97 { 0x43, 0x00 }, /* 43 DAC Control */
98 { 0x44, 0x06 }, /* 44 ADC Control */
99 { 0x45, 0x00 }, /* 45 Device Shutdown */
100 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
101 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
102 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
103 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
104 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
105 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
106 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
107 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
108 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
109 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
110
111 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
112 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
113 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
114 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
115 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
116 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
117 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
118 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
119 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
120 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
121 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
122 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
123 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
124 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
125 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
126 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
127
128 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
129 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
130 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
131 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
132 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
133 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
134 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
135 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
136 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
137 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
138 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
139 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
140 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
141 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
142 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
143 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
144
145 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
146 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
147 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
148 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
149 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
150 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
151 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
152 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
153 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
154 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
155 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
156 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
157 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
158 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
159 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
160 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
161
162 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
163 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
164 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
165 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
166 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
167 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
168 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
169 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
170 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
171 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
172 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
173 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
174 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
175 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
176 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
177 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
178
179 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
180 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
181 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
182 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
183 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
184 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
185 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
186 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
187 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
188 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
189 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
190 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
191 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
192 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
193 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
194 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
195
196 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
197 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
198 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
199 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
200 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
201 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
202 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
203 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
204 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
205 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
206 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
207 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
208 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
209 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
210 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
211 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
212
213 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
214 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
215 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
216 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
217 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
218 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
219 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
220 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
221 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
222 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
223 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
224 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
225 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
226 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
227 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
228 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
229
230 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
231 { 0xC1, 0x00 }, /* C1 Record TDM Slot */
232 { 0xC2, 0x00 }, /* C2 Sample Rate */
233 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
234 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
235 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
236 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
237 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
238 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
239 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
240 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
241 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
242 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
243 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
244 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
245 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
246
247 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
248 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
249 };
250
max98090_volatile_register(struct device * dev,unsigned int reg)251 static bool max98090_volatile_register(struct device *dev, unsigned int reg)
252 {
253 switch (reg) {
254 case M98090_REG_SOFTWARE_RESET:
255 case M98090_REG_DEVICE_STATUS:
256 case M98090_REG_JACK_STATUS:
257 case M98090_REG_REVISION_ID:
258 return true;
259 default:
260 return false;
261 }
262 }
263
max98090_readable_register(struct device * dev,unsigned int reg)264 static bool max98090_readable_register(struct device *dev, unsigned int reg)
265 {
266 switch (reg) {
267 case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S:
268 case M98090_REG_LINE_INPUT_CONFIG ... 0xD1:
269 case M98090_REG_REVISION_ID:
270 return true;
271 default:
272 return false;
273 }
274 }
275
max98090_reset(struct max98090_priv * max98090)276 static int max98090_reset(struct max98090_priv *max98090)
277 {
278 int ret;
279
280 /* Reset the codec by writing to this write-only reset register */
281 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
282 M98090_SWRESET_MASK);
283 if (ret < 0) {
284 dev_err(max98090->component->dev,
285 "Failed to reset codec: %d\n", ret);
286 return ret;
287 }
288
289 msleep(20);
290 return ret;
291 }
292
293 static const DECLARE_TLV_DB_RANGE(max98090_micboost_tlv,
294 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
295 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
296 );
297
298 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
299
300 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
301 -600, 600, 0);
302
303 static const DECLARE_TLV_DB_RANGE(max98090_line_tlv,
304 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
305 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
306 );
307
308 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
309 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
310
311 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
312 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
313
314 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
315 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
316 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
317 static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0);
318
319 static const DECLARE_TLV_DB_RANGE(max98090_mixout_tlv,
320 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
321 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
322 );
323
324 static const DECLARE_TLV_DB_RANGE(max98090_hp_tlv,
325 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
326 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
327 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
328 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
329 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
330 );
331
332 static const DECLARE_TLV_DB_RANGE(max98090_spk_tlv,
333 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
334 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
335 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
336 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
337 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0)
338 );
339
340 static const DECLARE_TLV_DB_RANGE(max98090_rcv_lout_tlv,
341 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
342 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
343 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
344 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
345 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
346 );
347
max98090_get_enab_tlv(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)348 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
349 struct snd_ctl_elem_value *ucontrol)
350 {
351 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
352 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
353 struct soc_mixer_control *mc =
354 (struct soc_mixer_control *)kcontrol->private_value;
355 unsigned int mask = (1 << fls(mc->max)) - 1;
356 unsigned int val = snd_soc_component_read(component, mc->reg);
357 unsigned int *select;
358
359 switch (mc->reg) {
360 case M98090_REG_MIC1_INPUT_LEVEL:
361 select = &(max98090->pa1en);
362 break;
363 case M98090_REG_MIC2_INPUT_LEVEL:
364 select = &(max98090->pa2en);
365 break;
366 case M98090_REG_ADC_SIDETONE:
367 select = &(max98090->sidetone);
368 break;
369 default:
370 return -EINVAL;
371 }
372
373 val = (val >> mc->shift) & mask;
374
375 if (val >= 1) {
376 /* If on, return the volume */
377 val = val - 1;
378 *select = val;
379 } else {
380 /* If off, return last stored value */
381 val = *select;
382 }
383
384 ucontrol->value.integer.value[0] = val;
385 return 0;
386 }
387
max98090_put_enab_tlv(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)388 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
389 struct snd_ctl_elem_value *ucontrol)
390 {
391 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
392 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
393 struct soc_mixer_control *mc =
394 (struct soc_mixer_control *)kcontrol->private_value;
395 unsigned int mask = (1 << fls(mc->max)) - 1;
396 int sel_unchecked = ucontrol->value.integer.value[0];
397 unsigned int sel;
398 unsigned int val = snd_soc_component_read(component, mc->reg);
399 unsigned int *select;
400
401 switch (mc->reg) {
402 case M98090_REG_MIC1_INPUT_LEVEL:
403 select = &(max98090->pa1en);
404 break;
405 case M98090_REG_MIC2_INPUT_LEVEL:
406 select = &(max98090->pa2en);
407 break;
408 case M98090_REG_ADC_SIDETONE:
409 select = &(max98090->sidetone);
410 break;
411 default:
412 return -EINVAL;
413 }
414
415 val = (val >> mc->shift) & mask;
416
417 if (sel_unchecked < 0 || sel_unchecked > mc->max)
418 return -EINVAL;
419 sel = sel_unchecked;
420
421 *select = sel;
422
423 /* Setting a volume is only valid if it is already On */
424 if (val >= 1) {
425 sel = sel + 1;
426 } else {
427 /* Write what was already there */
428 sel = val;
429 }
430
431 snd_soc_component_update_bits(component, mc->reg,
432 mask << mc->shift,
433 sel << mc->shift);
434
435 return *select != val;
436 }
437
438 static const char *max98090_perf_pwr_text[] =
439 { "High Performance", "Low Power" };
440 static const char *max98090_pwr_perf_text[] =
441 { "Low Power", "High Performance" };
442
443 static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum,
444 M98090_REG_BIAS_CONTROL,
445 M98090_VCM_MODE_SHIFT,
446 max98090_pwr_perf_text);
447
448 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
449
450 static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum,
451 M98090_REG_ADC_CONTROL,
452 M98090_OSR128_SHIFT,
453 max98090_osr128_text);
454
455 static const char *max98090_mode_text[] = { "Voice", "Music" };
456
457 static SOC_ENUM_SINGLE_DECL(max98090_mode_enum,
458 M98090_REG_FILTER_CONFIG,
459 M98090_MODE_SHIFT,
460 max98090_mode_text);
461
462 static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum,
463 M98090_REG_FILTER_CONFIG,
464 M98090_FLT_DMIC34MODE_SHIFT,
465 max98090_mode_text);
466
467 static const char *max98090_drcatk_text[] =
468 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
469
470 static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum,
471 M98090_REG_DRC_TIMING,
472 M98090_DRCATK_SHIFT,
473 max98090_drcatk_text);
474
475 static const char *max98090_drcrls_text[] =
476 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
477
478 static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum,
479 M98090_REG_DRC_TIMING,
480 M98090_DRCRLS_SHIFT,
481 max98090_drcrls_text);
482
483 static const char *max98090_alccmp_text[] =
484 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
485
486 static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum,
487 M98090_REG_DRC_COMPRESSOR,
488 M98090_DRCCMP_SHIFT,
489 max98090_alccmp_text);
490
491 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
492
493 static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum,
494 M98090_REG_DRC_EXPANDER,
495 M98090_DRCEXP_SHIFT,
496 max98090_drcexp_text);
497
498 static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum,
499 M98090_REG_DAC_CONTROL,
500 M98090_PERFMODE_SHIFT,
501 max98090_perf_pwr_text);
502
503 static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum,
504 M98090_REG_DAC_CONTROL,
505 M98090_DACHP_SHIFT,
506 max98090_pwr_perf_text);
507
508 static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
509 M98090_REG_ADC_CONTROL,
510 M98090_ADCHP_SHIFT,
511 max98090_pwr_perf_text);
512
513 static const struct snd_kcontrol_new max98090_snd_controls[] = {
514 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
515
516 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
517 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
518
519 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
520 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
521 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
522 max98090_put_enab_tlv, max98090_micboost_tlv),
523
524 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
525 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
526 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
527 max98090_put_enab_tlv, max98090_micboost_tlv),
528
529 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
530 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
531 max98090_mic_tlv),
532
533 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
534 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
535 max98090_mic_tlv),
536
537 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
538 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
539 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
540
541 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
542 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
543 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
544
545 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
546 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
547 max98090_line_tlv),
548
549 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
550 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
551 max98090_line_tlv),
552
553 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
554 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
555 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
556 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
557
558 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
559 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
560 max98090_avg_tlv),
561 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
562 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
563 max98090_avg_tlv),
564
565 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
566 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
567 max98090_av_tlv),
568 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
569 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
570 max98090_av_tlv),
571
572 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
573 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
574 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
575 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
576
577 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
578 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
579 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
580 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
581 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
582 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
583 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
584 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
585 SOC_ENUM("Filter Mode", max98090_mode_enum),
586 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
587 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
588 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
589 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
590 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
591 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
592 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
593 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
594 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
595 max98090_put_enab_tlv, max98090_sdg_tlv),
596 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
597 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
598 max98090_dvg_tlv),
599 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
600 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
601 max98090_dv_tlv),
602 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
603 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
604 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
605 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
606 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
607 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
608 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
609 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
610 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
611 1),
612 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
613 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
614 max98090_dv_tlv),
615
616 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
617 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
618 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
619 SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
620 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
621 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
622 max98090_alcmakeup_tlv),
623 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
624 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
625 SOC_SINGLE_TLV("ALC Compression Threshold Volume",
626 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
627 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
628 SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
629 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
630 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
631
632 SOC_ENUM("DAC HP Playback Performance Mode",
633 max98090_dac_perfmode_enum),
634 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
635
636 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
637 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
638 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
639 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
640 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
641 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
642
643 SOC_SINGLE_TLV("Speaker Left Mixer Volume",
644 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
645 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
646 SOC_SINGLE_TLV("Speaker Right Mixer Volume",
647 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
648 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
649
650 SOC_SINGLE_TLV("Receiver Left Mixer Volume",
651 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
652 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
653 SOC_SINGLE_TLV("Receiver Right Mixer Volume",
654 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
655 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
656
657 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
658 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
659 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
660
661 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
662 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
663 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
664 0, max98090_spk_tlv),
665
666 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
667 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
668 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
669
670 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
671 M98090_HPLM_SHIFT, 1, 1),
672 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
673 M98090_HPRM_SHIFT, 1, 1),
674
675 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
676 M98090_SPLM_SHIFT, 1, 1),
677 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
678 M98090_SPRM_SHIFT, 1, 1),
679
680 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
681 M98090_RCVLM_SHIFT, 1, 1),
682 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
683 M98090_RCVRM_SHIFT, 1, 1),
684
685 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
686 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
687 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
688 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
689 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
690 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
691
692 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
693 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
694 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
695 };
696
697 static const struct snd_kcontrol_new max98091_snd_controls[] = {
698
699 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
700 M98090_DMIC34_ZEROPAD_SHIFT,
701 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
702
703 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
704 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
705 M98090_FLT_DMIC34HPF_SHIFT,
706 M98090_FLT_DMIC34HPF_NUM - 1, 0),
707
708 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
709 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
710 max98090_avg_tlv),
711 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
712 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
713 max98090_avg_tlv),
714
715 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
716 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
717 max98090_av_tlv),
718 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
719 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
720 max98090_av_tlv),
721
722 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
723 M98090_REG_DMIC34_BIQUAD_BASE, 15),
724 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
725 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
726
727 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
728 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
729 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
730 };
731
max98090_micinput_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)732 static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
733 struct snd_kcontrol *kcontrol, int event)
734 {
735 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
736 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
737
738 unsigned int val = snd_soc_component_read(component, w->reg);
739
740 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
741 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
742 else
743 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
744
745 if (val >= 1) {
746 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
747 max98090->pa1en = val - 1; /* Update for volatile */
748 } else {
749 max98090->pa2en = val - 1; /* Update for volatile */
750 }
751 }
752
753 switch (event) {
754 case SND_SOC_DAPM_POST_PMU:
755 /* If turning on, set to most recently selected volume */
756 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
757 val = max98090->pa1en + 1;
758 else
759 val = max98090->pa2en + 1;
760 break;
761 case SND_SOC_DAPM_POST_PMD:
762 /* If turning off, turn off */
763 val = 0;
764 break;
765 default:
766 return -EINVAL;
767 }
768
769 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
770 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK,
771 val << M98090_MIC_PA1EN_SHIFT);
772 else
773 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK,
774 val << M98090_MIC_PA2EN_SHIFT);
775
776 return 0;
777 }
778
max98090_shdn_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)779 static int max98090_shdn_event(struct snd_soc_dapm_widget *w,
780 struct snd_kcontrol *kcontrol, int event)
781 {
782 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
783 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
784
785 if (event & SND_SOC_DAPM_POST_PMU)
786 max98090->shdn_pending = true;
787
788 return 0;
789
790 }
791
792 static const char *mic1_mux_text[] = { "IN12", "IN56" };
793
794 static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
795 M98090_REG_INPUT_MODE,
796 M98090_EXTMIC1_SHIFT,
797 mic1_mux_text);
798
799 static const struct snd_kcontrol_new max98090_mic1_mux =
800 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
801
802 static const char *mic2_mux_text[] = { "IN34", "IN56" };
803
804 static SOC_ENUM_SINGLE_DECL(mic2_mux_enum,
805 M98090_REG_INPUT_MODE,
806 M98090_EXTMIC2_SHIFT,
807 mic2_mux_text);
808
809 static const struct snd_kcontrol_new max98090_mic2_mux =
810 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
811
812 static const char *dmic_mux_text[] = { "ADC", "DMIC" };
813
814 static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text);
815
816 static const struct snd_kcontrol_new max98090_dmic_mux =
817 SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum);
818
819 /* LINEA mixer switch */
820 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
821 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
822 M98090_IN1SEEN_SHIFT, 1, 0),
823 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
824 M98090_IN3SEEN_SHIFT, 1, 0),
825 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
826 M98090_IN5SEEN_SHIFT, 1, 0),
827 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
828 M98090_IN34DIFF_SHIFT, 1, 0),
829 };
830
831 /* LINEB mixer switch */
832 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
833 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
834 M98090_IN2SEEN_SHIFT, 1, 0),
835 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
836 M98090_IN4SEEN_SHIFT, 1, 0),
837 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
838 M98090_IN6SEEN_SHIFT, 1, 0),
839 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
840 M98090_IN56DIFF_SHIFT, 1, 0),
841 };
842
843 /* Left ADC mixer switch */
844 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
845 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
846 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
847 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
848 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
849 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
850 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
851 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
852 M98090_MIXADL_LINEA_SHIFT, 1, 0),
853 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
854 M98090_MIXADL_LINEB_SHIFT, 1, 0),
855 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
856 M98090_MIXADL_MIC1_SHIFT, 1, 0),
857 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
858 M98090_MIXADL_MIC2_SHIFT, 1, 0),
859 };
860
861 /* Right ADC mixer switch */
862 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
863 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
864 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
865 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
866 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
867 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
868 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
869 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
870 M98090_MIXADR_LINEA_SHIFT, 1, 0),
871 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
872 M98090_MIXADR_LINEB_SHIFT, 1, 0),
873 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
874 M98090_MIXADR_MIC1_SHIFT, 1, 0),
875 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
876 M98090_MIXADR_MIC2_SHIFT, 1, 0),
877 };
878
879 static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
880
881 static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum,
882 M98090_REG_IO_CONFIGURATION,
883 M98090_LTEN_SHIFT,
884 lten_mux_text);
885
886 static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
887 M98090_REG_IO_CONFIGURATION,
888 M98090_LTEN_SHIFT,
889 lten_mux_text);
890
891 static const struct snd_kcontrol_new max98090_ltenl_mux =
892 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
893
894 static const struct snd_kcontrol_new max98090_ltenr_mux =
895 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
896
897 static const char *lben_mux_text[] = { "Normal", "Loopback" };
898
899 static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
900 M98090_REG_IO_CONFIGURATION,
901 M98090_LBEN_SHIFT,
902 lben_mux_text);
903
904 static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
905 M98090_REG_IO_CONFIGURATION,
906 M98090_LBEN_SHIFT,
907 lben_mux_text);
908
909 static const struct snd_kcontrol_new max98090_lbenl_mux =
910 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
911
912 static const struct snd_kcontrol_new max98090_lbenr_mux =
913 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
914
915 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
916
917 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
918
919 static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
920 M98090_REG_ADC_SIDETONE,
921 M98090_DSTSL_SHIFT,
922 stenl_mux_text);
923
924 static SOC_ENUM_SINGLE_DECL(stenr_mux_enum,
925 M98090_REG_ADC_SIDETONE,
926 M98090_DSTSR_SHIFT,
927 stenr_mux_text);
928
929 static const struct snd_kcontrol_new max98090_stenl_mux =
930 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
931
932 static const struct snd_kcontrol_new max98090_stenr_mux =
933 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
934
935 /* Left speaker mixer switch */
936 static const struct
937 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
938 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
939 M98090_MIXSPL_DACL_SHIFT, 1, 0),
940 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
941 M98090_MIXSPL_DACR_SHIFT, 1, 0),
942 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
943 M98090_MIXSPL_LINEA_SHIFT, 1, 0),
944 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
945 M98090_MIXSPL_LINEB_SHIFT, 1, 0),
946 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
947 M98090_MIXSPL_MIC1_SHIFT, 1, 0),
948 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
949 M98090_MIXSPL_MIC2_SHIFT, 1, 0),
950 };
951
952 /* Right speaker mixer switch */
953 static const struct
954 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
955 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
956 M98090_MIXSPR_DACL_SHIFT, 1, 0),
957 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
958 M98090_MIXSPR_DACR_SHIFT, 1, 0),
959 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
960 M98090_MIXSPR_LINEA_SHIFT, 1, 0),
961 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
962 M98090_MIXSPR_LINEB_SHIFT, 1, 0),
963 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
964 M98090_MIXSPR_MIC1_SHIFT, 1, 0),
965 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
966 M98090_MIXSPR_MIC2_SHIFT, 1, 0),
967 };
968
969 /* Left headphone mixer switch */
970 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
971 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
972 M98090_MIXHPL_DACL_SHIFT, 1, 0),
973 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
974 M98090_MIXHPL_DACR_SHIFT, 1, 0),
975 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
976 M98090_MIXHPL_LINEA_SHIFT, 1, 0),
977 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
978 M98090_MIXHPL_LINEB_SHIFT, 1, 0),
979 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
980 M98090_MIXHPL_MIC1_SHIFT, 1, 0),
981 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
982 M98090_MIXHPL_MIC2_SHIFT, 1, 0),
983 };
984
985 /* Right headphone mixer switch */
986 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
987 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
988 M98090_MIXHPR_DACL_SHIFT, 1, 0),
989 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
990 M98090_MIXHPR_DACR_SHIFT, 1, 0),
991 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
992 M98090_MIXHPR_LINEA_SHIFT, 1, 0),
993 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
994 M98090_MIXHPR_LINEB_SHIFT, 1, 0),
995 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
996 M98090_MIXHPR_MIC1_SHIFT, 1, 0),
997 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
998 M98090_MIXHPR_MIC2_SHIFT, 1, 0),
999 };
1000
1001 /* Left receiver mixer switch */
1002 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
1003 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1004 M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1005 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1006 M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1007 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1008 M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1009 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1010 M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1011 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1012 M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1013 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1014 M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1015 };
1016
1017 /* Right receiver mixer switch */
1018 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1019 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1020 M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1021 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1022 M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1023 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1024 M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1025 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1026 M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1027 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1028 M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1029 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1030 M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1031 };
1032
1033 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1034
1035 static SOC_ENUM_SINGLE_DECL(linmod_mux_enum,
1036 M98090_REG_LOUTR_MIXER,
1037 M98090_LINMOD_SHIFT,
1038 linmod_mux_text);
1039
1040 static const struct snd_kcontrol_new max98090_linmod_mux =
1041 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1042
1043 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1044
1045 /*
1046 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1047 */
1048 static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum,
1049 M98090_REG_HP_CONTROL,
1050 M98090_MIXHPLSEL_SHIFT,
1051 mixhpsel_mux_text);
1052
1053 static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1054 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1055
1056 static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum,
1057 M98090_REG_HP_CONTROL,
1058 M98090_MIXHPRSEL_SHIFT,
1059 mixhpsel_mux_text);
1060
1061 static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1062 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1063
1064 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1065 SND_SOC_DAPM_INPUT("MIC1"),
1066 SND_SOC_DAPM_INPUT("MIC2"),
1067 SND_SOC_DAPM_INPUT("DMICL"),
1068 SND_SOC_DAPM_INPUT("DMICR"),
1069 SND_SOC_DAPM_INPUT("IN1"),
1070 SND_SOC_DAPM_INPUT("IN2"),
1071 SND_SOC_DAPM_INPUT("IN3"),
1072 SND_SOC_DAPM_INPUT("IN4"),
1073 SND_SOC_DAPM_INPUT("IN5"),
1074 SND_SOC_DAPM_INPUT("IN6"),
1075 SND_SOC_DAPM_INPUT("IN12"),
1076 SND_SOC_DAPM_INPUT("IN34"),
1077 SND_SOC_DAPM_INPUT("IN56"),
1078
1079 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1080 M98090_MBEN_SHIFT, 0, NULL, 0),
1081 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1082 M98090_SHDNN_SHIFT, 0, NULL, 0),
1083 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1084 M98090_SDIEN_SHIFT, 0, NULL, 0),
1085 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1086 M98090_SDOEN_SHIFT, 0, NULL, 0),
1087 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1088 M98090_DIGMICL_SHIFT, 0, max98090_shdn_event,
1089 SND_SOC_DAPM_POST_PMU),
1090 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1091 M98090_DIGMICR_SHIFT, 0, max98090_shdn_event,
1092 SND_SOC_DAPM_POST_PMU),
1093 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1094 M98090_AHPF_SHIFT, 0, NULL, 0),
1095
1096 /*
1097 * Note: Sysclk and misc power supplies are taken care of by SHDN
1098 */
1099
1100 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1101 0, 0, &max98090_mic1_mux),
1102
1103 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1104 0, 0, &max98090_mic2_mux),
1105
1106 SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux),
1107
1108 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1109 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1110 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1111
1112 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1113 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1114 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1115
1116 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1117 &max98090_linea_mixer_controls[0],
1118 ARRAY_SIZE(max98090_linea_mixer_controls)),
1119
1120 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1121 &max98090_lineb_mixer_controls[0],
1122 ARRAY_SIZE(max98090_lineb_mixer_controls)),
1123
1124 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1125 M98090_LINEAEN_SHIFT, 0, NULL, 0),
1126 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1127 M98090_LINEBEN_SHIFT, 0, NULL, 0),
1128
1129 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1130 &max98090_left_adc_mixer_controls[0],
1131 ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1132
1133 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1134 &max98090_right_adc_mixer_controls[0],
1135 ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1136
1137 SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1138 M98090_ADLEN_SHIFT, 0, max98090_shdn_event,
1139 SND_SOC_DAPM_POST_PMU),
1140 SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1141 M98090_ADREN_SHIFT, 0, max98090_shdn_event,
1142 SND_SOC_DAPM_POST_PMU),
1143
1144 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1145 SND_SOC_NOPM, 0, 0),
1146 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1147 SND_SOC_NOPM, 0, 0),
1148
1149 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1150 0, 0, &max98090_lbenl_mux),
1151
1152 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1153 0, 0, &max98090_lbenr_mux),
1154
1155 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1156 0, 0, &max98090_ltenl_mux),
1157
1158 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1159 0, 0, &max98090_ltenr_mux),
1160
1161 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1162 0, 0, &max98090_stenl_mux),
1163
1164 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1165 0, 0, &max98090_stenr_mux),
1166
1167 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1168 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1169
1170 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1171 M98090_DALEN_SHIFT, 0),
1172 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1173 M98090_DAREN_SHIFT, 0),
1174
1175 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1176 &max98090_left_hp_mixer_controls[0],
1177 ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1178
1179 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1180 &max98090_right_hp_mixer_controls[0],
1181 ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1182
1183 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1184 &max98090_left_speaker_mixer_controls[0],
1185 ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1186
1187 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1188 &max98090_right_speaker_mixer_controls[0],
1189 ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1190
1191 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1192 &max98090_left_rcv_mixer_controls[0],
1193 ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1194
1195 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1196 &max98090_right_rcv_mixer_controls[0],
1197 ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1198
1199 SND_SOC_DAPM_MUX("LINMOD Mux", SND_SOC_NOPM, 0, 0,
1200 &max98090_linmod_mux),
1201
1202 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", SND_SOC_NOPM, 0, 0,
1203 &max98090_mixhplsel_mux),
1204
1205 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", SND_SOC_NOPM, 0, 0,
1206 &max98090_mixhprsel_mux),
1207
1208 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1209 M98090_HPLEN_SHIFT, 0, NULL, 0),
1210 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1211 M98090_HPREN_SHIFT, 0, NULL, 0),
1212
1213 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1214 M98090_SPLEN_SHIFT, 0, NULL, 0),
1215 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1216 M98090_SPREN_SHIFT, 0, NULL, 0),
1217
1218 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1219 M98090_RCVLEN_SHIFT, 0, NULL, 0),
1220 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1221 M98090_RCVREN_SHIFT, 0, NULL, 0),
1222
1223 SND_SOC_DAPM_OUTPUT("HPL"),
1224 SND_SOC_DAPM_OUTPUT("HPR"),
1225 SND_SOC_DAPM_OUTPUT("SPKL"),
1226 SND_SOC_DAPM_OUTPUT("SPKR"),
1227 SND_SOC_DAPM_OUTPUT("RCVL"),
1228 SND_SOC_DAPM_OUTPUT("RCVR"),
1229 };
1230
1231 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
1232 SND_SOC_DAPM_INPUT("DMIC3"),
1233 SND_SOC_DAPM_INPUT("DMIC4"),
1234
1235 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1236 M98090_DIGMIC3_SHIFT, 0, NULL, 0),
1237 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1238 M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1239 };
1240
1241 static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
1242 {"MIC1 Input", NULL, "MIC1"},
1243 {"MIC2 Input", NULL, "MIC2"},
1244
1245 {"DMICL", NULL, "DMICL_ENA"},
1246 {"DMICL", NULL, "DMICR_ENA"},
1247 {"DMICR", NULL, "DMICL_ENA"},
1248 {"DMICR", NULL, "DMICR_ENA"},
1249 {"DMICL", NULL, "AHPF"},
1250 {"DMICR", NULL, "AHPF"},
1251
1252 /* MIC1 input mux */
1253 {"MIC1 Mux", "IN12", "IN12"},
1254 {"MIC1 Mux", "IN56", "IN56"},
1255
1256 /* MIC2 input mux */
1257 {"MIC2 Mux", "IN34", "IN34"},
1258 {"MIC2 Mux", "IN56", "IN56"},
1259
1260 {"MIC1 Input", NULL, "MIC1 Mux"},
1261 {"MIC2 Input", NULL, "MIC2 Mux"},
1262
1263 /* Left ADC input mixer */
1264 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1265 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1266 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1267 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1268 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1269 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1270 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1271
1272 /* Right ADC input mixer */
1273 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1274 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1275 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1276 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1277 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1278 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1279 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1280
1281 /* Line A input mixer */
1282 {"LINEA Mixer", "IN1 Switch", "IN1"},
1283 {"LINEA Mixer", "IN3 Switch", "IN3"},
1284 {"LINEA Mixer", "IN5 Switch", "IN5"},
1285 {"LINEA Mixer", "IN34 Switch", "IN34"},
1286
1287 /* Line B input mixer */
1288 {"LINEB Mixer", "IN2 Switch", "IN2"},
1289 {"LINEB Mixer", "IN4 Switch", "IN4"},
1290 {"LINEB Mixer", "IN6 Switch", "IN6"},
1291 {"LINEB Mixer", "IN56 Switch", "IN56"},
1292
1293 {"LINEA Input", NULL, "LINEA Mixer"},
1294 {"LINEB Input", NULL, "LINEB Mixer"},
1295
1296 /* Inputs */
1297 {"ADCL", NULL, "Left ADC Mixer"},
1298 {"ADCR", NULL, "Right ADC Mixer"},
1299 {"ADCL", NULL, "SHDN"},
1300 {"ADCR", NULL, "SHDN"},
1301
1302 {"DMIC Mux", "ADC", "ADCL"},
1303 {"DMIC Mux", "ADC", "ADCR"},
1304 {"DMIC Mux", "DMIC", "DMICL"},
1305 {"DMIC Mux", "DMIC", "DMICR"},
1306
1307 {"LBENL Mux", "Normal", "DMIC Mux"},
1308 {"LBENL Mux", "Loopback", "LTENL Mux"},
1309 {"LBENR Mux", "Normal", "DMIC Mux"},
1310 {"LBENR Mux", "Loopback", "LTENR Mux"},
1311
1312 {"AIFOUTL", NULL, "LBENL Mux"},
1313 {"AIFOUTR", NULL, "LBENR Mux"},
1314 {"AIFOUTL", NULL, "SHDN"},
1315 {"AIFOUTR", NULL, "SHDN"},
1316 {"AIFOUTL", NULL, "SDOEN"},
1317 {"AIFOUTR", NULL, "SDOEN"},
1318
1319 {"LTENL Mux", "Normal", "AIFINL"},
1320 {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1321 {"LTENR Mux", "Normal", "AIFINR"},
1322 {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1323
1324 {"DACL", NULL, "LTENL Mux"},
1325 {"DACR", NULL, "LTENR Mux"},
1326
1327 {"STENL Mux", "Sidetone Left", "ADCL"},
1328 {"STENL Mux", "Sidetone Left", "DMICL"},
1329 {"STENR Mux", "Sidetone Right", "ADCR"},
1330 {"STENR Mux", "Sidetone Right", "DMICR"},
1331 {"DACL", NULL, "STENL Mux"},
1332 {"DACR", NULL, "STENR Mux"},
1333
1334 {"AIFINL", NULL, "SHDN"},
1335 {"AIFINR", NULL, "SHDN"},
1336 {"AIFINL", NULL, "SDIEN"},
1337 {"AIFINR", NULL, "SDIEN"},
1338 {"DACL", NULL, "SHDN"},
1339 {"DACR", NULL, "SHDN"},
1340
1341 /* Left headphone output mixer */
1342 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1343 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1344 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1345 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1346 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1347 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1348
1349 /* Right headphone output mixer */
1350 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1351 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1352 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1353 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1354 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1355 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1356
1357 /* Left speaker output mixer */
1358 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1359 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1360 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1361 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1362 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1363 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1364
1365 /* Right speaker output mixer */
1366 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1367 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1368 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1369 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1370 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1371 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1372
1373 /* Left Receiver output mixer */
1374 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1375 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1376 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1377 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1378 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1379 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1380
1381 /* Right Receiver output mixer */
1382 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1383 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1384 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1385 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1386 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1387 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1388
1389 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1390
1391 /*
1392 * Disable this for lowest power if bypassing
1393 * the DAC with an analog signal
1394 */
1395 {"HP Left Out", NULL, "DACL"},
1396 {"HP Left Out", NULL, "MIXHPLSEL Mux"},
1397
1398 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1399
1400 /*
1401 * Disable this for lowest power if bypassing
1402 * the DAC with an analog signal
1403 */
1404 {"HP Right Out", NULL, "DACR"},
1405 {"HP Right Out", NULL, "MIXHPRSEL Mux"},
1406
1407 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1408 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1409 {"RCV Left Out", NULL, "Left Receiver Mixer"},
1410
1411 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1412 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1413 {"RCV Right Out", NULL, "LINMOD Mux"},
1414
1415 {"HPL", NULL, "HP Left Out"},
1416 {"HPR", NULL, "HP Right Out"},
1417 {"SPKL", NULL, "SPK Left Out"},
1418 {"SPKR", NULL, "SPK Right Out"},
1419 {"RCVL", NULL, "RCV Left Out"},
1420 {"RCVR", NULL, "RCV Right Out"},
1421 };
1422
1423 static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
1424 /* DMIC inputs */
1425 {"DMIC3", NULL, "DMIC3_ENA"},
1426 {"DMIC4", NULL, "DMIC4_ENA"},
1427 {"DMIC3", NULL, "AHPF"},
1428 {"DMIC4", NULL, "AHPF"},
1429 };
1430
max98090_add_widgets(struct snd_soc_component * component)1431 static int max98090_add_widgets(struct snd_soc_component *component)
1432 {
1433 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1434 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1435
1436 snd_soc_add_component_controls(component, max98090_snd_controls,
1437 ARRAY_SIZE(max98090_snd_controls));
1438
1439 if (max98090->devtype == MAX98091) {
1440 snd_soc_add_component_controls(component, max98091_snd_controls,
1441 ARRAY_SIZE(max98091_snd_controls));
1442 }
1443
1444 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1445 ARRAY_SIZE(max98090_dapm_widgets));
1446
1447 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1448 ARRAY_SIZE(max98090_dapm_routes));
1449
1450 if (max98090->devtype == MAX98091) {
1451 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1452 ARRAY_SIZE(max98091_dapm_widgets));
1453
1454 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1455 ARRAY_SIZE(max98091_dapm_routes));
1456 }
1457
1458 return 0;
1459 }
1460
1461 static const int pclk_rates[] = {
1462 12000000, 12000000, 13000000, 13000000,
1463 16000000, 16000000, 19200000, 19200000
1464 };
1465
1466 static const int lrclk_rates[] = {
1467 8000, 16000, 8000, 16000,
1468 8000, 16000, 8000, 16000
1469 };
1470
1471 static const int user_pclk_rates[] = {
1472 13000000, 13000000, 19200000, 19200000,
1473 };
1474
1475 static const int user_lrclk_rates[] = {
1476 44100, 48000, 44100, 48000,
1477 };
1478
1479 static const unsigned long long ni_value[] = {
1480 3528, 768, 441, 8
1481 };
1482
1483 static const unsigned long long mi_value[] = {
1484 8125, 1625, 1500, 25
1485 };
1486
max98090_configure_bclk(struct snd_soc_component * component)1487 static void max98090_configure_bclk(struct snd_soc_component *component)
1488 {
1489 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1490 unsigned long long ni;
1491 int i;
1492
1493 if (!max98090->sysclk) {
1494 dev_err(component->dev, "No SYSCLK configured\n");
1495 return;
1496 }
1497
1498 if (!max98090->bclk || !max98090->lrclk) {
1499 dev_err(component->dev, "No audio clocks configured\n");
1500 return;
1501 }
1502
1503 /* Skip configuration when operating as slave */
1504 if (!(snd_soc_component_read(component, M98090_REG_MASTER_MODE) &
1505 M98090_MAS_MASK)) {
1506 return;
1507 }
1508
1509 /* Check for supported PCLK to LRCLK ratios */
1510 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1511 if ((pclk_rates[i] == max98090->sysclk) &&
1512 (lrclk_rates[i] == max98090->lrclk)) {
1513 dev_dbg(component->dev,
1514 "Found supported PCLK to LRCLK rates 0x%x\n",
1515 i + 0x8);
1516
1517 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1518 M98090_FREQ_MASK,
1519 (i + 0x8) << M98090_FREQ_SHIFT);
1520 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1521 M98090_USE_M1_MASK, 0);
1522 return;
1523 }
1524 }
1525
1526 /* Check for user calculated MI and NI ratios */
1527 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1528 if ((user_pclk_rates[i] == max98090->sysclk) &&
1529 (user_lrclk_rates[i] == max98090->lrclk)) {
1530 dev_dbg(component->dev,
1531 "Found user supported PCLK to LRCLK rates\n");
1532 dev_dbg(component->dev, "i %d ni %lld mi %lld\n",
1533 i, ni_value[i], mi_value[i]);
1534
1535 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1536 M98090_FREQ_MASK, 0);
1537 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1538 M98090_USE_M1_MASK,
1539 1 << M98090_USE_M1_SHIFT);
1540
1541 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB,
1542 (ni_value[i] >> 8) & 0x7F);
1543 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB,
1544 ni_value[i] & 0xFF);
1545 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_MSB,
1546 (mi_value[i] >> 8) & 0x7F);
1547 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_LSB,
1548 mi_value[i] & 0xFF);
1549
1550 return;
1551 }
1552 }
1553
1554 /*
1555 * Calculate based on MI = 65536 (not as good as either method above)
1556 */
1557 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1558 M98090_FREQ_MASK, 0);
1559 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1560 M98090_USE_M1_MASK, 0);
1561
1562 /*
1563 * Configure NI when operating as master
1564 * Note: There is a small, but significant audio quality improvement
1565 * by calculating ni and mi.
1566 */
1567 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1568 * (unsigned long long int)max98090->lrclk;
1569 do_div(ni, (unsigned long long int)max98090->sysclk);
1570 dev_info(component->dev, "No better method found\n");
1571 dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni);
1572 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB,
1573 (ni >> 8) & 0x7F);
1574 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
1575 }
1576
max98090_dai_set_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)1577 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1578 unsigned int fmt)
1579 {
1580 struct snd_soc_component *component = codec_dai->component;
1581 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1582 struct max98090_cdata *cdata;
1583 u8 regval;
1584
1585 max98090->dai_fmt = fmt;
1586 cdata = &max98090->dai[0];
1587
1588 if (fmt != cdata->fmt) {
1589 cdata->fmt = fmt;
1590
1591 regval = 0;
1592 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1593 case SND_SOC_DAIFMT_CBS_CFS:
1594 /* Set to slave mode PLL - MAS mode off */
1595 snd_soc_component_write(component,
1596 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1597 snd_soc_component_write(component,
1598 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1599 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1600 M98090_USE_M1_MASK, 0);
1601 max98090->master = false;
1602 break;
1603 case SND_SOC_DAIFMT_CBM_CFM:
1604 /* Set to master mode */
1605 if (max98090->tdm_slots == 4) {
1606 /* TDM */
1607 regval |= M98090_MAS_MASK |
1608 M98090_BSEL_64;
1609 } else if (max98090->tdm_slots == 3) {
1610 /* TDM */
1611 regval |= M98090_MAS_MASK |
1612 M98090_BSEL_48;
1613 } else {
1614 /* Few TDM slots, or No TDM */
1615 regval |= M98090_MAS_MASK |
1616 M98090_BSEL_32;
1617 }
1618 max98090->master = true;
1619 break;
1620 case SND_SOC_DAIFMT_CBS_CFM:
1621 case SND_SOC_DAIFMT_CBM_CFS:
1622 default:
1623 dev_err(component->dev, "DAI clock mode unsupported");
1624 return -EINVAL;
1625 }
1626 snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval);
1627
1628 regval = 0;
1629 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1630 case SND_SOC_DAIFMT_I2S:
1631 regval |= M98090_DLY_MASK;
1632 break;
1633 case SND_SOC_DAIFMT_LEFT_J:
1634 break;
1635 case SND_SOC_DAIFMT_RIGHT_J:
1636 regval |= M98090_RJ_MASK;
1637 break;
1638 case SND_SOC_DAIFMT_DSP_A:
1639 /* Not supported mode */
1640 default:
1641 dev_err(component->dev, "DAI format unsupported");
1642 return -EINVAL;
1643 }
1644
1645 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1646 case SND_SOC_DAIFMT_NB_NF:
1647 break;
1648 case SND_SOC_DAIFMT_NB_IF:
1649 regval |= M98090_WCI_MASK;
1650 break;
1651 case SND_SOC_DAIFMT_IB_NF:
1652 regval |= M98090_BCI_MASK;
1653 break;
1654 case SND_SOC_DAIFMT_IB_IF:
1655 regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1656 break;
1657 default:
1658 dev_err(component->dev, "DAI invert mode unsupported");
1659 return -EINVAL;
1660 }
1661
1662 /*
1663 * This accommodates an inverted logic in the MAX98090 chip
1664 * for Bit Clock Invert (BCI). The inverted logic is only
1665 * seen for the case of TDM mode. The remaining cases have
1666 * normal logic.
1667 */
1668 if (max98090->tdm_slots > 1)
1669 regval ^= M98090_BCI_MASK;
1670
1671 snd_soc_component_write(component,
1672 M98090_REG_INTERFACE_FORMAT, regval);
1673 }
1674
1675 return 0;
1676 }
1677
max98090_set_tdm_slot(struct snd_soc_dai * codec_dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1678 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1679 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1680 {
1681 struct snd_soc_component *component = codec_dai->component;
1682 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1683 struct max98090_cdata *cdata;
1684 cdata = &max98090->dai[0];
1685
1686 if (slots < 0 || slots > 4)
1687 return -EINVAL;
1688
1689 max98090->tdm_slots = slots;
1690 max98090->tdm_width = slot_width;
1691
1692 if (max98090->tdm_slots > 1) {
1693 /* SLOTL SLOTR SLOTDLY */
1694 snd_soc_component_write(component, M98090_REG_TDM_FORMAT,
1695 0 << M98090_TDM_SLOTL_SHIFT |
1696 1 << M98090_TDM_SLOTR_SHIFT |
1697 0 << M98090_TDM_SLOTDLY_SHIFT);
1698
1699 /* FSW TDM */
1700 snd_soc_component_update_bits(component, M98090_REG_TDM_CONTROL,
1701 M98090_TDM_MASK,
1702 M98090_TDM_MASK);
1703 }
1704
1705 /*
1706 * Normally advisable to set TDM first, but this permits either order
1707 */
1708 cdata->fmt = 0;
1709 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1710
1711 return 0;
1712 }
1713
max98090_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1714 static int max98090_set_bias_level(struct snd_soc_component *component,
1715 enum snd_soc_bias_level level)
1716 {
1717 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1718 int ret;
1719
1720 switch (level) {
1721 case SND_SOC_BIAS_ON:
1722 break;
1723
1724 case SND_SOC_BIAS_PREPARE:
1725 /*
1726 * SND_SOC_BIAS_PREPARE is called while preparing for a
1727 * transition to ON or away from ON. If current bias_level
1728 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1729 * away from ON. Disable the clock in that case, otherwise
1730 * enable it.
1731 */
1732 if (IS_ERR(max98090->mclk))
1733 break;
1734
1735 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
1736 clk_disable_unprepare(max98090->mclk);
1737 } else {
1738 ret = clk_prepare_enable(max98090->mclk);
1739 if (ret)
1740 return ret;
1741 }
1742 break;
1743
1744 case SND_SOC_BIAS_STANDBY:
1745 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1746 ret = regcache_sync(max98090->regmap);
1747 if (ret != 0) {
1748 dev_err(component->dev,
1749 "Failed to sync cache: %d\n", ret);
1750 return ret;
1751 }
1752 }
1753 break;
1754
1755 case SND_SOC_BIAS_OFF:
1756 /* Set internal pull-up to lowest power mode */
1757 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
1758 M98090_JDWK_MASK, M98090_JDWK_MASK);
1759 regcache_mark_dirty(max98090->regmap);
1760 break;
1761 }
1762 return 0;
1763 }
1764
1765 static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 };
1766
1767 static const int comp_lrclk_rates[] = {
1768 8000, 16000, 32000, 44100, 48000, 96000
1769 };
1770
1771 struct dmic_table {
1772 int pclk;
1773 struct {
1774 int freq;
1775 int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */
1776 } settings[6]; /* One for each dmic divisor. */
1777 };
1778
1779 static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */
1780 {
1781 .pclk = 11289600,
1782 .settings = {
1783 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1784 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1785 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1786 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1787 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1788 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1789 },
1790 },
1791 {
1792 .pclk = 12000000,
1793 .settings = {
1794 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1795 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1796 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1797 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1798 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1799 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1800 }
1801 },
1802 {
1803 .pclk = 12288000,
1804 .settings = {
1805 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1806 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1807 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1808 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1809 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1810 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1811 }
1812 },
1813 {
1814 .pclk = 13000000,
1815 .settings = {
1816 { .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } },
1817 { .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } },
1818 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1819 { .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } },
1820 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1821 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1822 }
1823 },
1824 {
1825 .pclk = 19200000,
1826 .settings = {
1827 { .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } },
1828 { .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } },
1829 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1830 { .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } },
1831 { .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } },
1832 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1833 }
1834 },
1835 };
1836
max98090_find_divisor(int target_freq,int pclk)1837 static int max98090_find_divisor(int target_freq, int pclk)
1838 {
1839 int current_diff = INT_MAX;
1840 int test_diff;
1841 int divisor_index = 0;
1842 int i;
1843
1844 for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) {
1845 test_diff = abs(target_freq - (pclk / dmic_divisors[i]));
1846 if (test_diff < current_diff) {
1847 current_diff = test_diff;
1848 divisor_index = i;
1849 }
1850 }
1851
1852 return divisor_index;
1853 }
1854
max98090_find_closest_pclk(int pclk)1855 static int max98090_find_closest_pclk(int pclk)
1856 {
1857 int m1;
1858 int m2;
1859 int i;
1860
1861 for (i = 0; i < ARRAY_SIZE(dmic_table); i++) {
1862 if (pclk == dmic_table[i].pclk)
1863 return i;
1864 if (pclk < dmic_table[i].pclk) {
1865 if (i == 0)
1866 return i;
1867 m1 = pclk - dmic_table[i-1].pclk;
1868 m2 = dmic_table[i].pclk - pclk;
1869 if (m1 < m2)
1870 return i - 1;
1871 else
1872 return i;
1873 }
1874 }
1875
1876 return -EINVAL;
1877 }
1878
max98090_configure_dmic(struct max98090_priv * max98090,int target_dmic_clk,int pclk,int fs)1879 static int max98090_configure_dmic(struct max98090_priv *max98090,
1880 int target_dmic_clk, int pclk, int fs)
1881 {
1882 int micclk_index;
1883 int pclk_index;
1884 int dmic_freq;
1885 int dmic_comp;
1886 int i;
1887
1888 pclk_index = max98090_find_closest_pclk(pclk);
1889 if (pclk_index < 0)
1890 return pclk_index;
1891
1892 micclk_index = max98090_find_divisor(target_dmic_clk, pclk);
1893
1894 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1895 if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2)
1896 break;
1897 }
1898
1899 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq;
1900 dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i];
1901
1902 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE,
1903 M98090_MICCLK_MASK,
1904 micclk_index << M98090_MICCLK_SHIFT);
1905
1906 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG,
1907 M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK,
1908 dmic_comp << M98090_DMIC_COMP_SHIFT |
1909 dmic_freq << M98090_DMIC_FREQ_SHIFT);
1910
1911 return 0;
1912 }
1913
max98090_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1914 static int max98090_dai_startup(struct snd_pcm_substream *substream,
1915 struct snd_soc_dai *dai)
1916 {
1917 struct snd_soc_component *component = dai->component;
1918 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1919 unsigned int fmt = max98090->dai_fmt;
1920
1921 /* Remove 24-bit format support if it is not in right justified mode. */
1922 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_RIGHT_J) {
1923 substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
1924 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16);
1925 }
1926 return 0;
1927 }
1928
max98090_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1929 static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1930 struct snd_pcm_hw_params *params,
1931 struct snd_soc_dai *dai)
1932 {
1933 struct snd_soc_component *component = dai->component;
1934 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1935 struct max98090_cdata *cdata;
1936
1937 cdata = &max98090->dai[0];
1938 max98090->bclk = snd_soc_params_to_bclk(params);
1939 if (params_channels(params) == 1)
1940 max98090->bclk *= 2;
1941
1942 max98090->lrclk = params_rate(params);
1943
1944 switch (params_width(params)) {
1945 case 16:
1946 snd_soc_component_update_bits(component, M98090_REG_INTERFACE_FORMAT,
1947 M98090_WS_MASK, 0);
1948 break;
1949 default:
1950 return -EINVAL;
1951 }
1952
1953 if (max98090->master)
1954 max98090_configure_bclk(component);
1955
1956 cdata->rate = max98090->lrclk;
1957
1958 /* Update filter mode */
1959 if (max98090->lrclk < 24000)
1960 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1961 M98090_MODE_MASK, 0);
1962 else
1963 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1964 M98090_MODE_MASK, M98090_MODE_MASK);
1965
1966 /* Update sample rate mode */
1967 if (max98090->lrclk < 50000)
1968 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1969 M98090_DHF_MASK, 0);
1970 else
1971 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1972 M98090_DHF_MASK, M98090_DHF_MASK);
1973
1974 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk,
1975 max98090->lrclk);
1976
1977 return 0;
1978 }
1979
1980 /*
1981 * PLL / Sysclk
1982 */
max98090_dai_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)1983 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
1984 int clk_id, unsigned int freq, int dir)
1985 {
1986 struct snd_soc_component *component = dai->component;
1987 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1988
1989 /* Requested clock frequency is already setup */
1990 if (freq == max98090->sysclk)
1991 return 0;
1992
1993 if (!IS_ERR(max98090->mclk)) {
1994 freq = clk_round_rate(max98090->mclk, freq);
1995 clk_set_rate(max98090->mclk, freq);
1996 }
1997
1998 /* Setup clocks for slave mode, and using the PLL
1999 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
2000 * 0x02 (when master clk is 20MHz to 40MHz)..
2001 * 0x03 (when master clk is 40MHz to 60MHz)..
2002 */
2003 if ((freq >= 10000000) && (freq <= 20000000)) {
2004 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2005 M98090_PSCLK_DIV1);
2006 max98090->pclk = freq;
2007 } else if ((freq > 20000000) && (freq <= 40000000)) {
2008 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2009 M98090_PSCLK_DIV2);
2010 max98090->pclk = freq >> 1;
2011 } else if ((freq > 40000000) && (freq <= 60000000)) {
2012 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2013 M98090_PSCLK_DIV4);
2014 max98090->pclk = freq >> 2;
2015 } else {
2016 dev_err(component->dev, "Invalid master clock frequency\n");
2017 return -EINVAL;
2018 }
2019
2020 max98090->sysclk = freq;
2021
2022 return 0;
2023 }
2024
max98090_dai_mute(struct snd_soc_dai * codec_dai,int mute,int direction)2025 static int max98090_dai_mute(struct snd_soc_dai *codec_dai, int mute,
2026 int direction)
2027 {
2028 struct snd_soc_component *component = codec_dai->component;
2029 int regval;
2030
2031 regval = mute ? M98090_DVM_MASK : 0;
2032 snd_soc_component_update_bits(component, M98090_REG_DAI_PLAYBACK_LEVEL,
2033 M98090_DVM_MASK, regval);
2034
2035 return 0;
2036 }
2037
max98090_dai_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)2038 static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd,
2039 struct snd_soc_dai *dai)
2040 {
2041 struct snd_soc_component *component = dai->component;
2042 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2043
2044 switch (cmd) {
2045 case SNDRV_PCM_TRIGGER_START:
2046 case SNDRV_PCM_TRIGGER_RESUME:
2047 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2048 if (!max98090->master && snd_soc_dai_active(dai) == 1)
2049 queue_delayed_work(system_power_efficient_wq,
2050 &max98090->pll_det_enable_work,
2051 msecs_to_jiffies(10));
2052 break;
2053 case SNDRV_PCM_TRIGGER_STOP:
2054 case SNDRV_PCM_TRIGGER_SUSPEND:
2055 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2056 if (!max98090->master && snd_soc_dai_active(dai) == 1)
2057 schedule_work(&max98090->pll_det_disable_work);
2058 break;
2059 default:
2060 break;
2061 }
2062
2063 return 0;
2064 }
2065
max98090_pll_det_enable_work(struct work_struct * work)2066 static void max98090_pll_det_enable_work(struct work_struct *work)
2067 {
2068 struct max98090_priv *max98090 =
2069 container_of(work, struct max98090_priv,
2070 pll_det_enable_work.work);
2071 struct snd_soc_component *component = max98090->component;
2072 unsigned int status, mask;
2073
2074 /*
2075 * Clear status register in order to clear possibly already occurred
2076 * PLL unlock. If PLL hasn't still locked, the status will be set
2077 * again and PLL unlock interrupt will occur.
2078 * Note this will clear all status bits
2079 */
2080 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2081
2082 /*
2083 * Queue jack work in case jack state has just changed but handler
2084 * hasn't run yet
2085 */
2086 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2087 status &= mask;
2088 if (status & M98090_JDET_MASK)
2089 queue_delayed_work(system_power_efficient_wq,
2090 &max98090->jack_work,
2091 msecs_to_jiffies(100));
2092
2093 /* Enable PLL unlock interrupt */
2094 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2095 M98090_IULK_MASK,
2096 1 << M98090_IULK_SHIFT);
2097 }
2098
max98090_pll_det_disable_work(struct work_struct * work)2099 static void max98090_pll_det_disable_work(struct work_struct *work)
2100 {
2101 struct max98090_priv *max98090 =
2102 container_of(work, struct max98090_priv, pll_det_disable_work);
2103 struct snd_soc_component *component = max98090->component;
2104
2105 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2106
2107 /* Disable PLL unlock interrupt */
2108 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2109 M98090_IULK_MASK, 0);
2110 }
2111
max98090_pll_work(struct max98090_priv * max98090)2112 static void max98090_pll_work(struct max98090_priv *max98090)
2113 {
2114 struct snd_soc_component *component = max98090->component;
2115 unsigned int pll;
2116 int i;
2117
2118 if (!snd_soc_component_active(component))
2119 return;
2120
2121 dev_info_ratelimited(component->dev, "PLL unlocked\n");
2122
2123 /*
2124 * As the datasheet suggested, the maximum PLL lock time should be
2125 * 7 msec. The workaround resets the codec softly by toggling SHDN
2126 * off and on if PLL failed to lock for 10 msec. Notably, there is
2127 * no suggested hold time for SHDN off.
2128 */
2129
2130 /* Toggle shutdown OFF then ON */
2131 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2132 M98090_SHDNN_MASK, 0);
2133 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2134 M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2135
2136 for (i = 0; i < 10; ++i) {
2137 /* Give PLL time to lock */
2138 usleep_range(1000, 1200);
2139
2140 /* Check lock status */
2141 pll = snd_soc_component_read(
2142 component, M98090_REG_DEVICE_STATUS);
2143 if (!(pll & M98090_ULK_MASK))
2144 break;
2145 }
2146 }
2147
max98090_jack_work(struct work_struct * work)2148 static void max98090_jack_work(struct work_struct *work)
2149 {
2150 struct max98090_priv *max98090 = container_of(work,
2151 struct max98090_priv,
2152 jack_work.work);
2153 struct snd_soc_component *component = max98090->component;
2154 int status = 0;
2155 int reg;
2156
2157 /* Read a second time */
2158 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
2159
2160 /* Strong pull up allows mic detection */
2161 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
2162 M98090_JDWK_MASK, 0);
2163
2164 msleep(50);
2165
2166 snd_soc_component_read(component, M98090_REG_JACK_STATUS);
2167
2168 /* Weak pull up allows only insertion detection */
2169 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
2170 M98090_JDWK_MASK, M98090_JDWK_MASK);
2171 }
2172
2173 reg = snd_soc_component_read(component, M98090_REG_JACK_STATUS);
2174
2175 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
2176 case M98090_LSNS_MASK | M98090_JKSNS_MASK:
2177 dev_dbg(component->dev, "No Headset Detected\n");
2178
2179 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2180
2181 status |= 0;
2182
2183 break;
2184
2185 case 0:
2186 if (max98090->jack_state ==
2187 M98090_JACK_STATE_HEADSET) {
2188
2189 dev_dbg(component->dev,
2190 "Headset Button Down Detected\n");
2191
2192 /*
2193 * max98090_headset_button_event(codec)
2194 * could be defined, then called here.
2195 */
2196
2197 status |= SND_JACK_HEADSET;
2198 status |= SND_JACK_BTN_0;
2199
2200 break;
2201 }
2202
2203 /* Line is reported as Headphone */
2204 /* Nokia Headset is reported as Headphone */
2205 /* Mono Headphone is reported as Headphone */
2206 dev_dbg(component->dev, "Headphone Detected\n");
2207
2208 max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2209
2210 status |= SND_JACK_HEADPHONE;
2211
2212 break;
2213
2214 case M98090_JKSNS_MASK:
2215 dev_dbg(component->dev, "Headset Detected\n");
2216
2217 max98090->jack_state = M98090_JACK_STATE_HEADSET;
2218
2219 status |= SND_JACK_HEADSET;
2220
2221 break;
2222
2223 default:
2224 dev_dbg(component->dev, "Unrecognized Jack Status\n");
2225 break;
2226 }
2227
2228 snd_soc_jack_report(max98090->jack, status,
2229 SND_JACK_HEADSET | SND_JACK_BTN_0);
2230 }
2231
max98090_interrupt(int irq,void * data)2232 static irqreturn_t max98090_interrupt(int irq, void *data)
2233 {
2234 struct max98090_priv *max98090 = data;
2235 struct snd_soc_component *component = max98090->component;
2236 int ret;
2237 unsigned int mask;
2238 unsigned int active;
2239
2240 /* Treat interrupt before codec is initialized as spurious */
2241 if (component == NULL)
2242 return IRQ_NONE;
2243
2244 dev_dbg(component->dev, "***** max98090_interrupt *****\n");
2245
2246 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2247
2248 if (ret != 0) {
2249 dev_err(component->dev,
2250 "failed to read M98090_REG_INTERRUPT_S: %d\n",
2251 ret);
2252 return IRQ_NONE;
2253 }
2254
2255 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2256
2257 if (ret != 0) {
2258 dev_err(component->dev,
2259 "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2260 ret);
2261 return IRQ_NONE;
2262 }
2263
2264 dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2265 active, mask, active & mask);
2266
2267 active &= mask;
2268
2269 if (!active)
2270 return IRQ_NONE;
2271
2272 if (active & M98090_CLD_MASK)
2273 dev_err(component->dev, "M98090_CLD_MASK\n");
2274
2275 if (active & M98090_SLD_MASK)
2276 dev_dbg(component->dev, "M98090_SLD_MASK\n");
2277
2278 if (active & M98090_ULK_MASK) {
2279 dev_dbg(component->dev, "M98090_ULK_MASK\n");
2280 max98090_pll_work(max98090);
2281 }
2282
2283 if (active & M98090_JDET_MASK) {
2284 dev_dbg(component->dev, "M98090_JDET_MASK\n");
2285
2286 pm_wakeup_event(component->dev, 100);
2287
2288 queue_delayed_work(system_power_efficient_wq,
2289 &max98090->jack_work,
2290 msecs_to_jiffies(100));
2291 }
2292
2293 if (active & M98090_DRCACT_MASK)
2294 dev_dbg(component->dev, "M98090_DRCACT_MASK\n");
2295
2296 if (active & M98090_DRCCLP_MASK)
2297 dev_err(component->dev, "M98090_DRCCLP_MASK\n");
2298
2299 return IRQ_HANDLED;
2300 }
2301
2302 /**
2303 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2304 *
2305 * @component: MAX98090 component
2306 * @jack: jack to report detection events on
2307 *
2308 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2309 * being used to bring out signals to the processor then only platform
2310 * data configuration is needed for MAX98090 and processor GPIOs should
2311 * be configured using snd_soc_jack_add_gpios() instead.
2312 *
2313 * If no jack is supplied detection will be disabled.
2314 */
max98090_mic_detect(struct snd_soc_component * component,struct snd_soc_jack * jack)2315 int max98090_mic_detect(struct snd_soc_component *component,
2316 struct snd_soc_jack *jack)
2317 {
2318 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2319
2320 dev_dbg(component->dev, "max98090_mic_detect\n");
2321
2322 max98090->jack = jack;
2323 if (jack) {
2324 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2325 M98090_IJDET_MASK,
2326 1 << M98090_IJDET_SHIFT);
2327 } else {
2328 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2329 M98090_IJDET_MASK,
2330 0);
2331 }
2332
2333 /* Send an initial empty report */
2334 snd_soc_jack_report(max98090->jack, 0,
2335 SND_JACK_HEADSET | SND_JACK_BTN_0);
2336
2337 queue_delayed_work(system_power_efficient_wq,
2338 &max98090->jack_work,
2339 msecs_to_jiffies(100));
2340
2341 return 0;
2342 }
2343 EXPORT_SYMBOL_GPL(max98090_mic_detect);
2344
2345 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2346 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2347
2348 static const struct snd_soc_dai_ops max98090_dai_ops = {
2349 .startup = max98090_dai_startup,
2350 .set_sysclk = max98090_dai_set_sysclk,
2351 .set_fmt = max98090_dai_set_fmt,
2352 .set_tdm_slot = max98090_set_tdm_slot,
2353 .hw_params = max98090_dai_hw_params,
2354 .mute_stream = max98090_dai_mute,
2355 .trigger = max98090_dai_trigger,
2356 .no_capture_mute = 1,
2357 };
2358
2359 static struct snd_soc_dai_driver max98090_dai[] = {
2360 {
2361 .name = "HiFi",
2362 .playback = {
2363 .stream_name = "HiFi Playback",
2364 .channels_min = 2,
2365 .channels_max = 2,
2366 .rates = MAX98090_RATES,
2367 .formats = MAX98090_FORMATS,
2368 },
2369 .capture = {
2370 .stream_name = "HiFi Capture",
2371 .channels_min = 1,
2372 .channels_max = 2,
2373 .rates = MAX98090_RATES,
2374 .formats = MAX98090_FORMATS,
2375 },
2376 .ops = &max98090_dai_ops,
2377 }
2378 };
2379
max98090_probe(struct snd_soc_component * component)2380 static int max98090_probe(struct snd_soc_component *component)
2381 {
2382 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2383 struct max98090_cdata *cdata;
2384 enum max98090_type devtype;
2385 int ret = 0;
2386 int err;
2387 unsigned int micbias;
2388
2389 dev_dbg(component->dev, "max98090_probe\n");
2390
2391 max98090->mclk = devm_clk_get(component->dev, "mclk");
2392 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER)
2393 return -EPROBE_DEFER;
2394
2395 max98090->component = component;
2396
2397 /* Reset the codec, the DSP core, and disable all interrupts */
2398 max98090_reset(max98090);
2399
2400 /* Initialize private data */
2401
2402 max98090->sysclk = (unsigned)-1;
2403 max98090->pclk = (unsigned)-1;
2404 max98090->master = false;
2405
2406 cdata = &max98090->dai[0];
2407 cdata->rate = (unsigned)-1;
2408 cdata->fmt = (unsigned)-1;
2409
2410 max98090->lin_state = 0;
2411 max98090->pa1en = 0;
2412 max98090->pa2en = 0;
2413
2414 ret = snd_soc_component_read(component, M98090_REG_REVISION_ID);
2415 if (ret < 0) {
2416 dev_err(component->dev, "Failed to read device revision: %d\n",
2417 ret);
2418 goto err_access;
2419 }
2420
2421 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
2422 devtype = MAX98090;
2423 dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret);
2424 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
2425 devtype = MAX98091;
2426 dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret);
2427 } else {
2428 devtype = MAX98090;
2429 dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret);
2430 }
2431
2432 if (max98090->devtype != devtype) {
2433 dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n");
2434 max98090->devtype = devtype;
2435 }
2436
2437 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2438
2439 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2440 INIT_DELAYED_WORK(&max98090->pll_det_enable_work,
2441 max98090_pll_det_enable_work);
2442 INIT_WORK(&max98090->pll_det_disable_work,
2443 max98090_pll_det_disable_work);
2444
2445 /* Enable jack detection */
2446 snd_soc_component_write(component, M98090_REG_JACK_DETECT,
2447 M98090_JDETEN_MASK | M98090_JDEB_25MS);
2448
2449 /*
2450 * Clear any old interrupts.
2451 * An old interrupt ocurring prior to installing the ISR
2452 * can keep a new interrupt from generating a trigger.
2453 */
2454 snd_soc_component_read(component, M98090_REG_DEVICE_STATUS);
2455
2456 /* High Performance is default */
2457 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
2458 M98090_DACHP_MASK,
2459 1 << M98090_DACHP_SHIFT);
2460 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
2461 M98090_PERFMODE_MASK,
2462 0 << M98090_PERFMODE_SHIFT);
2463 snd_soc_component_update_bits(component, M98090_REG_ADC_CONTROL,
2464 M98090_ADCHP_MASK,
2465 1 << M98090_ADCHP_SHIFT);
2466
2467 /* Turn on VCM bandgap reference */
2468 snd_soc_component_write(component, M98090_REG_BIAS_CONTROL,
2469 M98090_VCM_MODE_MASK);
2470
2471 err = device_property_read_u32(component->dev, "maxim,micbias", &micbias);
2472 if (err) {
2473 micbias = M98090_MBVSEL_2V8;
2474 dev_info(component->dev, "use default 2.8v micbias\n");
2475 } else if (micbias > M98090_MBVSEL_2V8) {
2476 dev_err(component->dev, "micbias out of range 0x%x\n", micbias);
2477 micbias = M98090_MBVSEL_2V8;
2478 }
2479
2480 snd_soc_component_update_bits(component, M98090_REG_MIC_BIAS_VOLTAGE,
2481 M98090_MBVSEL_MASK, micbias);
2482
2483 max98090_add_widgets(component);
2484
2485 err_access:
2486 return ret;
2487 }
2488
max98090_remove(struct snd_soc_component * component)2489 static void max98090_remove(struct snd_soc_component *component)
2490 {
2491 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2492
2493 cancel_delayed_work_sync(&max98090->jack_work);
2494 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2495 cancel_work_sync(&max98090->pll_det_disable_work);
2496 max98090->component = NULL;
2497 }
2498
max98090_seq_notifier(struct snd_soc_component * component,enum snd_soc_dapm_type event,int subseq)2499 static void max98090_seq_notifier(struct snd_soc_component *component,
2500 enum snd_soc_dapm_type event, int subseq)
2501 {
2502 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2503
2504 if (max98090->shdn_pending) {
2505 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2506 M98090_SHDNN_MASK, 0);
2507 msleep(40);
2508 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2509 M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2510 max98090->shdn_pending = false;
2511 }
2512 }
2513
2514 static const struct snd_soc_component_driver soc_component_dev_max98090 = {
2515 .probe = max98090_probe,
2516 .remove = max98090_remove,
2517 .seq_notifier = max98090_seq_notifier,
2518 .set_bias_level = max98090_set_bias_level,
2519 .idle_bias_on = 1,
2520 .use_pmdown_time = 1,
2521 .endianness = 1,
2522 .non_legacy_dai_naming = 1,
2523 };
2524
2525 static const struct regmap_config max98090_regmap = {
2526 .reg_bits = 8,
2527 .val_bits = 8,
2528
2529 .max_register = MAX98090_MAX_REGISTER,
2530 .reg_defaults = max98090_reg,
2531 .num_reg_defaults = ARRAY_SIZE(max98090_reg),
2532 .volatile_reg = max98090_volatile_register,
2533 .readable_reg = max98090_readable_register,
2534 .cache_type = REGCACHE_RBTREE,
2535 };
2536
max98090_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * i2c_id)2537 static int max98090_i2c_probe(struct i2c_client *i2c,
2538 const struct i2c_device_id *i2c_id)
2539 {
2540 struct max98090_priv *max98090;
2541 const struct acpi_device_id *acpi_id;
2542 kernel_ulong_t driver_data = 0;
2543 int ret;
2544
2545 pr_debug("max98090_i2c_probe\n");
2546
2547 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2548 GFP_KERNEL);
2549 if (max98090 == NULL)
2550 return -ENOMEM;
2551
2552 if (ACPI_HANDLE(&i2c->dev)) {
2553 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table,
2554 &i2c->dev);
2555 if (!acpi_id) {
2556 dev_err(&i2c->dev, "No driver data\n");
2557 return -EINVAL;
2558 }
2559 driver_data = acpi_id->driver_data;
2560 } else if (i2c_id) {
2561 driver_data = i2c_id->driver_data;
2562 }
2563
2564 max98090->devtype = driver_data;
2565 i2c_set_clientdata(i2c, max98090);
2566 max98090->pdata = i2c->dev.platform_data;
2567
2568 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq",
2569 &max98090->dmic_freq);
2570 if (ret < 0)
2571 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ;
2572
2573 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
2574 if (IS_ERR(max98090->regmap)) {
2575 ret = PTR_ERR(max98090->regmap);
2576 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2577 goto err_enable;
2578 }
2579
2580 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2581 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2582 "max98090_interrupt", max98090);
2583 if (ret < 0) {
2584 dev_err(&i2c->dev, "request_irq failed: %d\n",
2585 ret);
2586 return ret;
2587 }
2588
2589 ret = devm_snd_soc_register_component(&i2c->dev,
2590 &soc_component_dev_max98090, max98090_dai,
2591 ARRAY_SIZE(max98090_dai));
2592 err_enable:
2593 return ret;
2594 }
2595
max98090_i2c_shutdown(struct i2c_client * i2c)2596 static void max98090_i2c_shutdown(struct i2c_client *i2c)
2597 {
2598 struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev);
2599
2600 /*
2601 * Enable volume smoothing, disable zero cross. This will cause
2602 * a quick 40ms ramp to mute on shutdown.
2603 */
2604 regmap_write(max98090->regmap,
2605 M98090_REG_LEVEL_CONTROL, M98090_VSENN_MASK);
2606 regmap_write(max98090->regmap,
2607 M98090_REG_DEVICE_SHUTDOWN, 0x00);
2608 msleep(40);
2609 }
2610
max98090_i2c_remove(struct i2c_client * client)2611 static int max98090_i2c_remove(struct i2c_client *client)
2612 {
2613 max98090_i2c_shutdown(client);
2614
2615 return 0;
2616 }
2617
2618 #ifdef CONFIG_PM
max98090_runtime_resume(struct device * dev)2619 static int max98090_runtime_resume(struct device *dev)
2620 {
2621 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2622
2623 regcache_cache_only(max98090->regmap, false);
2624
2625 max98090_reset(max98090);
2626
2627 regcache_sync(max98090->regmap);
2628
2629 return 0;
2630 }
2631
max98090_runtime_suspend(struct device * dev)2632 static int max98090_runtime_suspend(struct device *dev)
2633 {
2634 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2635
2636 regcache_cache_only(max98090->regmap, true);
2637
2638 return 0;
2639 }
2640 #endif
2641
2642 #ifdef CONFIG_PM_SLEEP
max98090_resume(struct device * dev)2643 static int max98090_resume(struct device *dev)
2644 {
2645 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2646 unsigned int status;
2647
2648 regcache_mark_dirty(max98090->regmap);
2649
2650 max98090_reset(max98090);
2651
2652 /* clear IRQ status */
2653 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2654
2655 regcache_sync(max98090->regmap);
2656
2657 return 0;
2658 }
2659 #endif
2660
2661 static const struct dev_pm_ops max98090_pm = {
2662 SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2663 max98090_runtime_resume, NULL)
2664 SET_SYSTEM_SLEEP_PM_OPS(NULL, max98090_resume)
2665 };
2666
2667 static const struct i2c_device_id max98090_i2c_id[] = {
2668 { "max98090", MAX98090 },
2669 { "max98091", MAX98091 },
2670 { }
2671 };
2672 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
2673
2674 #ifdef CONFIG_OF
2675 static const struct of_device_id max98090_of_match[] = {
2676 { .compatible = "maxim,max98090", },
2677 { .compatible = "maxim,max98091", },
2678 { }
2679 };
2680 MODULE_DEVICE_TABLE(of, max98090_of_match);
2681 #endif
2682
2683 #ifdef CONFIG_ACPI
2684 static const struct acpi_device_id max98090_acpi_match[] = {
2685 { "193C9890", MAX98090 },
2686 { }
2687 };
2688 MODULE_DEVICE_TABLE(acpi, max98090_acpi_match);
2689 #endif
2690
2691 static struct i2c_driver max98090_i2c_driver = {
2692 .driver = {
2693 .name = "max98090",
2694 .pm = &max98090_pm,
2695 .of_match_table = of_match_ptr(max98090_of_match),
2696 .acpi_match_table = ACPI_PTR(max98090_acpi_match),
2697 },
2698 .probe = max98090_i2c_probe,
2699 .shutdown = max98090_i2c_shutdown,
2700 .remove = max98090_i2c_remove,
2701 .id_table = max98090_i2c_id,
2702 };
2703
2704 module_i2c_driver(max98090_i2c_driver);
2705
2706 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2707 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2708 MODULE_LICENSE("GPL");
2709