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Searched refs:DOMAIN0_PG_CONFIG (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_hwseq.h202 SR(DOMAIN0_PG_CONFIG), \
246 SR(DOMAIN0_PG_CONFIG), \
310 SR(DOMAIN0_PG_CONFIG), \
391 SR(DOMAIN0_PG_CONFIG), \
443 SR(DOMAIN0_PG_CONFIG), \
559 uint32_t DOMAIN0_PG_CONFIG; member
744 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
745 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
779 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
780 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
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/drivers/gpu/drm/amd/display/dc/dcn302/
Ddcn302_hwseq.c109 if (REG(DOMAIN0_PG_CONFIG) == 0) in dcn302_hubp_pg_control()
114 REG_UPDATE(DOMAIN0_PG_CONFIG, in dcn302_hubp_pg_control()
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_hwseq.c371 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); in dcn31_enable_power_gating_plane()
451 if (REG(DOMAIN0_PG_CONFIG) == 0) in dcn31_hubp_pg_control()
456 REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate); in dcn31_hubp_pg_control()
Ddcn31_resource.c784 SR(DOMAIN0_PG_CONFIG), \
816 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
817 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c195 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); in dcn20_enable_power_gating_plane()
500 if (REG(DOMAIN0_PG_CONFIG) == 0) in dcn20_hubp_pg_control()
505 REG_UPDATE(DOMAIN0_PG_CONFIG, in dcn20_hubp_pg_control()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c499 REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); in dcn10_enable_power_gating_plane()
624 if (REG(DOMAIN0_PG_CONFIG) == 0) in dcn10_hubp_pg_control()
629 REG_UPDATE(DOMAIN0_PG_CONFIG, in dcn10_hubp_pg_control()