1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * linux/arch/alpha/kernel/core_mcpcia.c
4 *
5 * Based on code written by David A Rusling (david.rusling@reo.mts.dec.com).
6 *
7 * Code common to all MCbus-PCI Adaptor core logic chipsets
8 */
9
10 #define __EXTERN_INLINE inline
11 #include <asm/io.h>
12 #include <asm/core_mcpcia.h>
13 #undef __EXTERN_INLINE
14
15 #include <linux/types.h>
16 #include <linux/pci.h>
17 #include <linux/sched.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20
21 #include <asm/ptrace.h>
22
23 #include "proto.h"
24 #include "pci_impl.h"
25
26 /*
27 * NOTE: Herein lie back-to-back mb instructions. They are magic.
28 * One plausible explanation is that the i/o controller does not properly
29 * handle the system transaction. Another involves timing. Ho hum.
30 */
31
32 /*
33 * BIOS32-style PCI interface:
34 */
35
36 #define DEBUG_CFG 0
37
38 #if DEBUG_CFG
39 # define DBG_CFG(args) printk args
40 #else
41 # define DBG_CFG(args)
42 #endif
43
44 /*
45 * Given a bus, device, and function number, compute resulting
46 * configuration space address and setup the MCPCIA_HAXR2 register
47 * accordingly. It is therefore not safe to have concurrent
48 * invocations to configuration space access routines, but there
49 * really shouldn't be any need for this.
50 *
51 * Type 0:
52 *
53 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
54 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
55 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
56 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
57 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
58 *
59 * 31:11 Device select bit.
60 * 10:8 Function number
61 * 7:2 Register number
62 *
63 * Type 1:
64 *
65 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
66 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
67 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
68 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
69 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
70 *
71 * 31:24 reserved
72 * 23:16 bus number (8 bits = 128 possible buses)
73 * 15:11 Device number (5 bits)
74 * 10:8 function number
75 * 7:2 register number
76 *
77 * Notes:
78 * The function number selects which function of a multi-function device
79 * (e.g., SCSI and Ethernet).
80 *
81 * The register selects a DWORD (32 bit) register offset. Hence it
82 * doesn't get shifted by 2 bits as we want to "drop" the bottom two
83 * bits.
84 */
85
86 static unsigned int
conf_read(unsigned long addr,unsigned char type1,struct pci_controller * hose)87 conf_read(unsigned long addr, unsigned char type1,
88 struct pci_controller *hose)
89 {
90 unsigned long flags;
91 unsigned long mid = MCPCIA_HOSE2MID(hose->index);
92 unsigned int stat0, value, cpu;
93
94 cpu = smp_processor_id();
95
96 local_irq_save(flags);
97
98 DBG_CFG(("conf_read(addr=0x%lx, type1=%d, hose=%d)\n",
99 addr, type1, mid));
100
101 /* Reset status register to avoid losing errors. */
102 stat0 = *(vuip)MCPCIA_CAP_ERR(mid);
103 *(vuip)MCPCIA_CAP_ERR(mid) = stat0;
104 mb();
105 *(vuip)MCPCIA_CAP_ERR(mid);
106 DBG_CFG(("conf_read: MCPCIA_CAP_ERR(%d) was 0x%x\n", mid, stat0));
107
108 mb();
109 draina();
110 mcheck_expected(cpu) = 1;
111 mcheck_taken(cpu) = 0;
112 mcheck_extra(cpu) = mid;
113 mb();
114
115 /* Access configuration space. */
116 value = *((vuip)addr);
117 mb();
118 mb(); /* magic */
119
120 if (mcheck_taken(cpu)) {
121 mcheck_taken(cpu) = 0;
122 value = 0xffffffffU;
123 mb();
124 }
125 mcheck_expected(cpu) = 0;
126 mb();
127
128 DBG_CFG(("conf_read(): finished\n"));
129
130 local_irq_restore(flags);
131 return value;
132 }
133
134 static void
conf_write(unsigned long addr,unsigned int value,unsigned char type1,struct pci_controller * hose)135 conf_write(unsigned long addr, unsigned int value, unsigned char type1,
136 struct pci_controller *hose)
137 {
138 unsigned long flags;
139 unsigned long mid = MCPCIA_HOSE2MID(hose->index);
140 unsigned int stat0, cpu;
141
142 cpu = smp_processor_id();
143
144 local_irq_save(flags); /* avoid getting hit by machine check */
145
146 /* Reset status register to avoid losing errors. */
147 stat0 = *(vuip)MCPCIA_CAP_ERR(mid);
148 *(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb();
149 *(vuip)MCPCIA_CAP_ERR(mid);
150 DBG_CFG(("conf_write: MCPCIA CAP_ERR(%d) was 0x%x\n", mid, stat0));
151
152 draina();
153 mcheck_expected(cpu) = 1;
154 mcheck_extra(cpu) = mid;
155 mb();
156
157 /* Access configuration space. */
158 *((vuip)addr) = value;
159 mb();
160 mb(); /* magic */
161 *(vuip)MCPCIA_CAP_ERR(mid); /* read to force the write */
162 mcheck_expected(cpu) = 0;
163 mb();
164
165 DBG_CFG(("conf_write(): finished\n"));
166 local_irq_restore(flags);
167 }
168
169 static int
mk_conf_addr(struct pci_bus * pbus,unsigned int devfn,int where,struct pci_controller * hose,unsigned long * pci_addr,unsigned char * type1)170 mk_conf_addr(struct pci_bus *pbus, unsigned int devfn, int where,
171 struct pci_controller *hose, unsigned long *pci_addr,
172 unsigned char *type1)
173 {
174 u8 bus = pbus->number;
175 unsigned long addr;
176
177 DBG_CFG(("mk_conf_addr(bus=%d,devfn=0x%x,hose=%d,where=0x%x,"
178 " pci_addr=0x%p, type1=0x%p)\n",
179 bus, devfn, hose->index, where, pci_addr, type1));
180
181 /* Type 1 configuration cycle for *ALL* busses. */
182 *type1 = 1;
183
184 if (!pbus->parent) /* No parent means peer PCI bus. */
185 bus = 0;
186 addr = (bus << 16) | (devfn << 8) | (where);
187 addr <<= 5; /* swizzle for SPARSE */
188 addr |= hose->config_space_base;
189
190 *pci_addr = addr;
191 DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
192 return 0;
193 }
194
195 static int
mcpcia_read_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * value)196 mcpcia_read_config(struct pci_bus *bus, unsigned int devfn, int where,
197 int size, u32 *value)
198 {
199 struct pci_controller *hose = bus->sysdata;
200 unsigned long addr, w;
201 unsigned char type1;
202
203 if (mk_conf_addr(bus, devfn, where, hose, &addr, &type1))
204 return PCIBIOS_DEVICE_NOT_FOUND;
205
206 addr |= (size - 1) * 8;
207 w = conf_read(addr, type1, hose);
208 switch (size) {
209 case 1:
210 *value = __kernel_extbl(w, where & 3);
211 break;
212 case 2:
213 *value = __kernel_extwl(w, where & 3);
214 break;
215 case 4:
216 *value = w;
217 break;
218 }
219 return PCIBIOS_SUCCESSFUL;
220 }
221
222 static int
mcpcia_write_config(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 value)223 mcpcia_write_config(struct pci_bus *bus, unsigned int devfn, int where,
224 int size, u32 value)
225 {
226 struct pci_controller *hose = bus->sysdata;
227 unsigned long addr;
228 unsigned char type1;
229
230 if (mk_conf_addr(bus, devfn, where, hose, &addr, &type1))
231 return PCIBIOS_DEVICE_NOT_FOUND;
232
233 addr |= (size - 1) * 8;
234 value = __kernel_insql(value, where & 3);
235 conf_write(addr, value, type1, hose);
236 return PCIBIOS_SUCCESSFUL;
237 }
238
239 struct pci_ops mcpcia_pci_ops =
240 {
241 .read = mcpcia_read_config,
242 .write = mcpcia_write_config,
243 };
244
245 void
mcpcia_pci_tbi(struct pci_controller * hose,dma_addr_t start,dma_addr_t end)246 mcpcia_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
247 {
248 wmb();
249 *(vuip)MCPCIA_SG_TBIA(MCPCIA_HOSE2MID(hose->index)) = 0;
250 mb();
251 }
252
253 static int __init
mcpcia_probe_hose(int h)254 mcpcia_probe_hose(int h)
255 {
256 int cpu = smp_processor_id();
257 int mid = MCPCIA_HOSE2MID(h);
258 unsigned int pci_rev;
259
260 /* Gotta be REAL careful. If hose is absent, we get an mcheck. */
261
262 mb();
263 mb();
264 draina();
265 wrmces(7);
266
267 mcheck_expected(cpu) = 2; /* indicates probing */
268 mcheck_taken(cpu) = 0;
269 mcheck_extra(cpu) = mid;
270 mb();
271
272 /* Access the bus revision word. */
273 pci_rev = *(vuip)MCPCIA_REV(mid);
274
275 mb();
276 mb(); /* magic */
277 if (mcheck_taken(cpu)) {
278 mcheck_taken(cpu) = 0;
279 pci_rev = 0xffffffff;
280 mb();
281 }
282 mcheck_expected(cpu) = 0;
283 mb();
284
285 return (pci_rev >> 16) == PCI_CLASS_BRIDGE_HOST;
286 }
287
288 static void __init
mcpcia_new_hose(int h)289 mcpcia_new_hose(int h)
290 {
291 struct pci_controller *hose;
292 struct resource *io, *mem, *hae_mem;
293 int mid = MCPCIA_HOSE2MID(h);
294
295 hose = alloc_pci_controller();
296 if (h == 0)
297 pci_isa_hose = hose;
298 io = alloc_resource();
299 mem = alloc_resource();
300 hae_mem = alloc_resource();
301
302 hose->io_space = io;
303 hose->mem_space = hae_mem;
304 hose->sparse_mem_base = MCPCIA_SPARSE(mid) - IDENT_ADDR;
305 hose->dense_mem_base = MCPCIA_DENSE(mid) - IDENT_ADDR;
306 hose->sparse_io_base = MCPCIA_IO(mid) - IDENT_ADDR;
307 hose->dense_io_base = 0;
308 hose->config_space_base = MCPCIA_CONF(mid);
309 hose->index = h;
310
311 io->start = MCPCIA_IO(mid) - MCPCIA_IO_BIAS;
312 io->end = io->start + 0xffff;
313 io->name = pci_io_names[h];
314 io->flags = IORESOURCE_IO;
315
316 mem->start = MCPCIA_DENSE(mid) - MCPCIA_MEM_BIAS;
317 mem->end = mem->start + 0xffffffff;
318 mem->name = pci_mem_names[h];
319 mem->flags = IORESOURCE_MEM;
320
321 hae_mem->start = mem->start;
322 hae_mem->end = mem->start + MCPCIA_MEM_MASK;
323 hae_mem->name = pci_hae0_name;
324 hae_mem->flags = IORESOURCE_MEM;
325
326 if (request_resource(&ioport_resource, io) < 0)
327 printk(KERN_ERR "Failed to request IO on hose %d\n", h);
328 if (request_resource(&iomem_resource, mem) < 0)
329 printk(KERN_ERR "Failed to request MEM on hose %d\n", h);
330 if (request_resource(mem, hae_mem) < 0)
331 printk(KERN_ERR "Failed to request HAE_MEM on hose %d\n", h);
332 }
333
334 static void
mcpcia_pci_clr_err(int mid)335 mcpcia_pci_clr_err(int mid)
336 {
337 *(vuip)MCPCIA_CAP_ERR(mid);
338 *(vuip)MCPCIA_CAP_ERR(mid) = 0xffffffff; /* Clear them all. */
339 mb();
340 *(vuip)MCPCIA_CAP_ERR(mid); /* Re-read for force write. */
341 }
342
343 static void __init
mcpcia_startup_hose(struct pci_controller * hose)344 mcpcia_startup_hose(struct pci_controller *hose)
345 {
346 int mid = MCPCIA_HOSE2MID(hose->index);
347 unsigned int tmp;
348
349 mcpcia_pci_clr_err(mid);
350
351 /*
352 * Set up error reporting.
353 */
354 tmp = *(vuip)MCPCIA_CAP_ERR(mid);
355 tmp |= 0x0006; /* master/target abort */
356 *(vuip)MCPCIA_CAP_ERR(mid) = tmp;
357 mb();
358 tmp = *(vuip)MCPCIA_CAP_ERR(mid);
359
360 /*
361 * Set up the PCI->physical memory translation windows.
362 *
363 * Window 0 is scatter-gather 8MB at 8MB (for isa)
364 * Window 1 is scatter-gather (up to) 1GB at 1GB (for pci)
365 * Window 2 is direct access 2GB at 2GB
366 */
367 hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000,
368 SMP_CACHE_BYTES);
369 hose->sg_pci = iommu_arena_new(hose, 0x40000000,
370 size_for_memory(0x40000000),
371 SMP_CACHE_BYTES);
372
373 __direct_map_base = 0x80000000;
374 __direct_map_size = 0x80000000;
375
376 *(vuip)MCPCIA_W0_BASE(mid) = hose->sg_isa->dma_base | 3;
377 *(vuip)MCPCIA_W0_MASK(mid) = (hose->sg_isa->size - 1) & 0xfff00000;
378 *(vuip)MCPCIA_T0_BASE(mid) = virt_to_phys(hose->sg_isa->ptes) >> 8;
379
380 *(vuip)MCPCIA_W1_BASE(mid) = hose->sg_pci->dma_base | 3;
381 *(vuip)MCPCIA_W1_MASK(mid) = (hose->sg_pci->size - 1) & 0xfff00000;
382 *(vuip)MCPCIA_T1_BASE(mid) = virt_to_phys(hose->sg_pci->ptes) >> 8;
383
384 *(vuip)MCPCIA_W2_BASE(mid) = __direct_map_base | 1;
385 *(vuip)MCPCIA_W2_MASK(mid) = (__direct_map_size - 1) & 0xfff00000;
386 *(vuip)MCPCIA_T2_BASE(mid) = 0;
387
388 *(vuip)MCPCIA_W3_BASE(mid) = 0x0;
389
390 mcpcia_pci_tbi(hose, 0, -1);
391
392 *(vuip)MCPCIA_HBASE(mid) = 0x0;
393 mb();
394
395 *(vuip)MCPCIA_HAE_MEM(mid) = 0U;
396 mb();
397 *(vuip)MCPCIA_HAE_MEM(mid); /* read it back. */
398 *(vuip)MCPCIA_HAE_IO(mid) = 0;
399 mb();
400 *(vuip)MCPCIA_HAE_IO(mid); /* read it back. */
401 }
402
403 void __init
mcpcia_init_arch(void)404 mcpcia_init_arch(void)
405 {
406 /* With multiple PCI busses, we play with I/O as physical addrs. */
407 ioport_resource.end = ~0UL;
408
409 /* Allocate hose 0. That's the one that all the ISA junk hangs
410 off of, from which we'll be registering stuff here in a bit.
411 Other hose detection is done in mcpcia_init_hoses, which is
412 called from init_IRQ. */
413
414 mcpcia_new_hose(0);
415 }
416
417 /* This is called from init_IRQ, since we cannot take interrupts
418 before then. Which means we cannot do this in init_arch. */
419
420 void __init
mcpcia_init_hoses(void)421 mcpcia_init_hoses(void)
422 {
423 struct pci_controller *hose;
424 int hose_count;
425 int h;
426
427 /* First, find how many hoses we have. */
428 hose_count = 0;
429 for (h = 0; h < MCPCIA_MAX_HOSES; ++h) {
430 if (mcpcia_probe_hose(h)) {
431 if (h != 0)
432 mcpcia_new_hose(h);
433 hose_count++;
434 }
435 }
436
437 printk("mcpcia_init_hoses: found %d hoses\n", hose_count);
438
439 /* Now do init for each hose. */
440 for (hose = hose_head; hose; hose = hose->next)
441 mcpcia_startup_hose(hose);
442 }
443
444 static void
mcpcia_print_uncorrectable(struct el_MCPCIA_uncorrected_frame_mcheck * logout)445 mcpcia_print_uncorrectable(struct el_MCPCIA_uncorrected_frame_mcheck *logout)
446 {
447 struct el_common_EV5_uncorrectable_mcheck *frame;
448 int i;
449
450 frame = &logout->procdata;
451
452 /* Print PAL fields */
453 for (i = 0; i < 24; i += 2) {
454 printk(" paltmp[%d-%d] = %16lx %16lx\n",
455 i, i+1, frame->paltemp[i], frame->paltemp[i+1]);
456 }
457 for (i = 0; i < 8; i += 2) {
458 printk(" shadow[%d-%d] = %16lx %16lx\n",
459 i, i+1, frame->shadow[i],
460 frame->shadow[i+1]);
461 }
462 printk(" Addr of excepting instruction = %16lx\n",
463 frame->exc_addr);
464 printk(" Summary of arithmetic traps = %16lx\n",
465 frame->exc_sum);
466 printk(" Exception mask = %16lx\n",
467 frame->exc_mask);
468 printk(" Base address for PALcode = %16lx\n",
469 frame->pal_base);
470 printk(" Interrupt Status Reg = %16lx\n",
471 frame->isr);
472 printk(" CURRENT SETUP OF EV5 IBOX = %16lx\n",
473 frame->icsr);
474 printk(" I-CACHE Reg %s parity error = %16lx\n",
475 (frame->ic_perr_stat & 0x800L) ?
476 "Data" : "Tag",
477 frame->ic_perr_stat);
478 printk(" D-CACHE error Reg = %16lx\n",
479 frame->dc_perr_stat);
480 if (frame->dc_perr_stat & 0x2) {
481 switch (frame->dc_perr_stat & 0x03c) {
482 case 8:
483 printk(" Data error in bank 1\n");
484 break;
485 case 4:
486 printk(" Data error in bank 0\n");
487 break;
488 case 20:
489 printk(" Tag error in bank 1\n");
490 break;
491 case 10:
492 printk(" Tag error in bank 0\n");
493 break;
494 }
495 }
496 printk(" Effective VA = %16lx\n",
497 frame->va);
498 printk(" Reason for D-stream = %16lx\n",
499 frame->mm_stat);
500 printk(" EV5 SCache address = %16lx\n",
501 frame->sc_addr);
502 printk(" EV5 SCache TAG/Data parity = %16lx\n",
503 frame->sc_stat);
504 printk(" EV5 BC_TAG_ADDR = %16lx\n",
505 frame->bc_tag_addr);
506 printk(" EV5 EI_ADDR: Phys addr of Xfer = %16lx\n",
507 frame->ei_addr);
508 printk(" Fill Syndrome = %16lx\n",
509 frame->fill_syndrome);
510 printk(" EI_STAT reg = %16lx\n",
511 frame->ei_stat);
512 printk(" LD_LOCK = %16lx\n",
513 frame->ld_lock);
514 }
515
516 static void
mcpcia_print_system_area(unsigned long la_ptr)517 mcpcia_print_system_area(unsigned long la_ptr)
518 {
519 struct el_common *frame;
520 struct pci_controller *hose;
521
522 struct IOD_subpacket {
523 unsigned long base;
524 unsigned int whoami;
525 unsigned int rsvd1;
526 unsigned int pci_rev;
527 unsigned int cap_ctrl;
528 unsigned int hae_mem;
529 unsigned int hae_io;
530 unsigned int int_ctl;
531 unsigned int int_reg;
532 unsigned int int_mask0;
533 unsigned int int_mask1;
534 unsigned int mc_err0;
535 unsigned int mc_err1;
536 unsigned int cap_err;
537 unsigned int rsvd2;
538 unsigned int pci_err1;
539 unsigned int mdpa_stat;
540 unsigned int mdpa_syn;
541 unsigned int mdpb_stat;
542 unsigned int mdpb_syn;
543 unsigned int rsvd3;
544 unsigned int rsvd4;
545 unsigned int rsvd5;
546 } *iodpp;
547
548 frame = (struct el_common *)la_ptr;
549 iodpp = (struct IOD_subpacket *) (la_ptr + frame->sys_offset);
550
551 for (hose = hose_head; hose; hose = hose->next, iodpp++) {
552
553 printk("IOD %d Register Subpacket - Bridge Base Address %16lx\n",
554 hose->index, iodpp->base);
555 printk(" WHOAMI = %8x\n", iodpp->whoami);
556 printk(" PCI_REV = %8x\n", iodpp->pci_rev);
557 printk(" CAP_CTRL = %8x\n", iodpp->cap_ctrl);
558 printk(" HAE_MEM = %8x\n", iodpp->hae_mem);
559 printk(" HAE_IO = %8x\n", iodpp->hae_io);
560 printk(" INT_CTL = %8x\n", iodpp->int_ctl);
561 printk(" INT_REG = %8x\n", iodpp->int_reg);
562 printk(" INT_MASK0 = %8x\n", iodpp->int_mask0);
563 printk(" INT_MASK1 = %8x\n", iodpp->int_mask1);
564 printk(" MC_ERR0 = %8x\n", iodpp->mc_err0);
565 printk(" MC_ERR1 = %8x\n", iodpp->mc_err1);
566 printk(" CAP_ERR = %8x\n", iodpp->cap_err);
567 printk(" PCI_ERR1 = %8x\n", iodpp->pci_err1);
568 printk(" MDPA_STAT = %8x\n", iodpp->mdpa_stat);
569 printk(" MDPA_SYN = %8x\n", iodpp->mdpa_syn);
570 printk(" MDPB_STAT = %8x\n", iodpp->mdpb_stat);
571 printk(" MDPB_SYN = %8x\n", iodpp->mdpb_syn);
572 }
573 }
574
575 void
mcpcia_machine_check(unsigned long vector,unsigned long la_ptr)576 mcpcia_machine_check(unsigned long vector, unsigned long la_ptr)
577 {
578 struct el_MCPCIA_uncorrected_frame_mcheck *mchk_logout;
579 unsigned int cpu = smp_processor_id();
580 int expected;
581
582 mchk_logout = (struct el_MCPCIA_uncorrected_frame_mcheck *)la_ptr;
583 expected = mcheck_expected(cpu);
584
585 mb();
586 mb(); /* magic */
587 draina();
588
589 switch (expected) {
590 case 0:
591 {
592 /* FIXME: how do we figure out which hose the
593 error was on? */
594 struct pci_controller *hose;
595 for (hose = hose_head; hose; hose = hose->next)
596 mcpcia_pci_clr_err(MCPCIA_HOSE2MID(hose->index));
597 break;
598 }
599 case 1:
600 mcpcia_pci_clr_err(mcheck_extra(cpu));
601 break;
602 default:
603 /* Otherwise, we're being called from mcpcia_probe_hose
604 and there's no hose clear an error from. */
605 break;
606 }
607
608 wrmces(0x7);
609 mb();
610
611 process_mcheck_info(vector, la_ptr, "MCPCIA", expected != 0);
612 if (!expected && vector != 0x620 && vector != 0x630) {
613 mcpcia_print_uncorrectable(mchk_logout);
614 mcpcia_print_system_area(la_ptr);
615 }
616 }
617