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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device Tree file for the Turris Omnia
4 *
5 * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
6 * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
7 *
8 * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
9 */
10
11/dts-v1/;
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/leds/common.h>
16#include "armada-385.dtsi"
17
18/ {
19	model = "Turris Omnia";
20	compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
21
22	chosen {
23		stdout-path = &uart0;
24	};
25
26	aliases {
27		ethernet0 = &eth0;
28		ethernet1 = &eth1;
29		ethernet2 = &eth2;
30	};
31
32	memory {
33		device_type = "memory";
34		reg = <0x00000000 0x40000000>; /* 1024 MB */
35	};
36
37	soc {
38		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
39			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
40			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
41			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
42			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
43
44		internal-regs {
45
46			/* USB part of the PCIe2/USB 2.0 port */
47			usb@58000 {
48				status = "okay";
49			};
50
51			sata@a8000 {
52				status = "okay";
53			};
54
55			sdhci@d8000 {
56				pinctrl-names = "default";
57				pinctrl-0 = <&sdhci_pins>;
58				status = "okay";
59
60				bus-width = <8>;
61				no-1-8-v;
62				non-removable;
63			};
64
65			usb3@f0000 {
66				status = "okay";
67			};
68
69			usb3@f8000 {
70				status = "okay";
71			};
72		};
73
74		pcie {
75			status = "okay";
76
77			pcie@1,0 {
78				/* Port 0, Lane 0 */
79				status = "okay";
80			};
81
82			pcie@2,0 {
83				/* Port 1, Lane 0 */
84				status = "okay";
85			};
86
87			pcie@3,0 {
88				/* Port 2, Lane 0 */
89				status = "okay";
90			};
91		};
92	};
93
94	sfp: sfp {
95		compatible = "sff,sfp";
96		i2c-bus = <&sfp_i2c>;
97		tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>;
98		tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>;
99		rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>;
100		los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>;
101		mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>;
102		maximum-power-milliwatt = <3000>;
103
104		/*
105		 * For now this has to be enabled at boot time by U-Boot when
106		 * a SFP module is present. Read more in the comment in the
107		 * eth2 node below.
108		 */
109		status = "disabled";
110	};
111};
112
113&bm {
114	status = "okay";
115};
116
117&bm_bppi {
118	status = "okay";
119};
120
121/* Connected to 88E6176 switch, port 6 */
122&eth0 {
123	pinctrl-names = "default";
124	pinctrl-0 = <&ge0_rgmii_pins>;
125	status = "okay";
126	phy-mode = "rgmii";
127	buffer-manager = <&bm>;
128	bm,pool-long = <0>;
129	bm,pool-short = <3>;
130
131	fixed-link {
132		speed = <1000>;
133		full-duplex;
134	};
135};
136
137/* Connected to 88E6176 switch, port 5 */
138&eth1 {
139	pinctrl-names = "default";
140	pinctrl-0 = <&ge1_rgmii_pins>;
141	status = "okay";
142	phy-mode = "rgmii";
143	buffer-manager = <&bm>;
144	bm,pool-long = <1>;
145	bm,pool-short = <3>;
146
147	fixed-link {
148		speed = <1000>;
149		full-duplex;
150	};
151};
152
153/* WAN port */
154&eth2 {
155	/*
156	 * eth2 is connected via a multiplexor to both the SFP cage and to
157	 * ethernet-phy@1. The multiplexor switches the signal to SFP cage when
158	 * a SFP module is present, as determined by the mode-def0 GPIO.
159	 *
160	 * Until kernel supports this configuration properly, in case SFP module
161	 * is present, U-Boot has to enable the sfp node above, remove phy
162	 * handle and add managed = "in-band-status" property.
163	 */
164	status = "okay";
165	phy-mode = "sgmii";
166	phy-handle = <&phy1>;
167	phys = <&comphy5 2>;
168	sfp = <&sfp>;
169	buffer-manager = <&bm>;
170	bm,pool-long = <2>;
171	bm,pool-short = <3>;
172};
173
174&i2c0 {
175	pinctrl-names = "default";
176	pinctrl-0 = <&i2c0_pins>;
177	status = "okay";
178
179	i2cmux@70 {
180		compatible = "nxp,pca9547";
181		#address-cells = <1>;
182		#size-cells = <0>;
183		reg = <0x70>;
184
185		i2c@0 {
186			#address-cells = <1>;
187			#size-cells = <0>;
188			reg = <0>;
189
190			/* STM32F0 command interface at address 0x2a */
191
192			led-controller@2b {
193				compatible = "cznic,turris-omnia-leds";
194				reg = <0x2b>;
195				#address-cells = <1>;
196				#size-cells = <0>;
197
198				/*
199				 * LEDs are controlled by MCU (STM32F0) at
200				 * address 0x2b.
201				 *
202				 * The driver does not support HW control mode
203				 * for the LEDs yet. Disable the LEDs for now.
204				 *
205				 * Also LED functions are not stable yet:
206				 * - there are 3 LEDs connected via MCU to PCIe
207				 *   ports. One of these ports supports mSATA.
208				 *   There is no mSATA nor PCIe function.
209				 *   For now we use LED_FUNCTION_WLAN, since
210				 *   in most cases users have wifi cards in
211				 *   these slots
212				 * - there are 2 LEDs dedicated for user: A and
213				 *   B. Again there is no such function defined.
214				 *   For now we use LED_FUNCTION_INDICATOR
215				 */
216				status = "disabled";
217
218				multi-led@0 {
219					reg = <0x0>;
220					color = <LED_COLOR_ID_RGB>;
221					function = LED_FUNCTION_INDICATOR;
222					function-enumerator = <2>;
223				};
224
225				multi-led@1 {
226					reg = <0x1>;
227					color = <LED_COLOR_ID_RGB>;
228					function = LED_FUNCTION_INDICATOR;
229					function-enumerator = <1>;
230				};
231
232				multi-led@2 {
233					reg = <0x2>;
234					color = <LED_COLOR_ID_RGB>;
235					function = LED_FUNCTION_WLAN;
236					function-enumerator = <3>;
237				};
238
239				multi-led@3 {
240					reg = <0x3>;
241					color = <LED_COLOR_ID_RGB>;
242					function = LED_FUNCTION_WLAN;
243					function-enumerator = <2>;
244				};
245
246				multi-led@4 {
247					reg = <0x4>;
248					color = <LED_COLOR_ID_RGB>;
249					function = LED_FUNCTION_WLAN;
250					function-enumerator = <1>;
251				};
252
253				multi-led@5 {
254					reg = <0x5>;
255					color = <LED_COLOR_ID_RGB>;
256					function = LED_FUNCTION_WAN;
257				};
258
259				multi-led@6 {
260					reg = <0x6>;
261					color = <LED_COLOR_ID_RGB>;
262					function = LED_FUNCTION_LAN;
263					function-enumerator = <4>;
264				};
265
266				multi-led@7 {
267					reg = <0x7>;
268					color = <LED_COLOR_ID_RGB>;
269					function = LED_FUNCTION_LAN;
270					function-enumerator = <3>;
271				};
272
273				multi-led@8 {
274					reg = <0x8>;
275					color = <LED_COLOR_ID_RGB>;
276					function = LED_FUNCTION_LAN;
277					function-enumerator = <2>;
278				};
279
280				multi-led@9 {
281					reg = <0x9>;
282					color = <LED_COLOR_ID_RGB>;
283					function = LED_FUNCTION_LAN;
284					function-enumerator = <1>;
285				};
286
287				multi-led@a {
288					reg = <0xa>;
289					color = <LED_COLOR_ID_RGB>;
290					function = LED_FUNCTION_LAN;
291					function-enumerator = <0>;
292				};
293
294				multi-led@b {
295					reg = <0xb>;
296					color = <LED_COLOR_ID_RGB>;
297					function = LED_FUNCTION_POWER;
298				};
299			};
300
301			eeprom@54 {
302				compatible = "atmel,24c64";
303				reg = <0x54>;
304
305				/* The EEPROM contains data for bootloader.
306				 * Contents:
307				 * 	struct omnia_eeprom {
308				 * 		u32 magic; (=0x0341a034 in LE)
309				 *		u32 ramsize; (in GiB)
310				 * 		char regdomain[4];
311				 * 		u32 crc32;
312				 * 	};
313				 */
314			};
315		};
316
317		i2c@1 {
318			#address-cells = <1>;
319			#size-cells = <0>;
320			reg = <1>;
321
322			/* routed to PCIe0/mSATA connector (CN7A) */
323		};
324
325		i2c@2 {
326			#address-cells = <1>;
327			#size-cells = <0>;
328			reg = <2>;
329
330			/* routed to PCIe1/USB2 connector (CN61A) */
331		};
332
333		i2c@3 {
334			#address-cells = <1>;
335			#size-cells = <0>;
336			reg = <3>;
337
338			/* routed to PCIe2 connector (CN62A) */
339		};
340
341		sfp_i2c: i2c@4 {
342			#address-cells = <1>;
343			#size-cells = <0>;
344			reg = <4>;
345
346			/* routed to SFP+ */
347		};
348
349		i2c@5 {
350			#address-cells = <1>;
351			#size-cells = <0>;
352			reg = <5>;
353
354			/* ATSHA204A at address 0x64 */
355		};
356
357		i2c@6 {
358			#address-cells = <1>;
359			#size-cells = <0>;
360			reg = <6>;
361
362			/* exposed on pin header */
363		};
364
365		i2c@7 {
366			#address-cells = <1>;
367			#size-cells = <0>;
368			reg = <7>;
369
370			pcawan: gpio@71 {
371				/*
372				 * GPIO expander for SFP+ signals and
373				 * and phy irq
374				 */
375				compatible = "nxp,pca9538";
376				reg = <0x71>;
377
378				pinctrl-names = "default";
379				pinctrl-0 = <&pcawan_pins>;
380
381				interrupt-parent = <&gpio1>;
382				interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
383
384				gpio-controller;
385				#gpio-cells = <2>;
386			};
387		};
388	};
389};
390
391&mdio {
392	pinctrl-names = "default";
393	pinctrl-0 = <&mdio_pins>;
394	status = "okay";
395
396	phy1: ethernet-phy@1 {
397		compatible = "ethernet-phy-ieee802.3-c22";
398		reg = <1>;
399		marvell,reg-init = <3 18 0 0x4985>;
400
401		/* irq is connected to &pcawan pin 7 */
402	};
403
404	/* Switch MV88E6176 at address 0x10 */
405	switch@10 {
406		pinctrl-names = "default";
407		pinctrl-0 = <&swint_pins>;
408		compatible = "marvell,mv88e6085";
409		#address-cells = <1>;
410		#size-cells = <0>;
411
412		dsa,member = <0 0>;
413		reg = <0x10>;
414
415		interrupt-parent = <&gpio1>;
416		interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
417
418		ports {
419			#address-cells = <1>;
420			#size-cells = <0>;
421
422			ports@0 {
423				reg = <0>;
424				label = "lan0";
425			};
426
427			ports@1 {
428				reg = <1>;
429				label = "lan1";
430			};
431
432			ports@2 {
433				reg = <2>;
434				label = "lan2";
435			};
436
437			ports@3 {
438				reg = <3>;
439				label = "lan3";
440			};
441
442			ports@4 {
443				reg = <4>;
444				label = "lan4";
445			};
446
447			ports@5 {
448				reg = <5>;
449				label = "cpu";
450				ethernet = <&eth1>;
451				phy-mode = "rgmii-id";
452
453				fixed-link {
454					speed = <1000>;
455					full-duplex;
456				};
457			};
458
459			ports@6 {
460				reg = <6>;
461				label = "cpu";
462				ethernet = <&eth0>;
463				phy-mode = "rgmii-id";
464
465				fixed-link {
466					speed = <1000>;
467					full-duplex;
468				};
469			};
470		};
471	};
472};
473
474&pinctrl {
475	pcawan_pins: pcawan-pins {
476		marvell,pins = "mpp46";
477		marvell,function = "gpio";
478	};
479
480	swint_pins: swint-pins {
481		marvell,pins = "mpp45";
482		marvell,function = "gpio";
483	};
484
485	spi0cs0_pins: spi0cs0-pins {
486		marvell,pins = "mpp25";
487		marvell,function = "spi0";
488	};
489
490	spi0cs2_pins: spi0cs2-pins {
491		marvell,pins = "mpp26";
492		marvell,function = "spi0";
493	};
494};
495
496&spi0 {
497	pinctrl-names = "default";
498	pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
499	status = "okay";
500
501	spi-nor@0 {
502		compatible = "spansion,s25fl164k", "jedec,spi-nor";
503		#address-cells = <1>;
504		#size-cells = <1>;
505		reg = <0>;
506		spi-max-frequency = <40000000>;
507
508		partitions {
509			compatible = "fixed-partitions";
510			#address-cells = <1>;
511			#size-cells = <1>;
512
513			partition@0 {
514				reg = <0x0 0x00100000>;
515				label = "U-Boot";
516			};
517
518			partition@100000 {
519				reg = <0x00100000 0x00700000>;
520				label = "Rescue system";
521			};
522		};
523	};
524
525	/* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */
526};
527
528&uart0 {
529	/* Pin header CN10 */
530	pinctrl-names = "default";
531	pinctrl-0 = <&uart0_pins>;
532	status = "okay";
533};
534
535&uart1 {
536	/* Pin header CN11 */
537	pinctrl-names = "default";
538	pinctrl-0 = <&uart1_pins>;
539	status = "okay";
540};
541