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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7
8/ {
9	model = "Phytec phyFLEX-i.MX6 Quad";
10	compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
11
12	memory@10000000 {
13		device_type = "memory";
14		reg = <0x10000000 0x80000000>;
15	};
16
17	regulators {
18		compatible = "simple-bus";
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		reg_usb_otg_vbus: regulator@0 {
23			compatible = "regulator-fixed";
24			reg = <0>;
25			regulator-name = "usb_otg_vbus";
26			regulator-min-microvolt = <5000000>;
27			regulator-max-microvolt = <5000000>;
28			gpio = <&gpio4 15 0>;
29			enable-active-high;
30		};
31
32		reg_usb_h1_vbus: regulator@1 {
33			compatible = "regulator-fixed";
34			pinctrl-names = "default";
35			pinctrl-0 = <&pinctrl_usbh1_vbus>;
36			reg = <1>;
37			regulator-name = "usb_h1_vbus";
38			regulator-min-microvolt = <5000000>;
39			regulator-max-microvolt = <5000000>;
40			gpio = <&gpio1 0 0>;
41			enable-active-high;
42		};
43	};
44
45	gpio_leds: leds {
46		pinctrl-names = "default";
47		pinctrl-0 = <&pinctrl_leds>;
48		compatible = "gpio-leds";
49
50		green {
51			label = "phyflex:green";
52			gpios = <&gpio1 30 0>;
53		};
54
55		red {
56			label = "phyflex:red";
57			gpios = <&gpio2 31 0>;
58		};
59	};
60};
61
62&audmux {
63	pinctrl-names = "default";
64	pinctrl-0 = <&pinctrl_audmux>;
65	status = "disabled";
66};
67
68&can1 {
69	pinctrl-names = "default";
70	pinctrl-0 = <&pinctrl_flexcan1>;
71	status = "disabled";
72};
73
74&ecspi3 {
75	pinctrl-names = "default";
76	pinctrl-0 = <&pinctrl_ecspi3>;
77	status = "okay";
78	cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
79
80	som_flash: flash@0 {
81		compatible = "m25p80", "jedec,spi-nor";
82		spi-max-frequency = <20000000>;
83		reg = <0>;
84	};
85};
86
87&fec {
88	pinctrl-names = "default";
89	pinctrl-0 = <&pinctrl_enet>;
90	phy-handle = <&ethphy>;
91	phy-mode = "rgmii";
92	phy-reset-duration = <10>; /* in msecs */
93	phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
94	phy-supply = <&vdd_eth_io_reg>;
95	status = "disabled";
96
97	fec_mdio: mdio {
98		#address-cells = <1>;
99		#size-cells = <0>;
100
101		ethphy: ethernet-phy@0 {
102			compatible = "ethernet-phy-ieee802.3-c22";
103			reg = <0>;
104			txc-skew-ps = <1680>;
105			rxc-skew-ps = <1860>;
106		};
107	};
108};
109
110&gpmi {
111	pinctrl-names = "default";
112	pinctrl-0 = <&pinctrl_gpmi_nand>;
113	nand-on-flash-bbt;
114	status = "okay";
115};
116
117&i2c1 {
118	pinctrl-names = "default";
119	pinctrl-0 = <&pinctrl_i2c1>;
120	status = "okay";
121
122	som_eeprom: eeprom@50 {
123		compatible = "catalyst,24c32", "atmel,24c32";
124		pagesize = <32>;
125		reg = <0x50>;
126	};
127
128	pmic@58 {
129		pinctrl-names = "default";
130		pinctrl-0 = <&pinctrl_pmic>;
131		compatible = "dlg,da9063";
132		reg = <0x58>;
133		interrupt-parent = <&gpio2>;
134		interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
135		interrupt-controller;
136
137		regulators {
138			vddcore_reg: bcore1 {
139				regulator-min-microvolt = <730000>;
140				regulator-max-microvolt = <1380000>;
141				regulator-always-on;
142			};
143
144			vddsoc_reg: bcore2 {
145				regulator-min-microvolt = <730000>;
146				regulator-max-microvolt = <1380000>;
147				regulator-always-on;
148			};
149
150			vdd_ddr3_reg: bpro {
151				regulator-min-microvolt = <1500000>;
152				regulator-max-microvolt = <1500000>;
153				regulator-always-on;
154			};
155
156			vdd_3v3_reg: bperi {
157				regulator-min-microvolt = <3300000>;
158				regulator-max-microvolt = <3300000>;
159				regulator-always-on;
160			};
161
162			vdd_buckmem_reg: bmem {
163				regulator-min-microvolt = <3300000>;
164				regulator-max-microvolt = <3300000>;
165				regulator-always-on;
166			};
167
168			vdd_eth_reg: bio {
169				regulator-min-microvolt = <1200000>;
170				regulator-max-microvolt = <1200000>;
171				regulator-always-on;
172			};
173
174			vdd_eth_io_reg: ldo4 {
175				regulator-min-microvolt = <2500000>;
176				regulator-max-microvolt = <2500000>;
177				regulator-always-on;
178			};
179
180			vdd_mx6_snvs_reg: ldo5 {
181				regulator-min-microvolt = <3000000>;
182				regulator-max-microvolt = <3000000>;
183				regulator-always-on;
184			};
185
186			vdd_3v3_pmic_io_reg: ldo6 {
187				regulator-min-microvolt = <3300000>;
188				regulator-max-microvolt = <3300000>;
189				regulator-always-on;
190			};
191
192			vdd_sd0_reg: ldo9 {
193				regulator-min-microvolt = <3300000>;
194				regulator-max-microvolt = <3300000>;
195			};
196
197			vdd_sd1_reg: ldo10 {
198				regulator-min-microvolt = <3300000>;
199				regulator-max-microvolt = <3300000>;
200			};
201
202			vdd_mx6_high_reg: ldo11 {
203				regulator-min-microvolt = <3000000>;
204				regulator-max-microvolt = <3000000>;
205				regulator-always-on;
206			};
207		};
208	};
209};
210
211&i2c2 {
212	pinctrl-names = "default";
213	pinctrl-0 = <&pinctrl_i2c2>;
214	clock-frequency = <100000>;
215};
216
217&i2c3 {
218	pinctrl-names = "default";
219	pinctrl-0 = <&pinctrl_i2c3>;
220	clock-frequency = <100000>;
221};
222
223&iomuxc {
224	imx6q-phytec-pfla02 {
225		pinctrl_ecspi3: ecspi3grp {
226			fsl,pins = <
227				MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO	0x100b1
228				MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI	0x100b1
229				MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK	0x100b1
230				MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24	0x80000000 /* CS0 */
231			>;
232		};
233
234		pinctrl_enet: enetgrp {
235			fsl,pins = <
236				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
237				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
238				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
239				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
240				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
241				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
242				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
243				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
244				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
245				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
246				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
247				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
248				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
249				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
250				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
251				MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
252				MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x80000000 /* Reset GPIO */
253			>;
254		};
255
256		pinctrl_flexcan1: flexcan1grp {
257			fsl,pins = <
258				MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b0
259				MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b0
260			>;
261		};
262
263		pinctrl_gpmi_nand: gpminandgrp {
264			fsl,pins = <
265				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
266				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
267				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
268				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
269				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
270				MX6QDL_PAD_NANDF_CS1__NAND_CE1_B	0xb0b1
271				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
272				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
273				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
274				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
275				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
276				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
277				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
278				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
279				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
280				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
281				MX6QDL_PAD_SD4_DAT0__NAND_DQS		0x00b1
282			>;
283		};
284
285		pinctrl_i2c1: i2c1grp {
286			fsl,pins = <
287				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
288				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
289			>;
290		};
291
292		pinctrl_i2c2: i2c2grp {
293			fsl,pins = <
294				MX6QDL_PAD_EIM_EB2__I2C2_SCL		0x4001b8b1
295				MX6QDL_PAD_EIM_D16__I2C2_SDA		0x4001b8b1
296			>;
297		};
298
299		pinctrl_i2c3: i2c3grp {
300			fsl,pins = <
301				MX6QDL_PAD_EIM_D17__I2C3_SCL		0x4001b8b1
302				MX6QDL_PAD_EIM_D18__I2C3_SDA		0x4001b8b1
303			>;
304		};
305
306		pinctrl_leds: ledsgrp {
307			fsl,pins = <
308				MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x80000000 /* Green LED */
309				MX6QDL_PAD_EIM_EB3__GPIO2_IO31		0x80000000 /* Red LED */
310			>;
311		};
312
313		pinctrl_pcie: pciegrp {
314			fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000>;
315		};
316
317		pinctrl_pmic: pmicgrp {
318			fsl,pins = <MX6QDL_PAD_SD4_DAT1__GPIO2_IO09	0x80000000>; /* PMIC interrupt */
319		};
320
321		pinctrl_uart3: uart3grp {
322			fsl,pins = <
323				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
324				MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
325				MX6QDL_PAD_EIM_D31__UART3_RTS_B		0x1b0b1
326				MX6QDL_PAD_EIM_D30__UART3_CTS_B		0x1b0b1
327			>;
328		};
329
330		pinctrl_uart4: uart4grp {
331			fsl,pins = <
332				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
333				MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
334			>;
335		};
336
337		pinctrl_usbh1_vbus: usbh1vbusgrp {
338			fsl,pins = <
339				MX6QDL_PAD_GPIO_0__GPIO1_IO00		0x1b0b0
340			>;
341		};
342
343		pinctrl_usbotg: usbotggrp {
344			fsl,pins = <
345				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
346				MX6QDL_PAD_KEY_COL4__USB_OTG_OC		0x1b0b0
347				MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x80000000
348			>;
349		};
350
351		pinctrl_usdhc2: usdhc2grp {
352			fsl,pins = <
353				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
354				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
355				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
356				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
357				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
358				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
359			>;
360		};
361
362		pinctrl_usdhc3: usdhc3grp {
363			fsl,pins = <
364				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
365				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
366				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
367				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
368				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
369				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
370			>;
371		};
372
373		pinctrl_usdhc3_cdwp: usdhc3cdwp {
374			fsl,pins = <
375				MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
376				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
377			>;
378		};
379
380		pinctrl_audmux: audmuxgrp {
381			fsl,pins = <
382				MX6QDL_PAD_DISP0_DAT16__AUD5_TXC	0x130b0
383				MX6QDL_PAD_DISP0_DAT17__AUD5_TXD	0x110b0
384				MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS	0x130b0
385				MX6QDL_PAD_DISP0_DAT19__AUD5_RXD	0x130b0
386			>;
387		};
388	};
389};
390
391&pcie {
392	pinctrl-names = "default";
393	pinctrl-0 = <&pinctrl_pcie>;
394	reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
395	status = "disabled";
396};
397
398&reg_arm {
399	vin-supply = <&vddcore_reg>;
400};
401
402&reg_pu {
403	vin-supply = <&vddsoc_reg>;
404};
405
406&reg_soc {
407	vin-supply = <&vddsoc_reg>;
408};
409
410&uart3 {
411	pinctrl-names = "default";
412	pinctrl-0 = <&pinctrl_uart3>;
413	uart-has-rtscts;
414	status = "disabled";
415};
416
417&uart4 {
418	pinctrl-names = "default";
419	pinctrl-0 = <&pinctrl_uart4>;
420	status = "disabled";
421};
422
423&usbh1 {
424	vbus-supply = <&reg_usb_h1_vbus>;
425	status = "disabled";
426};
427
428&usbotg {
429	vbus-supply = <&reg_usb_otg_vbus>;
430	pinctrl-names = "default";
431	pinctrl-0 = <&pinctrl_usbotg>;
432	disable-over-current;
433	status = "disabled";
434};
435
436&usdhc2 {
437	pinctrl-names = "default";
438	pinctrl-0 = <&pinctrl_usdhc2>;
439	cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
440	wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
441	vmmc-supply = <&vdd_sd1_reg>;
442	status = "disabled";
443};
444
445&usdhc3 {
446	pinctrl-names = "default";
447	pinctrl-0 = <&pinctrl_usdhc3
448		     &pinctrl_usdhc3_cdwp>;
449	cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
450	wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
451	vmmc-supply = <&vdd_sd0_reg>;
452	status = "disabled";
453};
454