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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Device Tree Source for OMAP3 SoC
4 *
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#include <dt-bindings/bus/ti-sysc.h>
9#include <dt-bindings/media/omap3-isp.h>
10
11#include "omap3.dtsi"
12
13/ {
14	aliases {
15		serial3 = &uart4;
16	};
17
18	cpus {
19		/* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */
20		cpu: cpu@0 {
21			operating-points-v2 = <&cpu0_opp_table>;
22
23			vbb-supply = <&abb_mpu_iva>;
24			clock-latency = <300000>; /* From omap-cpufreq driver */
25			#cooling-cells = <2>;
26		};
27	};
28
29	cpu0_opp_table: opp-table {
30		compatible = "operating-points-v2-ti-cpu";
31		syscon = <&scm_conf>;
32
33		opp50-300000000 {
34			opp-hz = /bits/ 64 <300000000>;
35			/*
36			 * we currently only select the max voltage from table
37			 * Table 4-19 of the DM3730 Data sheet (SPRS685B)
38			 * Format is:	cpu0-supply:	<target min max>
39			 *		vbb-supply:	<target min max>
40			 */
41			opp-microvolt = <1012500 1012500 1012500>,
42					 <1012500 1012500 1012500>;
43			/*
44			 * first value is silicon revision bit mask
45			 * second one is "speed binned" bit mask
46			 */
47			opp-supported-hw = <0xffffffff 3>;
48			opp-suspend;
49		};
50
51		opp100-600000000 {
52			opp-hz = /bits/ 64 <600000000>;
53			opp-microvolt = <1200000 1200000 1200000>,
54					 <1200000 1200000 1200000>;
55			opp-supported-hw = <0xffffffff 3>;
56		};
57
58		opp130-800000000 {
59			opp-hz = /bits/ 64 <800000000>;
60			opp-microvolt = <1325000 1325000 1325000>,
61					 <1325000 1325000 1325000>;
62			opp-supported-hw = <0xffffffff 3>;
63		};
64
65		opp1g-1000000000 {
66			opp-hz = /bits/ 64 <1000000000>;
67			opp-microvolt = <1375000 1375000 1375000>,
68					 <1375000 1375000 1375000>;
69			/* only on am/dm37x with speed-binned bit set */
70			opp-supported-hw = <0xffffffff 2>;
71		};
72	};
73
74	opp_supply_mpu_iva: opp_supply {
75		compatible = "ti,omap-opp-supply";
76		ti,absolute-max-voltage-uv = <1375000>;
77	};
78
79	ocp@68000000 {
80		uart4: serial@49042000 {
81			compatible = "ti,omap3-uart";
82			reg = <0x49042000 0x400>;
83			interrupts = <80>;
84			dmas = <&sdma 81 &sdma 82>;
85			dma-names = "tx", "rx";
86			ti,hwmods = "uart4";
87			clock-frequency = <48000000>;
88		};
89
90		abb_mpu_iva: regulator-abb-mpu {
91			compatible = "ti,abb-v1";
92			regulator-name = "abb_mpu_iva";
93			#address-cells = <0>;
94			#size-cells = <0>;
95			reg = <0x483072f0 0x8>, <0x48306818 0x4>;
96			reg-names = "base-address", "int-address";
97			ti,tranxdone-status-mask = <0x4000000>;
98			clocks = <&sys_ck>;
99			ti,settling-time = <30>;
100			ti,clock-cycles = <8>;
101			ti,abb_info = <
102			/*uV		ABB	efuse	rbb_m	fbb_m	vset_m*/
103			1012500		0	0	0	0	0
104			1200000		0	0	0	0	0
105			1325000		0	0	0	0	0
106			1375000		1	0	0	0	0
107			>;
108		};
109
110		omap3_pmx_core2: pinmux@480025a0 {
111			compatible = "ti,omap3-padconf", "pinctrl-single";
112			reg = <0x480025a0 0x5c>;
113			#address-cells = <1>;
114			#size-cells = <0>;
115			#pinctrl-cells = <1>;
116			#interrupt-cells = <1>;
117			interrupt-controller;
118			pinctrl-single,register-width = <16>;
119			pinctrl-single,function-mask = <0xff1f>;
120		};
121
122		isp: isp@480bc000 {
123			compatible = "ti,omap3-isp";
124			reg = <0x480bc000 0x12fc
125			       0x480bd800 0x0600>;
126			interrupts = <24>;
127			iommus = <&mmu_isp>;
128			syscon = <&scm_conf 0x2f0>;
129			ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
130			#clock-cells = <1>;
131			ports {
132				#address-cells = <1>;
133				#size-cells = <0>;
134			};
135		};
136
137		bandgap: bandgap@48002524 {
138			reg = <0x48002524 0x4>;
139			compatible = "ti,omap36xx-bandgap";
140			#thermal-sensor-cells = <0>;
141		};
142
143		target-module@480cb000 {
144			compatible = "ti,sysc-omap3630-sr", "ti,sysc";
145			ti,hwmods = "smartreflex_core";
146			reg = <0x480cb038 0x4>;
147			reg-names = "sysc";
148			ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
149			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
150					<SYSC_IDLE_NO>,
151					<SYSC_IDLE_SMART>;
152			clocks = <&sr2_fck>;
153			clock-names = "fck";
154			#address-cells = <1>;
155			#size-cells = <1>;
156			ranges = <0 0x480cb000 0x001000>;
157
158			smartreflex_core: smartreflex@0 {
159				compatible = "ti,omap3-smartreflex-core";
160				reg = <0 0x400>;
161				interrupts = <19>;
162			};
163		};
164
165		target-module@480c9000 {
166			compatible = "ti,sysc-omap3630-sr", "ti,sysc";
167			ti,hwmods = "smartreflex_mpu_iva";
168			reg = <0x480c9038 0x4>;
169			reg-names = "sysc";
170			ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
171			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
172					<SYSC_IDLE_NO>,
173					<SYSC_IDLE_SMART>;
174			clocks = <&sr1_fck>;
175			clock-names = "fck";
176			#address-cells = <1>;
177			#size-cells = <1>;
178			ranges = <0 0x480c9000 0x001000>;
179
180
181			smartreflex_mpu_iva: smartreflex@480c9000 {
182				compatible = "ti,omap3-smartreflex-mpu-iva";
183				reg = <0 0x400>;
184				interrupts = <18>;
185			};
186		};
187
188		/*
189		 * Note that the sysconfig register layout is a subset of the
190		 * "ti,sysc-omap4" type register with just sidle and midle bits
191		 * available while omap34xx has "ti,sysc-omap2" type sysconfig.
192		 */
193		sgx_module: target-module@50000000 {
194			compatible = "ti,sysc-omap4", "ti,sysc";
195			reg = <0x5000fe00 0x4>,
196			      <0x5000fe10 0x4>;
197			reg-names = "rev", "sysc";
198			ti,sysc-midle = <SYSC_IDLE_FORCE>,
199					<SYSC_IDLE_NO>,
200					<SYSC_IDLE_SMART>;
201			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
202					<SYSC_IDLE_NO>,
203					<SYSC_IDLE_SMART>;
204			clocks = <&sgx_fck>, <&sgx_ick>;
205			clock-names = "fck", "ick";
206			#address-cells = <1>;
207			#size-cells = <1>;
208			ranges = <0 0x50000000 0x2000000>;
209
210			/*
211			 * Closed source PowerVR driver, no child device
212			 * binding or driver in mainline
213			 */
214		};
215	};
216
217	thermal_zones: thermal-zones {
218		#include "omap3-cpu-thermal.dtsi"
219	};
220};
221
222&sdma {
223	compatible = "ti,omap3630-sdma", "ti,omap-sdma";
224};
225
226/* OMAP3630 needs dss_96m_fck for VENC */
227&venc {
228	clocks = <&dss_tv_fck>, <&dss_96m_fck>;
229	clock-names = "fck", "tv_dac_clk";
230};
231
232&ssi {
233	status = "okay";
234
235	clocks = <&ssi_ssr_fck>,
236		 <&ssi_sst_fck>,
237		 <&ssi_ick>;
238	clock-names = "ssi_ssr_fck",
239		      "ssi_sst_fck",
240		      "ssi_ick";
241};
242
243/include/ "omap34xx-omap36xx-clocks.dtsi"
244/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
245/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
246/include/ "omap36xx-clocks.dtsi"
247