1/* 2 * Copyright (C) 2016 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13#include <linux/serial_reg.h> 14#include <asm/cputype.h> 15 16/* Physical register offset and virtual register offset */ 17#define REG_PHYS_BASE 0xf0000000 18#define REG_PHYS_BASE_V7 0x08000000 19#define REG_VIRT_BASE 0xfc000000 20#define REG_PHYS_ADDR(x) ((x) + REG_PHYS_BASE) 21#define REG_PHYS_ADDR_V7(x) ((x) + REG_PHYS_BASE_V7) 22 23/* Product id can be read from here */ 24#define SUN_TOP_CTRL_BASE REG_PHYS_ADDR(0x404000) 25#define SUN_TOP_CTRL_BASE_V7 REG_PHYS_ADDR_V7(0x404000) 26 27#define UARTA_3390 REG_PHYS_ADDR(0x40a900) 28#define UARTA_72116 UARTA_7255 29#define UARTA_7250 REG_PHYS_ADDR(0x40b400) 30#define UARTA_7255 REG_PHYS_ADDR(0x40c000) 31#define UARTA_7260 UARTA_7255 32#define UARTA_7268 UARTA_7255 33#define UARTA_7271 UARTA_7268 34#define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000) 35#define UARTA_7216 UARTA_7278 36#define UARTA_72164 UARTA_7278 37#define UARTA_72165 UARTA_7278 38#define UARTA_7364 REG_PHYS_ADDR(0x40b000) 39#define UARTA_7366 UARTA_7364 40#define UARTA_74371 REG_PHYS_ADDR(0x406b00) 41#define UARTA_7439 REG_PHYS_ADDR(0x40a900) 42#define UARTA_7445 REG_PHYS_ADDR(0x40ab00) 43 44#define UART_SHIFT 2 45 46#define checkuart(rp, rv, family_id, family) \ 47 /* Load family id */ \ 48 ldr rp, =family_id ; \ 49 /* Compare SUN_TOP_CTRL value against it */ \ 50 cmp rp, rv ; \ 51 /* Passed test, load address */ \ 52 ldreq rp, =UARTA_##family ; \ 53 /* Jump to save UART address */ \ 54 beq 91f 55 56 .macro addruart, rp, rv, tmp 57 adr \rp, 99f @ actual addr of 99f 58 ldr \rv, [\rp] @ linked addr is stored there 59 sub \rv, \rv, \rp @ offset between the two 60 ldr \rp, [\rp, #4] @ linked brcmstb_uart_config 61 sub \tmp, \rp, \rv @ actual brcmstb_uart_config 62 ldr \rp, [\tmp] @ Load brcmstb_uart_config 63 cmp \rp, #1 @ needs initialization? 64 bne 100f @ no; go load the addresses 65 mov \rv, #0 @ yes; record init is done 66 str \rv, [\tmp] 67 68 /* Check for V7 memory map if B53 */ 69 mrc p15, 0, \rv, c0, c0, 0 @ get Main ID register 70 ldr \rp, =ARM_CPU_PART_MASK 71 and \rv, \rv, \rp 72 ldr \rp, =ARM_CPU_PART_BRAHMA_B53 @ check for B53 CPU 73 cmp \rv, \rp 74 bne 10f 75 76 /* if PERIPHBASE doesn't overlap REG_PHYS_BASE use V7 map */ 77 mrc p15, 1, \rv, c15, c3, 0 @ get PERIPHBASE from CBAR 78 ands \rv, \rv, #REG_PHYS_BASE 79 ldreq \rp, =SUN_TOP_CTRL_BASE_V7 80 81 /* Check SUN_TOP_CTRL base */ 8210: ldrne \rp, =SUN_TOP_CTRL_BASE @ load SUN_TOP_CTRL PA 83 ldr \rv, [\rp, #0] @ get register contents 84ARM_BE8( rev \rv, \rv ) 85 and \rv, \rv, #0xffffff00 @ strip revision bits [7:0] 86 87 /* Chip specific detection starts here */ 8820: checkuart(\rp, \rv, 0x33900000, 3390) 8921: checkuart(\rp, \rv, 0x07211600, 72116) 9022: checkuart(\rp, \rv, 0x72160000, 7216) 9123: checkuart(\rp, \rv, 0x07216400, 72164) 9224: checkuart(\rp, \rv, 0x07216500, 72165) 9325: checkuart(\rp, \rv, 0x72500000, 7250) 9426: checkuart(\rp, \rv, 0x72550000, 7255) 9527: checkuart(\rp, \rv, 0x72600000, 7260) 9628: checkuart(\rp, \rv, 0x72680000, 7268) 9729: checkuart(\rp, \rv, 0x72710000, 7271) 9830: checkuart(\rp, \rv, 0x72780000, 7278) 9931: checkuart(\rp, \rv, 0x73640000, 7364) 10032: checkuart(\rp, \rv, 0x73660000, 7366) 10133: checkuart(\rp, \rv, 0x07437100, 74371) 10234: checkuart(\rp, \rv, 0x74390000, 7439) 10335: checkuart(\rp, \rv, 0x74450000, 7445) 104 105 /* No valid UART found */ 10690: mov \rp, #0 107 /* fall through */ 108 109 /* Record whichever UART we chose */ 11091: str \rp, [\tmp, #4] @ Store in brcmstb_uart_phys 111 cmp \rp, #0 @ Valid UART address? 112 bne 92f @ Yes, go process it 113 str \rp, [\tmp, #8] @ Store 0 in brcmstb_uart_virt 114 b 100f @ Done 11592: and \rv, \rp, #0xffffff @ offset within 16MB section 116 add \rv, \rv, #REG_VIRT_BASE 117 str \rv, [\tmp, #8] @ Store in brcmstb_uart_virt 118 b 100f 119 120 .align 12199: .word . 122 .word brcmstb_uart_config 123 .ltorg 124 125 /* Load previously selected UART address */ 126100: ldr \rp, [\tmp, #4] @ Load brcmstb_uart_phys 127 ldr \rv, [\tmp, #8] @ Load brcmstb_uart_virt 128 .endm 129 130 .macro store, rd, rx:vararg 131ARM_BE8( rev \rd, \rd ) 132 str \rd, \rx 133 .endm 134 135 .macro load, rd, rx:vararg 136 ldr \rd, \rx 137ARM_BE8( rev \rd, \rd ) 138 .endm 139 140 .macro senduart,rd,rx 141 store \rd, [\rx, #UART_TX << UART_SHIFT] 142 .endm 143 144 .macro busyuart,rd,rx 1451002: load \rd, [\rx, #UART_LSR << UART_SHIFT] 146 and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE 147 teq \rd, #UART_LSR_TEMT | UART_LSR_THRE 148 bne 1002b 149 .endm 150 151 .macro waituarttxrdy,rd,rx 152 .endm 153 154 .macro waituartcts,rd,rx 155 .endm 156 157/* 158 * Storage for the state maintained by the macros above. 159 * 160 * In the kernel proper, this data is located in arch/arm/mach-bcm/brcmstb.c. 161 * That's because this header is included from multiple files, and we only 162 * want a single copy of the data. In particular, the UART probing code above 163 * assumes it's running using physical addresses. This is true when this file 164 * is included from head.o, but not when included from debug.o. So we need 165 * to share the probe results between the two copies, rather than having 166 * to re-run the probing again later. 167 * 168 * In the decompressor, we put the symbol/storage right here, since common.c 169 * isn't included in the decompressor build. This symbol gets put in .text 170 * even though it's really data, since .data is discarded from the 171 * decompressor. Luckily, .text is writeable in the decompressor, unless 172 * CONFIG_ZBOOT_ROM. That dependency is handled in arch/arm/Kconfig.debug. 173 */ 174#if defined(ZIMAGE) 175brcmstb_uart_config: 176 /* Debug UART initialization required */ 177 .word 1 178 /* Debug UART physical address */ 179 .word 0 180 /* Debug UART virtual address */ 181 .word 0 182#endif 183