1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * arch/arm/mach-at91/pm.c
4 * AT91 Power Management
5 *
6 * Copyright (C) 2005 David Brownell
7 */
8
9 #include <linux/genalloc.h>
10 #include <linux/io.h>
11 #include <linux/of_address.h>
12 #include <linux/of.h>
13 #include <linux/of_fdt.h>
14 #include <linux/of_platform.h>
15 #include <linux/parser.h>
16 #include <linux/suspend.h>
17
18 #include <linux/clk/at91_pmc.h>
19 #include <linux/platform_data/atmel.h>
20
21 #include <soc/at91/pm.h>
22
23 #include <asm/cacheflush.h>
24 #include <asm/fncpy.h>
25 #include <asm/system_misc.h>
26 #include <asm/suspend.h>
27
28 #include "generic.h"
29 #include "pm.h"
30
31 #define BACKUP_DDR_PHY_CALIBRATION (9)
32
33 /**
34 * struct at91_pm_bu - AT91 power management backup unit data structure
35 * @suspended: true if suspended to backup mode
36 * @reserved: reserved
37 * @canary: canary data for memory checking after exit from backup mode
38 * @resume: resume API
39 * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words
40 * of the memory
41 */
42 struct at91_pm_bu {
43 int suspended;
44 unsigned long reserved;
45 phys_addr_t canary;
46 phys_addr_t resume;
47 unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION];
48 };
49
50 /*
51 * struct at91_pm_sfrbu_offsets: registers mapping for SFRBU
52 * @pswbu: power switch BU control registers
53 */
54 struct at91_pm_sfrbu_regs {
55 struct {
56 u32 key;
57 u32 ctrl;
58 u32 state;
59 u32 softsw;
60 } pswbu;
61 };
62
63 /**
64 * struct at91_soc_pm - AT91 SoC power management data structure
65 * @config_shdwc_ws: wakeup sources configuration function for SHDWC
66 * @config_pmc_ws: wakeup srouces configuration function for PMC
67 * @ws_ids: wakup sources of_device_id array
68 * @data: PM data to be used on last phase of suspend
69 * @sfrbu_regs: SFRBU registers mapping
70 * @bu: backup unit mapped data (for backup mode)
71 * @memcs: memory chip select
72 */
73 struct at91_soc_pm {
74 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
75 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
76 const struct of_device_id *ws_ids;
77 struct at91_pm_bu *bu;
78 struct at91_pm_data data;
79 struct at91_pm_sfrbu_regs sfrbu_regs;
80 void *memcs;
81 };
82
83 /**
84 * enum at91_pm_iomaps: IOs that needs to be mapped for different PM modes
85 * @AT91_PM_IOMAP_SHDWC: SHDWC controller
86 * @AT91_PM_IOMAP_SFRBU: SFRBU controller
87 */
88 enum at91_pm_iomaps {
89 AT91_PM_IOMAP_SHDWC,
90 AT91_PM_IOMAP_SFRBU,
91 };
92
93 #define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name)
94
95 static struct at91_soc_pm soc_pm = {
96 .data = {
97 .standby_mode = AT91_PM_STANDBY,
98 .suspend_mode = AT91_PM_ULP0,
99 },
100 };
101
102 static const match_table_t pm_modes __initconst = {
103 { AT91_PM_STANDBY, "standby" },
104 { AT91_PM_ULP0, "ulp0" },
105 { AT91_PM_ULP0_FAST, "ulp0-fast" },
106 { AT91_PM_ULP1, "ulp1" },
107 { AT91_PM_BACKUP, "backup" },
108 { -1, NULL },
109 };
110
111 #define at91_ramc_read(id, field) \
112 __raw_readl(soc_pm.data.ramc[id] + field)
113
114 #define at91_ramc_write(id, field, value) \
115 __raw_writel(value, soc_pm.data.ramc[id] + field)
116
at91_pm_valid_state(suspend_state_t state)117 static int at91_pm_valid_state(suspend_state_t state)
118 {
119 switch (state) {
120 case PM_SUSPEND_ON:
121 case PM_SUSPEND_STANDBY:
122 case PM_SUSPEND_MEM:
123 return 1;
124
125 default:
126 return 0;
127 }
128 }
129
130 static int canary = 0xA5A5A5A5;
131
132 struct wakeup_source_info {
133 unsigned int pmc_fsmr_bit;
134 unsigned int shdwc_mr_bit;
135 bool set_polarity;
136 };
137
138 static const struct wakeup_source_info ws_info[] = {
139 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
140 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
141 { .pmc_fsmr_bit = AT91_PMC_USBAL },
142 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
143 { .pmc_fsmr_bit = AT91_PMC_RTTAL },
144 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
145 };
146
147 static const struct of_device_id sama5d2_ws_ids[] = {
148 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
149 { .compatible = "atmel,sama5d2-rtc", .data = &ws_info[1] },
150 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
151 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
152 { .compatible = "usb-ohci", .data = &ws_info[2] },
153 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
154 { .compatible = "usb-ehci", .data = &ws_info[2] },
155 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
156 { /* sentinel */ }
157 };
158
159 static const struct of_device_id sam9x60_ws_ids[] = {
160 { .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] },
161 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
162 { .compatible = "usb-ohci", .data = &ws_info[2] },
163 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
164 { .compatible = "usb-ehci", .data = &ws_info[2] },
165 { .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] },
166 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
167 { /* sentinel */ }
168 };
169
170 static const struct of_device_id sama7g5_ws_ids[] = {
171 { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] },
172 { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] },
173 { .compatible = "usb-ohci", .data = &ws_info[2] },
174 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
175 { .compatible = "usb-ehci", .data = &ws_info[2] },
176 { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] },
177 { .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] },
178 { /* sentinel */ }
179 };
180
at91_pm_config_ws(unsigned int pm_mode,bool set)181 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
182 {
183 const struct wakeup_source_info *wsi;
184 const struct of_device_id *match;
185 struct platform_device *pdev;
186 struct device_node *np;
187 unsigned int mode = 0, polarity = 0, val = 0;
188
189 if (pm_mode != AT91_PM_ULP1)
190 return 0;
191
192 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
193 return -EPERM;
194
195 if (!set) {
196 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
197 return 0;
198 }
199
200 if (soc_pm.config_shdwc_ws)
201 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
202
203 /* SHDWC.MR */
204 val = readl(soc_pm.data.shdwc + 0x04);
205
206 /* Loop through defined wakeup sources. */
207 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
208 pdev = of_find_device_by_node(np);
209 if (!pdev)
210 continue;
211
212 if (device_may_wakeup(&pdev->dev)) {
213 wsi = match->data;
214
215 /* Check if enabled on SHDWC. */
216 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
217 goto put_device;
218
219 mode |= wsi->pmc_fsmr_bit;
220 if (wsi->set_polarity)
221 polarity |= wsi->pmc_fsmr_bit;
222 }
223
224 put_device:
225 put_device(&pdev->dev);
226 }
227
228 if (mode) {
229 if (soc_pm.config_pmc_ws)
230 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
231 } else {
232 pr_err("AT91: PM: no ULP1 wakeup sources found!");
233 }
234
235 return mode ? 0 : -EPERM;
236 }
237
at91_sama5d2_config_shdwc_ws(void __iomem * shdwc,u32 * mode,u32 * polarity)238 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
239 u32 *polarity)
240 {
241 u32 val;
242
243 /* SHDWC.WUIR */
244 val = readl(shdwc + 0x0c);
245 *mode |= (val & 0x3ff);
246 *polarity |= ((val >> 16) & 0x3ff);
247
248 return 0;
249 }
250
at91_sama5d2_config_pmc_ws(void __iomem * pmc,u32 mode,u32 polarity)251 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
252 {
253 writel(mode, pmc + AT91_PMC_FSMR);
254 writel(polarity, pmc + AT91_PMC_FSPR);
255
256 return 0;
257 }
258
at91_sam9x60_config_pmc_ws(void __iomem * pmc,u32 mode,u32 polarity)259 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
260 {
261 writel(mode, pmc + AT91_PMC_FSMR);
262
263 return 0;
264 }
265
266 /*
267 * Called after processes are frozen, but before we shutdown devices.
268 */
at91_pm_begin(suspend_state_t state)269 static int at91_pm_begin(suspend_state_t state)
270 {
271 int ret;
272
273 switch (state) {
274 case PM_SUSPEND_MEM:
275 soc_pm.data.mode = soc_pm.data.suspend_mode;
276 break;
277
278 case PM_SUSPEND_STANDBY:
279 soc_pm.data.mode = soc_pm.data.standby_mode;
280 break;
281
282 default:
283 soc_pm.data.mode = -1;
284 }
285
286 ret = at91_pm_config_ws(soc_pm.data.mode, true);
287 if (ret)
288 return ret;
289
290 if (soc_pm.data.mode == AT91_PM_BACKUP)
291 soc_pm.bu->suspended = 1;
292 else if (soc_pm.bu)
293 soc_pm.bu->suspended = 0;
294
295 return 0;
296 }
297
298 /*
299 * Verify that all the clocks are correct before entering
300 * slow-clock mode.
301 */
at91_pm_verify_clocks(void)302 static int at91_pm_verify_clocks(void)
303 {
304 unsigned long scsr;
305 int i;
306
307 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
308
309 /* USB must not be using PLLB */
310 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
311 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
312 return 0;
313 }
314
315 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
316 for (i = 0; i < 4; i++) {
317 u32 css;
318
319 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
320 continue;
321 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
322 if (css != AT91_PMC_CSS_SLOW) {
323 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
324 return 0;
325 }
326 }
327
328 return 1;
329 }
330
331 /*
332 * Call this from platform driver suspend() to see how deeply to suspend.
333 * For example, some controllers (like OHCI) need one of the PLL clocks
334 * in order to act as a wakeup source, and those are not available when
335 * going into slow clock mode.
336 *
337 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
338 * the very same problem (but not using at91 main_clk), and it'd be better
339 * to add one generic API rather than lots of platform-specific ones.
340 */
at91_suspend_entering_slow_clock(void)341 int at91_suspend_entering_slow_clock(void)
342 {
343 return (soc_pm.data.mode >= AT91_PM_ULP0);
344 }
345 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
346
347 static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
348 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
349 extern u32 at91_pm_suspend_in_sram_sz;
350
at91_suspend_finish(unsigned long val)351 static int at91_suspend_finish(unsigned long val)
352 {
353 unsigned char modified_gray_code[] = {
354 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d,
355 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b,
356 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13,
357 0x10, 0x11,
358 };
359 unsigned int tmp, index;
360 int i;
361
362 if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {
363 /*
364 * Bootloader will perform DDR recalibration and will try to
365 * restore the ZQ0SR0 with the value saved here. But the
366 * calibration is buggy and restoring some values from ZQ0SR0
367 * is forbidden and risky thus we need to provide processed
368 * values for these (modified gray code values).
369 */
370 tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0);
371
372 /* Store pull-down output impedance select. */
373 index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f;
374 soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index];
375
376 /* Store pull-up output impedance select. */
377 index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f;
378 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
379
380 /* Store pull-down on-die termination impedance select. */
381 index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f;
382 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
383
384 /* Store pull-up on-die termination impedance select. */
385 index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f;
386 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
387
388 /*
389 * The 1st 8 words of memory might get corrupted in the process
390 * of DDR PHY recalibration; it is saved here in securam and it
391 * will be restored later, after recalibration, by bootloader
392 */
393 for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++)
394 soc_pm.bu->ddr_phy_calibration[i] =
395 *((unsigned int *)soc_pm.memcs + (i - 1));
396 }
397
398 flush_cache_all();
399 outer_disable();
400
401 at91_suspend_sram_fn(&soc_pm.data);
402
403 return 0;
404 }
405
at91_pm_switch_ba_to_vbat(void)406 static void at91_pm_switch_ba_to_vbat(void)
407 {
408 unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu);
409 unsigned int val;
410
411 /* Just for safety. */
412 if (!soc_pm.data.sfrbu)
413 return;
414
415 val = readl(soc_pm.data.sfrbu + offset);
416
417 /* Already on VBAT. */
418 if (!(val & soc_pm.sfrbu_regs.pswbu.state))
419 return;
420
421 val &= ~soc_pm.sfrbu_regs.pswbu.softsw;
422 val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl;
423 writel(val, soc_pm.data.sfrbu + offset);
424
425 /* Wait for update. */
426 val = readl(soc_pm.data.sfrbu + offset);
427 while (val & soc_pm.sfrbu_regs.pswbu.state)
428 val = readl(soc_pm.data.sfrbu + offset);
429 }
430
at91_pm_suspend(suspend_state_t state)431 static void at91_pm_suspend(suspend_state_t state)
432 {
433 if (soc_pm.data.mode == AT91_PM_BACKUP) {
434 at91_pm_switch_ba_to_vbat();
435
436 cpu_suspend(0, at91_suspend_finish);
437
438 /* The SRAM is lost between suspend cycles */
439 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
440 &at91_pm_suspend_in_sram,
441 at91_pm_suspend_in_sram_sz);
442 } else {
443 at91_suspend_finish(0);
444 }
445
446 outer_resume();
447 }
448
449 /*
450 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
451 * event sources; and reduces DRAM power. But otherwise it's identical to
452 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
453 *
454 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
455 * suspend more deeply, the master clock switches to the clk32k and turns off
456 * the main oscillator
457 *
458 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
459 */
at91_pm_enter(suspend_state_t state)460 static int at91_pm_enter(suspend_state_t state)
461 {
462 #ifdef CONFIG_PINCTRL_AT91
463 /*
464 * FIXME: this is needed to communicate between the pinctrl driver and
465 * the PM implementation in the machine. Possibly part of the PM
466 * implementation should be moved down into the pinctrl driver and get
467 * called as part of the generic suspend/resume path.
468 */
469 at91_pinctrl_gpio_suspend();
470 #endif
471
472 switch (state) {
473 case PM_SUSPEND_MEM:
474 case PM_SUSPEND_STANDBY:
475 /*
476 * Ensure that clocks are in a valid state.
477 */
478 if (soc_pm.data.mode >= AT91_PM_ULP0 &&
479 !at91_pm_verify_clocks())
480 goto error;
481
482 at91_pm_suspend(state);
483
484 break;
485
486 case PM_SUSPEND_ON:
487 cpu_do_idle();
488 break;
489
490 default:
491 pr_debug("AT91: PM - bogus suspend state %d\n", state);
492 goto error;
493 }
494
495 error:
496 #ifdef CONFIG_PINCTRL_AT91
497 at91_pinctrl_gpio_resume();
498 #endif
499 return 0;
500 }
501
502 /*
503 * Called right prior to thawing processes.
504 */
at91_pm_end(void)505 static void at91_pm_end(void)
506 {
507 at91_pm_config_ws(soc_pm.data.mode, false);
508 }
509
510
511 static const struct platform_suspend_ops at91_pm_ops = {
512 .valid = at91_pm_valid_state,
513 .begin = at91_pm_begin,
514 .enter = at91_pm_enter,
515 .end = at91_pm_end,
516 };
517
518 static struct platform_device at91_cpuidle_device = {
519 .name = "cpuidle-at91",
520 };
521
522 /*
523 * The AT91RM9200 goes into self-refresh mode with this command, and will
524 * terminate self-refresh automatically on the next SDRAM access.
525 *
526 * Self-refresh mode is exited as soon as a memory access is made, but we don't
527 * know for sure when that happens. However, we need to restore the low-power
528 * mode if it was enabled before going idle. Restoring low-power mode while
529 * still in self-refresh is "not recommended", but seems to work.
530 */
at91rm9200_standby(void)531 static void at91rm9200_standby(void)
532 {
533 asm volatile(
534 "b 1f\n\t"
535 ".align 5\n\t"
536 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
537 " str %2, [%1, %3]\n\t"
538 " mcr p15, 0, %0, c7, c0, 4\n\t"
539 :
540 : "r" (0), "r" (soc_pm.data.ramc[0]),
541 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
542 }
543
544 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
545 * remember.
546 */
at91_ddr_standby(void)547 static void at91_ddr_standby(void)
548 {
549 /* Those two values allow us to delay self-refresh activation
550 * to the maximum. */
551 u32 lpr0, lpr1 = 0;
552 u32 mdr, saved_mdr0, saved_mdr1 = 0;
553 u32 saved_lpr0, saved_lpr1 = 0;
554
555 /* LPDDR1 --> force DDR2 mode during self-refresh */
556 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
557 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
558 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
559 mdr |= AT91_DDRSDRC_MD_DDR2;
560 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
561 }
562
563 if (soc_pm.data.ramc[1]) {
564 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
565 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
566 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
567 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
568 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
569 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
570 mdr |= AT91_DDRSDRC_MD_DDR2;
571 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
572 }
573 }
574
575 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
576 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
577 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
578
579 /* self-refresh mode now */
580 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
581 if (soc_pm.data.ramc[1])
582 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
583
584 cpu_do_idle();
585
586 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
587 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
588 if (soc_pm.data.ramc[1]) {
589 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
590 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
591 }
592 }
593
sama5d3_ddr_standby(void)594 static void sama5d3_ddr_standby(void)
595 {
596 u32 lpr0;
597 u32 saved_lpr0;
598
599 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
600 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
601 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
602
603 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
604
605 cpu_do_idle();
606
607 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
608 }
609
610 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
611 * remember.
612 */
at91sam9_sdram_standby(void)613 static void at91sam9_sdram_standby(void)
614 {
615 u32 lpr0, lpr1 = 0;
616 u32 saved_lpr0, saved_lpr1 = 0;
617
618 if (soc_pm.data.ramc[1]) {
619 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
620 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
621 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
622 }
623
624 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
625 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
626 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
627
628 /* self-refresh mode now */
629 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
630 if (soc_pm.data.ramc[1])
631 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
632
633 cpu_do_idle();
634
635 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
636 if (soc_pm.data.ramc[1])
637 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
638 }
639
640 struct ramc_info {
641 void (*idle)(void);
642 unsigned int memctrl;
643 };
644
645 static const struct ramc_info ramc_infos[] __initconst = {
646 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
647 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
648 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
649 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
650 };
651
652 static const struct of_device_id ramc_ids[] __initconst = {
653 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
654 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
655 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
656 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
657 { .compatible = "microchip,sama7g5-uddrc", },
658 { /*sentinel*/ }
659 };
660
661 static const struct of_device_id ramc_phy_ids[] __initconst = {
662 { .compatible = "microchip,sama7g5-ddr3phy", },
663 { /* Sentinel. */ },
664 };
665
at91_dt_ramc(bool phy_mandatory)666 static __init int at91_dt_ramc(bool phy_mandatory)
667 {
668 struct device_node *np;
669 const struct of_device_id *of_id;
670 int idx = 0;
671 void *standby = NULL;
672 const struct ramc_info *ramc;
673 int ret;
674
675 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
676 soc_pm.data.ramc[idx] = of_iomap(np, 0);
677 if (!soc_pm.data.ramc[idx]) {
678 pr_err("unable to map ramc[%d] cpu registers\n", idx);
679 ret = -ENOMEM;
680 goto unmap_ramc;
681 }
682
683 ramc = of_id->data;
684 if (ramc) {
685 if (!standby)
686 standby = ramc->idle;
687 soc_pm.data.memctrl = ramc->memctrl;
688 }
689
690 idx++;
691 }
692
693 if (!idx) {
694 pr_err("unable to find compatible ram controller node in dtb\n");
695 ret = -ENODEV;
696 goto unmap_ramc;
697 }
698
699 /* Lookup for DDR PHY node, if any. */
700 for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) {
701 soc_pm.data.ramc_phy = of_iomap(np, 0);
702 if (!soc_pm.data.ramc_phy) {
703 pr_err("unable to map ramc phy cpu registers\n");
704 ret = -ENOMEM;
705 goto unmap_ramc;
706 }
707 }
708
709 if (phy_mandatory && !soc_pm.data.ramc_phy) {
710 pr_err("DDR PHY is mandatory!\n");
711 ret = -ENODEV;
712 goto unmap_ramc;
713 }
714
715 if (!standby) {
716 pr_warn("ramc no standby function available\n");
717 return 0;
718 }
719
720 at91_cpuidle_device.dev.platform_data = standby;
721
722 return 0;
723
724 unmap_ramc:
725 while (idx)
726 iounmap(soc_pm.data.ramc[--idx]);
727
728 return ret;
729 }
730
at91rm9200_idle(void)731 static void at91rm9200_idle(void)
732 {
733 /*
734 * Disable the processor clock. The processor will be automatically
735 * re-enabled by an interrupt or by a reset.
736 */
737 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
738 }
739
at91sam9_idle(void)740 static void at91sam9_idle(void)
741 {
742 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
743 cpu_do_idle();
744 }
745
at91_pm_sram_init(void)746 static void __init at91_pm_sram_init(void)
747 {
748 struct gen_pool *sram_pool;
749 phys_addr_t sram_pbase;
750 unsigned long sram_base;
751 struct device_node *node;
752 struct platform_device *pdev = NULL;
753
754 for_each_compatible_node(node, NULL, "mmio-sram") {
755 pdev = of_find_device_by_node(node);
756 if (pdev) {
757 of_node_put(node);
758 break;
759 }
760 }
761
762 if (!pdev) {
763 pr_warn("%s: failed to find sram device!\n", __func__);
764 return;
765 }
766
767 sram_pool = gen_pool_get(&pdev->dev, NULL);
768 if (!sram_pool) {
769 pr_warn("%s: sram pool unavailable!\n", __func__);
770 goto out_put_device;
771 }
772
773 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
774 if (!sram_base) {
775 pr_warn("%s: unable to alloc sram!\n", __func__);
776 goto out_put_device;
777 }
778
779 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
780 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
781 at91_pm_suspend_in_sram_sz, false);
782 if (!at91_suspend_sram_fn) {
783 pr_warn("SRAM: Could not map\n");
784 goto out_put_device;
785 }
786
787 /* Copy the pm suspend handler to SRAM */
788 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
789 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
790 return;
791
792 out_put_device:
793 put_device(&pdev->dev);
794 return;
795 }
796
at91_is_pm_mode_active(int pm_mode)797 static bool __init at91_is_pm_mode_active(int pm_mode)
798 {
799 return (soc_pm.data.standby_mode == pm_mode ||
800 soc_pm.data.suspend_mode == pm_mode);
801 }
802
at91_pm_backup_scan_memcs(unsigned long node,const char * uname,int depth,void * data)803 static int __init at91_pm_backup_scan_memcs(unsigned long node,
804 const char *uname, int depth,
805 void *data)
806 {
807 const char *type;
808 const __be32 *reg;
809 int *located = data;
810 int size;
811
812 /* Memory node already located. */
813 if (*located)
814 return 0;
815
816 type = of_get_flat_dt_prop(node, "device_type", NULL);
817
818 /* We are scanning "memory" nodes only. */
819 if (!type || strcmp(type, "memory"))
820 return 0;
821
822 reg = of_get_flat_dt_prop(node, "reg", &size);
823 if (reg) {
824 soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg));
825 *located = 1;
826 }
827
828 return 0;
829 }
830
at91_pm_backup_init(void)831 static int __init at91_pm_backup_init(void)
832 {
833 struct gen_pool *sram_pool;
834 struct device_node *np;
835 struct platform_device *pdev;
836 int ret = -ENODEV, located = 0;
837
838 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) &&
839 !IS_ENABLED(CONFIG_SOC_SAMA7G5))
840 return -EPERM;
841
842 if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
843 return 0;
844
845 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
846 if (!np)
847 return ret;
848
849 pdev = of_find_device_by_node(np);
850 of_node_put(np);
851 if (!pdev) {
852 pr_warn("%s: failed to find securam device!\n", __func__);
853 return ret;
854 }
855
856 sram_pool = gen_pool_get(&pdev->dev, NULL);
857 if (!sram_pool) {
858 pr_warn("%s: securam pool unavailable!\n", __func__);
859 goto securam_fail;
860 }
861
862 soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
863 if (!soc_pm.bu) {
864 pr_warn("%s: unable to alloc securam!\n", __func__);
865 ret = -ENOMEM;
866 goto securam_fail;
867 }
868
869 soc_pm.bu->suspended = 0;
870 soc_pm.bu->canary = __pa_symbol(&canary);
871 soc_pm.bu->resume = __pa_symbol(cpu_resume);
872 if (soc_pm.data.ramc_phy) {
873 of_scan_flat_dt(at91_pm_backup_scan_memcs, &located);
874 if (!located)
875 goto securam_fail;
876 }
877
878 return 0;
879
880 securam_fail:
881 put_device(&pdev->dev);
882 return ret;
883 }
884
885 static const struct of_device_id atmel_shdwc_ids[] = {
886 { .compatible = "atmel,sama5d2-shdwc" },
887 { .compatible = "microchip,sam9x60-shdwc" },
888 { .compatible = "microchip,sama7g5-shdwc" },
889 { /* sentinel. */ }
890 };
891
at91_pm_modes_init(const u32 * maps,int len)892 static void __init at91_pm_modes_init(const u32 *maps, int len)
893 {
894 struct device_node *np;
895 int ret, mode;
896
897 ret = at91_pm_backup_init();
898 if (ret) {
899 if (soc_pm.data.standby_mode == AT91_PM_BACKUP)
900 soc_pm.data.standby_mode = AT91_PM_ULP0;
901 if (soc_pm.data.suspend_mode == AT91_PM_BACKUP)
902 soc_pm.data.suspend_mode = AT91_PM_ULP0;
903 }
904
905 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
906 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) {
907 np = of_find_matching_node(NULL, atmel_shdwc_ids);
908 if (!np) {
909 pr_warn("%s: failed to find shdwc!\n", __func__);
910
911 /* Use ULP0 if it doesn't needs SHDWC.*/
912 if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)))
913 mode = AT91_PM_ULP0;
914 else
915 mode = AT91_PM_STANDBY;
916
917 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC))
918 soc_pm.data.standby_mode = mode;
919 if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))
920 soc_pm.data.suspend_mode = mode;
921 } else {
922 soc_pm.data.shdwc = of_iomap(np, 0);
923 of_node_put(np);
924 }
925 }
926
927 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
928 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) {
929 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
930 if (!np) {
931 pr_warn("%s: failed to find sfrbu!\n", __func__);
932
933 /*
934 * Use ULP0 if it doesn't need SHDWC or if SHDWC
935 * was already located.
936 */
937 if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)) ||
938 soc_pm.data.shdwc)
939 mode = AT91_PM_ULP0;
940 else
941 mode = AT91_PM_STANDBY;
942
943 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU))
944 soc_pm.data.standby_mode = mode;
945 if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))
946 soc_pm.data.suspend_mode = mode;
947 } else {
948 soc_pm.data.sfrbu = of_iomap(np, 0);
949 of_node_put(np);
950 }
951 }
952
953 /* Unmap all unnecessary. */
954 if (soc_pm.data.shdwc &&
955 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
956 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) {
957 iounmap(soc_pm.data.shdwc);
958 soc_pm.data.shdwc = NULL;
959 }
960
961 if (soc_pm.data.sfrbu &&
962 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
963 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) {
964 iounmap(soc_pm.data.sfrbu);
965 soc_pm.data.sfrbu = NULL;
966 }
967
968 return;
969 }
970
971 struct pmc_info {
972 unsigned long uhp_udp_mask;
973 unsigned long mckr;
974 unsigned long version;
975 };
976
977 static const struct pmc_info pmc_infos[] __initconst = {
978 {
979 .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
980 .mckr = 0x30,
981 .version = AT91_PMC_V1,
982 },
983
984 {
985 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
986 .mckr = 0x30,
987 .version = AT91_PMC_V1,
988 },
989 {
990 .uhp_udp_mask = AT91SAM926x_PMC_UHP,
991 .mckr = 0x30,
992 .version = AT91_PMC_V1,
993 },
994 { .uhp_udp_mask = 0,
995 .mckr = 0x30,
996 .version = AT91_PMC_V1,
997 },
998 {
999 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
1000 .mckr = 0x28,
1001 .version = AT91_PMC_V2,
1002 },
1003 {
1004 .mckr = 0x28,
1005 .version = AT91_PMC_V2,
1006 },
1007
1008 };
1009
1010 static const struct of_device_id atmel_pmc_ids[] __initconst = {
1011 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
1012 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
1013 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
1014 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
1015 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
1016 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
1017 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
1018 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
1019 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
1020 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
1021 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
1022 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
1023 { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
1024 { /* sentinel */ },
1025 };
1026
at91_pm_modes_validate(const int * modes,int len)1027 static void __init at91_pm_modes_validate(const int *modes, int len)
1028 {
1029 u8 i, standby = 0, suspend = 0;
1030 int mode;
1031
1032 for (i = 0; i < len; i++) {
1033 if (standby && suspend)
1034 break;
1035
1036 if (modes[i] == soc_pm.data.standby_mode && !standby) {
1037 standby = 1;
1038 continue;
1039 }
1040
1041 if (modes[i] == soc_pm.data.suspend_mode && !suspend) {
1042 suspend = 1;
1043 continue;
1044 }
1045 }
1046
1047 if (!standby) {
1048 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY)
1049 mode = AT91_PM_ULP0;
1050 else
1051 mode = AT91_PM_STANDBY;
1052
1053 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
1054 pm_modes[soc_pm.data.standby_mode].pattern,
1055 pm_modes[mode].pattern);
1056 soc_pm.data.standby_mode = mode;
1057 }
1058
1059 if (!suspend) {
1060 if (soc_pm.data.standby_mode == AT91_PM_ULP0)
1061 mode = AT91_PM_STANDBY;
1062 else
1063 mode = AT91_PM_ULP0;
1064
1065 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
1066 pm_modes[soc_pm.data.suspend_mode].pattern,
1067 pm_modes[mode].pattern);
1068 soc_pm.data.suspend_mode = mode;
1069 }
1070 }
1071
at91_pm_init(void (* pm_idle)(void))1072 static void __init at91_pm_init(void (*pm_idle)(void))
1073 {
1074 struct device_node *pmc_np;
1075 const struct of_device_id *of_id;
1076 const struct pmc_info *pmc;
1077
1078 if (at91_cpuidle_device.dev.platform_data)
1079 platform_device_register(&at91_cpuidle_device);
1080
1081 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
1082 soc_pm.data.pmc = of_iomap(pmc_np, 0);
1083 of_node_put(pmc_np);
1084 if (!soc_pm.data.pmc) {
1085 pr_err("AT91: PM not supported, PMC not found\n");
1086 return;
1087 }
1088
1089 pmc = of_id->data;
1090 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
1091 soc_pm.data.pmc_mckr_offset = pmc->mckr;
1092 soc_pm.data.pmc_version = pmc->version;
1093
1094 if (pm_idle)
1095 arm_pm_idle = pm_idle;
1096
1097 at91_pm_sram_init();
1098
1099 if (at91_suspend_sram_fn) {
1100 suspend_set_ops(&at91_pm_ops);
1101 pr_info("AT91: PM: standby: %s, suspend: %s\n",
1102 pm_modes[soc_pm.data.standby_mode].pattern,
1103 pm_modes[soc_pm.data.suspend_mode].pattern);
1104 } else {
1105 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
1106 }
1107 }
1108
at91rm9200_pm_init(void)1109 void __init at91rm9200_pm_init(void)
1110 {
1111 int ret;
1112
1113 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
1114 return;
1115
1116 /*
1117 * Force STANDBY and ULP0 mode to avoid calling
1118 * at91_pm_modes_validate() which may increase booting time.
1119 * Platform supports anyway only STANDBY and ULP0 modes.
1120 */
1121 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1122 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1123
1124 ret = at91_dt_ramc(false);
1125 if (ret)
1126 return;
1127
1128 /*
1129 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
1130 */
1131 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
1132
1133 at91_pm_init(at91rm9200_idle);
1134 }
1135
sam9x60_pm_init(void)1136 void __init sam9x60_pm_init(void)
1137 {
1138 static const int modes[] __initconst = {
1139 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
1140 };
1141 static const int iomaps[] __initconst = {
1142 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
1143 };
1144 int ret;
1145
1146 if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
1147 return;
1148
1149 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1150 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1151 ret = at91_dt_ramc(false);
1152 if (ret)
1153 return;
1154
1155 at91_pm_init(NULL);
1156
1157 soc_pm.ws_ids = sam9x60_ws_ids;
1158 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
1159 }
1160
at91sam9_pm_init(void)1161 void __init at91sam9_pm_init(void)
1162 {
1163 int ret;
1164
1165 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
1166 return;
1167
1168 /*
1169 * Force STANDBY and ULP0 mode to avoid calling
1170 * at91_pm_modes_validate() which may increase booting time.
1171 * Platform supports anyway only STANDBY and ULP0 modes.
1172 */
1173 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1174 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1175
1176 ret = at91_dt_ramc(false);
1177 if (ret)
1178 return;
1179
1180 at91_pm_init(at91sam9_idle);
1181 }
1182
sama5_pm_init(void)1183 void __init sama5_pm_init(void)
1184 {
1185 static const int modes[] __initconst = {
1186 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
1187 };
1188 int ret;
1189
1190 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
1191 return;
1192
1193 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1194 ret = at91_dt_ramc(false);
1195 if (ret)
1196 return;
1197
1198 at91_pm_init(NULL);
1199 }
1200
sama5d2_pm_init(void)1201 void __init sama5d2_pm_init(void)
1202 {
1203 static const int modes[] __initconst = {
1204 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
1205 AT91_PM_BACKUP,
1206 };
1207 static const u32 iomaps[] __initconst = {
1208 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
1209 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) |
1210 AT91_PM_IOMAP(SFRBU),
1211 };
1212 int ret;
1213
1214 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
1215 return;
1216
1217 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1218 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1219 ret = at91_dt_ramc(false);
1220 if (ret)
1221 return;
1222
1223 at91_pm_init(NULL);
1224
1225 soc_pm.ws_ids = sama5d2_ws_ids;
1226 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
1227 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
1228
1229 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
1230 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
1231 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
1232 soc_pm.sfrbu_regs.pswbu.state = BIT(3);
1233 }
1234
sama7_pm_init(void)1235 void __init sama7_pm_init(void)
1236 {
1237 static const int modes[] __initconst = {
1238 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
1239 };
1240 static const u32 iomaps[] __initconst = {
1241 [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU),
1242 [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) |
1243 AT91_PM_IOMAP(SHDWC),
1244 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) |
1245 AT91_PM_IOMAP(SHDWC),
1246 };
1247 int ret;
1248
1249 if (!IS_ENABLED(CONFIG_SOC_SAMA7))
1250 return;
1251
1252 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1253
1254 ret = at91_dt_ramc(true);
1255 if (ret)
1256 return;
1257
1258 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1259 at91_pm_init(NULL);
1260
1261 soc_pm.ws_ids = sama7g5_ws_ids;
1262 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
1263
1264 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
1265 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
1266 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
1267 soc_pm.sfrbu_regs.pswbu.state = BIT(2);
1268 }
1269
at91_pm_modes_select(char * str)1270 static int __init at91_pm_modes_select(char *str)
1271 {
1272 char *s;
1273 substring_t args[MAX_OPT_ARGS];
1274 int standby, suspend;
1275
1276 if (!str)
1277 return 0;
1278
1279 s = strsep(&str, ",");
1280 standby = match_token(s, pm_modes, args);
1281 if (standby < 0)
1282 return 0;
1283
1284 suspend = match_token(str, pm_modes, args);
1285 if (suspend < 0)
1286 return 0;
1287
1288 soc_pm.data.standby_mode = standby;
1289 soc_pm.data.suspend_mode = suspend;
1290
1291 return 0;
1292 }
1293 early_param("atmel.pm_modes", at91_pm_modes_select);
1294