1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * arch/arm/mach-orion5x/pci.c
4 *
5 * PCI and PCIe functions for Marvell Orion System On Chip
6 *
7 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/mbus.h>
14 #include <video/vga.h>
15 #include <asm/irq.h>
16 #include <asm/mach/pci.h>
17 #include <plat/pcie.h>
18 #include <plat/addr-map.h>
19 #include "common.h"
20 #include "orion5x.h"
21
22 /*****************************************************************************
23 * Orion has one PCIe controller and one PCI controller.
24 *
25 * Note1: The local PCIe bus number is '0'. The local PCI bus number
26 * follows the scanned PCIe bridged busses, if any.
27 *
28 * Note2: It is possible for PCI/PCIe agents to access many subsystem's
29 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
30 * device bus, Orion registers, etc. However this code only enable the
31 * access to DDR banks.
32 ****************************************************************************/
33
34
35 /*****************************************************************************
36 * PCIe controller
37 ****************************************************************************/
38 #define PCIE_BASE (ORION5X_PCIE_VIRT_BASE)
39
orion5x_pcie_id(u32 * dev,u32 * rev)40 void __init orion5x_pcie_id(u32 *dev, u32 *rev)
41 {
42 *dev = orion_pcie_dev_id(PCIE_BASE);
43 *rev = orion_pcie_rev(PCIE_BASE);
44 }
45
pcie_valid_config(int bus,int dev)46 static int pcie_valid_config(int bus, int dev)
47 {
48 /*
49 * Don't go out when trying to access --
50 * 1. nonexisting device on local bus
51 * 2. where there's no device connected (no link)
52 */
53 if (bus == 0 && dev == 0)
54 return 1;
55
56 if (!orion_pcie_link_up(PCIE_BASE))
57 return 0;
58
59 if (bus == 0 && dev != 1)
60 return 0;
61
62 return 1;
63 }
64
65
66 /*
67 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
68 * and then reading the PCIE_CONF_DATA register. Need to make sure these
69 * transactions are atomic.
70 */
71 static DEFINE_SPINLOCK(orion5x_pcie_lock);
72
pcie_rd_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 * val)73 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
74 int size, u32 *val)
75 {
76 unsigned long flags;
77 int ret;
78
79 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
80 *val = 0xffffffff;
81 return PCIBIOS_DEVICE_NOT_FOUND;
82 }
83
84 spin_lock_irqsave(&orion5x_pcie_lock, flags);
85 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
86 spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
87
88 return ret;
89 }
90
pcie_rd_conf_wa(struct pci_bus * bus,u32 devfn,int where,int size,u32 * val)91 static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
92 int where, int size, u32 *val)
93 {
94 int ret;
95
96 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
97 *val = 0xffffffff;
98 return PCIBIOS_DEVICE_NOT_FOUND;
99 }
100
101 /*
102 * We only support access to the non-extended configuration
103 * space when using the WA access method (or we would have to
104 * sacrifice 256M of CPU virtual address space.)
105 */
106 if (where >= 0x100) {
107 *val = 0xffffffff;
108 return PCIBIOS_DEVICE_NOT_FOUND;
109 }
110
111 ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
112 bus, devfn, where, size, val);
113
114 return ret;
115 }
116
pcie_wr_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 val)117 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
118 int where, int size, u32 val)
119 {
120 unsigned long flags;
121 int ret;
122
123 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
124 return PCIBIOS_DEVICE_NOT_FOUND;
125
126 spin_lock_irqsave(&orion5x_pcie_lock, flags);
127 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
128 spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
129
130 return ret;
131 }
132
133 static struct pci_ops pcie_ops = {
134 .read = pcie_rd_conf,
135 .write = pcie_wr_conf,
136 };
137
138
pcie_setup(struct pci_sys_data * sys)139 static int __init pcie_setup(struct pci_sys_data *sys)
140 {
141 struct resource *res;
142 int dev;
143
144 /*
145 * Generic PCIe unit setup.
146 */
147 orion_pcie_setup(PCIE_BASE);
148
149 /*
150 * Check whether to apply Orion-1/Orion-NAS PCIe config
151 * read transaction workaround.
152 */
153 dev = orion_pcie_dev_id(PCIE_BASE);
154 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
155 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
156 "read transaction workaround\n");
157 mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
158 ORION_MBUS_PCIE_WA_ATTR,
159 ORION5X_PCIE_WA_PHYS_BASE,
160 ORION5X_PCIE_WA_SIZE);
161 pcie_ops.read = pcie_rd_conf_wa;
162 }
163
164 pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
165
166 /*
167 * Request resources.
168 */
169 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
170 if (!res)
171 panic("pcie_setup unable to alloc resources");
172
173 /*
174 * IORESOURCE_MEM
175 */
176 res->name = "PCIe Memory Space";
177 res->flags = IORESOURCE_MEM;
178 res->start = ORION5X_PCIE_MEM_PHYS_BASE;
179 res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
180 if (request_resource(&iomem_resource, res))
181 panic("Request PCIe Memory resource failed\n");
182 pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
183
184 return 1;
185 }
186
187 /*****************************************************************************
188 * PCI controller
189 ****************************************************************************/
190 #define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x))
191 #define PCI_MODE ORION5X_PCI_REG(0xd00)
192 #define PCI_CMD ORION5X_PCI_REG(0xc00)
193 #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
194 #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78)
195 #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c)
196
197 /*
198 * PCI_MODE bits
199 */
200 #define PCI_MODE_64BIT (1 << 2)
201 #define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
202
203 /*
204 * PCI_CMD bits
205 */
206 #define PCI_CMD_HOST_REORDER (1 << 29)
207
208 /*
209 * PCI_P2P_CONF bits
210 */
211 #define PCI_P2P_BUS_OFFS 16
212 #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
213 #define PCI_P2P_DEV_OFFS 24
214 #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
215
216 /*
217 * PCI_CONF_ADDR bits
218 */
219 #define PCI_CONF_REG(reg) ((reg) & 0xfc)
220 #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
221 #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
222 #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
223 #define PCI_CONF_ADDR_EN (1 << 31)
224
225 /*
226 * Internal configuration space
227 */
228 #define PCI_CONF_FUNC_STAT_CMD 0
229 #define PCI_CONF_REG_STAT_CMD 4
230 #define PCIX_STAT 0x64
231 #define PCIX_STAT_BUS_OFFS 8
232 #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
233
234 /*
235 * PCI Address Decode Windows registers
236 */
237 #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
238 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
239 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
240 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : NULL)
241 #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
242 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
243 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
244 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : NULL)
245 #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
246 #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
247
248 /*
249 * PCI configuration helpers for BAR settings
250 */
251 #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
252 #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
253 #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
254
255 /*
256 * PCI config cycles are done by programming the PCI_CONF_ADDR register
257 * and then reading the PCI_CONF_DATA register. Need to make sure these
258 * transactions are atomic.
259 */
260 static DEFINE_SPINLOCK(orion5x_pci_lock);
261
262 static int orion5x_pci_cardbus_mode;
263
orion5x_pci_local_bus_nr(void)264 static int orion5x_pci_local_bus_nr(void)
265 {
266 u32 conf = readl(PCI_P2P_CONF);
267 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
268 }
269
orion5x_pci_hw_rd_conf(int bus,int dev,u32 func,u32 where,u32 size,u32 * val)270 static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
271 u32 where, u32 size, u32 *val)
272 {
273 unsigned long flags;
274 spin_lock_irqsave(&orion5x_pci_lock, flags);
275
276 writel(PCI_CONF_BUS(bus) |
277 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
278 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
279
280 *val = readl(PCI_CONF_DATA);
281
282 if (size == 1)
283 *val = (*val >> (8*(where & 0x3))) & 0xff;
284 else if (size == 2)
285 *val = (*val >> (8*(where & 0x3))) & 0xffff;
286
287 spin_unlock_irqrestore(&orion5x_pci_lock, flags);
288
289 return PCIBIOS_SUCCESSFUL;
290 }
291
orion5x_pci_hw_wr_conf(int bus,int dev,u32 func,u32 where,u32 size,u32 val)292 static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
293 u32 where, u32 size, u32 val)
294 {
295 unsigned long flags;
296 int ret = PCIBIOS_SUCCESSFUL;
297
298 spin_lock_irqsave(&orion5x_pci_lock, flags);
299
300 writel(PCI_CONF_BUS(bus) |
301 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
302 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
303
304 if (size == 4) {
305 __raw_writel(val, PCI_CONF_DATA);
306 } else if (size == 2) {
307 __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
308 } else if (size == 1) {
309 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
310 } else {
311 ret = PCIBIOS_BAD_REGISTER_NUMBER;
312 }
313
314 spin_unlock_irqrestore(&orion5x_pci_lock, flags);
315
316 return ret;
317 }
318
orion5x_pci_valid_config(int bus,u32 devfn)319 static int orion5x_pci_valid_config(int bus, u32 devfn)
320 {
321 if (bus == orion5x_pci_local_bus_nr()) {
322 /*
323 * Don't go out for local device
324 */
325 if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
326 return 0;
327
328 /*
329 * When the PCI signals are directly connected to a
330 * Cardbus slot, ignore all but device IDs 0 and 1.
331 */
332 if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
333 return 0;
334 }
335
336 return 1;
337 }
338
orion5x_pci_rd_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 * val)339 static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
340 int where, int size, u32 *val)
341 {
342 if (!orion5x_pci_valid_config(bus->number, devfn)) {
343 *val = 0xffffffff;
344 return PCIBIOS_DEVICE_NOT_FOUND;
345 }
346
347 return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
348 PCI_FUNC(devfn), where, size, val);
349 }
350
orion5x_pci_wr_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 val)351 static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
352 int where, int size, u32 val)
353 {
354 if (!orion5x_pci_valid_config(bus->number, devfn))
355 return PCIBIOS_DEVICE_NOT_FOUND;
356
357 return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
358 PCI_FUNC(devfn), where, size, val);
359 }
360
361 static struct pci_ops pci_ops = {
362 .read = orion5x_pci_rd_conf,
363 .write = orion5x_pci_wr_conf,
364 };
365
orion5x_pci_set_bus_nr(int nr)366 static void __init orion5x_pci_set_bus_nr(int nr)
367 {
368 u32 p2p = readl(PCI_P2P_CONF);
369
370 if (readl(PCI_MODE) & PCI_MODE_PCIX) {
371 /*
372 * PCI-X mode
373 */
374 u32 pcix_status, bus, dev;
375 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
376 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
377 orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
378 pcix_status &= ~PCIX_STAT_BUS_MASK;
379 pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
380 orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
381 } else {
382 /*
383 * PCI Conventional mode
384 */
385 p2p &= ~PCI_P2P_BUS_MASK;
386 p2p |= (nr << PCI_P2P_BUS_OFFS);
387 writel(p2p, PCI_P2P_CONF);
388 }
389 }
390
orion5x_pci_master_slave_enable(void)391 static void __init orion5x_pci_master_slave_enable(void)
392 {
393 int bus_nr, func, reg;
394 u32 val;
395
396 bus_nr = orion5x_pci_local_bus_nr();
397 func = PCI_CONF_FUNC_STAT_CMD;
398 reg = PCI_CONF_REG_STAT_CMD;
399 orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
400 val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
401 orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
402 }
403
orion5x_setup_pci_wins(void)404 static void __init orion5x_setup_pci_wins(void)
405 {
406 const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
407 u32 win_enable;
408 int bus;
409 int i;
410
411 /*
412 * First, disable windows.
413 */
414 win_enable = 0xffffffff;
415 writel(win_enable, PCI_BAR_ENABLE);
416
417 /*
418 * Setup windows for DDR banks.
419 */
420 bus = orion5x_pci_local_bus_nr();
421
422 for (i = 0; i < dram->num_cs; i++) {
423 const struct mbus_dram_window *cs = dram->cs + i;
424 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
425 u32 reg;
426 u32 val;
427
428 /*
429 * Write DRAM bank base address register.
430 */
431 reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
432 orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
433 val = (cs->base & 0xfffff000) | (val & 0xfff);
434 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
435
436 /*
437 * Write DRAM bank size register.
438 */
439 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
440 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
441 writel((cs->size - 1) & 0xfffff000,
442 PCI_BAR_SIZE_DDR_CS(cs->cs_index));
443 writel(cs->base & 0xfffff000,
444 PCI_BAR_REMAP_DDR_CS(cs->cs_index));
445
446 /*
447 * Enable decode window for this chip select.
448 */
449 win_enable &= ~(1 << cs->cs_index);
450 }
451
452 /*
453 * Re-enable decode windows.
454 */
455 writel(win_enable, PCI_BAR_ENABLE);
456
457 /*
458 * Disable automatic update of address remapping when writing to BARs.
459 */
460 orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
461 }
462
pci_setup(struct pci_sys_data * sys)463 static int __init pci_setup(struct pci_sys_data *sys)
464 {
465 struct resource *res;
466
467 /*
468 * Point PCI unit MBUS decode windows to DRAM space.
469 */
470 orion5x_setup_pci_wins();
471
472 /*
473 * Master + Slave enable
474 */
475 orion5x_pci_master_slave_enable();
476
477 /*
478 * Force ordering
479 */
480 orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
481
482 pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE);
483
484 /*
485 * Request resources
486 */
487 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
488 if (!res)
489 panic("pci_setup unable to alloc resources");
490
491 /*
492 * IORESOURCE_MEM
493 */
494 res->name = "PCI Memory Space";
495 res->flags = IORESOURCE_MEM;
496 res->start = ORION5X_PCI_MEM_PHYS_BASE;
497 res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
498 if (request_resource(&iomem_resource, res))
499 panic("Request PCI Memory resource failed\n");
500 pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
501
502 return 1;
503 }
504
505
506 /*****************************************************************************
507 * General PCIe + PCI
508 ****************************************************************************/
rc_pci_fixup(struct pci_dev * dev)509 static void rc_pci_fixup(struct pci_dev *dev)
510 {
511 /*
512 * Prevent enumeration of root complex.
513 */
514 if (dev->bus->parent == NULL && dev->devfn == 0) {
515 int i;
516
517 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
518 dev->resource[i].start = 0;
519 dev->resource[i].end = 0;
520 dev->resource[i].flags = 0;
521 }
522 }
523 }
524 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
525
526 static int orion5x_pci_disabled __initdata;
527
orion5x_pci_disable(void)528 void __init orion5x_pci_disable(void)
529 {
530 orion5x_pci_disabled = 1;
531 }
532
orion5x_pci_set_cardbus_mode(void)533 void __init orion5x_pci_set_cardbus_mode(void)
534 {
535 orion5x_pci_cardbus_mode = 1;
536 }
537
orion5x_pci_sys_setup(int nr,struct pci_sys_data * sys)538 int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
539 {
540 vga_base = ORION5X_PCIE_MEM_PHYS_BASE;
541
542 if (nr == 0) {
543 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
544 return pcie_setup(sys);
545 }
546
547 if (nr == 1 && !orion5x_pci_disabled) {
548 orion5x_pci_set_bus_nr(sys->busnr);
549 return pci_setup(sys);
550 }
551
552 return 0;
553 }
554
orion5x_pci_sys_scan_bus(int nr,struct pci_host_bridge * bridge)555 int __init orion5x_pci_sys_scan_bus(int nr, struct pci_host_bridge *bridge)
556 {
557 struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
558
559 list_splice_init(&sys->resources, &bridge->windows);
560 bridge->dev.parent = NULL;
561 bridge->sysdata = sys;
562 bridge->busnr = sys->busnr;
563
564 if (nr == 0) {
565 bridge->ops = &pcie_ops;
566 return pci_scan_root_bus_bridge(bridge);
567 }
568
569 if (nr == 1 && !orion5x_pci_disabled) {
570 bridge->ops = &pci_ops;
571 return pci_scan_root_bus_bridge(bridge);
572 }
573
574 BUG();
575 return -ENODEV;
576 }
577
orion5x_pci_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)578 int __init orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
579 {
580 int bus = dev->bus->number;
581
582 /*
583 * PCIe endpoint?
584 */
585 if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr())
586 return IRQ_ORION5X_PCIE0_INT;
587
588 return -1;
589 }
590