1// SPDX-License-Identifier: GPL-2.0 2#include "juno-clocks.dtsi" 3#include "juno-motherboard.dtsi" 4 5/ { 6 /* 7 * Devices shared by all Juno boards 8 */ 9 10 memtimer: timer@2a810000 { 11 compatible = "arm,armv7-timer-mem"; 12 reg = <0x0 0x2a810000 0x0 0x10000>; 13 clock-frequency = <50000000>; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 ranges = <0 0x0 0x2a820000 0x20000>; 17 status = "disabled"; 18 frame@2a830000 { 19 frame-number = <1>; 20 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 21 reg = <0x10000 0x10000>; 22 }; 23 }; 24 25 mailbox: mhu@2b1f0000 { 26 compatible = "arm,mhu", "arm,primecell"; 27 reg = <0x0 0x2b1f0000 0x0 0x1000>; 28 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 31 #mbox-cells = <1>; 32 clocks = <&soc_refclk100mhz>; 33 clock-names = "apb_pclk"; 34 }; 35 36 smmu_gpu: iommu@2b400000 { 37 compatible = "arm,mmu-400", "arm,smmu-v1"; 38 reg = <0x0 0x2b400000 0x0 0x10000>; 39 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 41 #iommu-cells = <1>; 42 #global-interrupts = <1>; 43 power-domains = <&scpi_devpd 1>; 44 dma-coherent; 45 status = "disabled"; 46 }; 47 48 smmu_pcie: iommu@2b500000 { 49 compatible = "arm,mmu-401", "arm,smmu-v1"; 50 reg = <0x0 0x2b500000 0x0 0x10000>; 51 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 53 #iommu-cells = <1>; 54 #global-interrupts = <1>; 55 dma-coherent; 56 status = "disabled"; 57 }; 58 59 smmu_etr: iommu@2b600000 { 60 compatible = "arm,mmu-401", "arm,smmu-v1"; 61 reg = <0x0 0x2b600000 0x0 0x10000>; 62 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 64 #iommu-cells = <1>; 65 #global-interrupts = <1>; 66 dma-coherent; 67 power-domains = <&scpi_devpd 0>; 68 }; 69 70 gic: interrupt-controller@2c010000 { 71 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 72 reg = <0x0 0x2c010000 0 0x1000>, 73 <0x0 0x2c02f000 0 0x2000>, 74 <0x0 0x2c04f000 0 0x2000>, 75 <0x0 0x2c06f000 0 0x2000>; 76 #address-cells = <1>; 77 #interrupt-cells = <3>; 78 #size-cells = <1>; 79 interrupt-controller; 80 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 81 ranges = <0 0 0x2c1c0000 0x40000>; 82 83 v2m_0: v2m@0 { 84 compatible = "arm,gic-v2m-frame"; 85 msi-controller; 86 reg = <0 0x10000>; 87 }; 88 89 v2m@10000 { 90 compatible = "arm,gic-v2m-frame"; 91 msi-controller; 92 reg = <0x10000 0x10000>; 93 }; 94 95 v2m@20000 { 96 compatible = "arm,gic-v2m-frame"; 97 msi-controller; 98 reg = <0x20000 0x10000>; 99 }; 100 101 v2m@30000 { 102 compatible = "arm,gic-v2m-frame"; 103 msi-controller; 104 reg = <0x30000 0x10000>; 105 }; 106 }; 107 108 timer { 109 compatible = "arm,armv8-timer"; 110 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 111 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 112 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 113 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 114 }; 115 116 /* 117 * Juno TRMs specify the size for these coresight components as 64K. 118 * The actual size is just 4K though 64K is reserved. Access to the 119 * unmapped reserved region results in a DECERR response. 120 */ 121 etf@20010000 { /* etf0 */ 122 compatible = "arm,coresight-tmc", "arm,primecell"; 123 reg = <0 0x20010000 0 0x1000>; 124 125 clocks = <&soc_smc50mhz>; 126 clock-names = "apb_pclk"; 127 power-domains = <&scpi_devpd 0>; 128 129 in-ports { 130 port { 131 etf0_in_port: endpoint { 132 remote-endpoint = <&main_funnel_out_port>; 133 }; 134 }; 135 }; 136 137 out-ports { 138 port { 139 etf0_out_port: endpoint { 140 }; 141 }; 142 }; 143 }; 144 145 tpiu@20030000 { 146 compatible = "arm,coresight-tpiu", "arm,primecell"; 147 reg = <0 0x20030000 0 0x1000>; 148 149 clocks = <&soc_smc50mhz>; 150 clock-names = "apb_pclk"; 151 power-domains = <&scpi_devpd 0>; 152 in-ports { 153 port { 154 tpiu_in_port: endpoint { 155 remote-endpoint = <&replicator_out_port0>; 156 }; 157 }; 158 }; 159 }; 160 161 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/ 162 main_funnel: funnel@20040000 { 163 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 164 reg = <0 0x20040000 0 0x1000>; 165 166 clocks = <&soc_smc50mhz>; 167 clock-names = "apb_pclk"; 168 power-domains = <&scpi_devpd 0>; 169 170 out-ports { 171 port { 172 main_funnel_out_port: endpoint { 173 remote-endpoint = <&etf0_in_port>; 174 }; 175 }; 176 }; 177 178 main_funnel_in_ports: in-ports { 179 #address-cells = <1>; 180 #size-cells = <0>; 181 182 port@0 { 183 reg = <0>; 184 main_funnel_in_port0: endpoint { 185 remote-endpoint = <&cluster0_funnel_out_port>; 186 }; 187 }; 188 189 port@1 { 190 reg = <1>; 191 main_funnel_in_port1: endpoint { 192 remote-endpoint = <&cluster1_funnel_out_port>; 193 }; 194 }; 195 }; 196 }; 197 198 etr@20070000 { 199 compatible = "arm,coresight-tmc", "arm,primecell"; 200 reg = <0 0x20070000 0 0x1000>; 201 iommus = <&smmu_etr 0>; 202 203 clocks = <&soc_smc50mhz>; 204 clock-names = "apb_pclk"; 205 power-domains = <&scpi_devpd 0>; 206 arm,scatter-gather; 207 in-ports { 208 port { 209 etr_in_port: endpoint { 210 remote-endpoint = <&replicator_out_port1>; 211 }; 212 }; 213 }; 214 }; 215 216 stm@20100000 { 217 compatible = "arm,coresight-stm", "arm,primecell"; 218 reg = <0 0x20100000 0 0x1000>, 219 <0 0x28000000 0 0x1000000>; 220 reg-names = "stm-base", "stm-stimulus-base"; 221 222 clocks = <&soc_smc50mhz>; 223 clock-names = "apb_pclk"; 224 power-domains = <&scpi_devpd 0>; 225 out-ports { 226 port { 227 stm_out_port: endpoint { 228 }; 229 }; 230 }; 231 }; 232 233 replicator@20120000 { 234 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 235 reg = <0 0x20120000 0 0x1000>; 236 237 clocks = <&soc_smc50mhz>; 238 clock-names = "apb_pclk"; 239 power-domains = <&scpi_devpd 0>; 240 241 out-ports { 242 #address-cells = <1>; 243 #size-cells = <0>; 244 245 /* replicator output ports */ 246 port@0 { 247 reg = <0>; 248 replicator_out_port0: endpoint { 249 remote-endpoint = <&tpiu_in_port>; 250 }; 251 }; 252 253 port@1 { 254 reg = <1>; 255 replicator_out_port1: endpoint { 256 remote-endpoint = <&etr_in_port>; 257 }; 258 }; 259 }; 260 in-ports { 261 port { 262 replicator_in_port0: endpoint { 263 }; 264 }; 265 }; 266 }; 267 268 cpu_debug0: cpu-debug@22010000 { 269 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 270 reg = <0x0 0x22010000 0x0 0x1000>; 271 272 clocks = <&soc_smc50mhz>; 273 clock-names = "apb_pclk"; 274 power-domains = <&scpi_devpd 0>; 275 }; 276 277 etm0: etm@22040000 { 278 compatible = "arm,coresight-etm4x", "arm,primecell"; 279 reg = <0 0x22040000 0 0x1000>; 280 281 clocks = <&soc_smc50mhz>; 282 clock-names = "apb_pclk"; 283 power-domains = <&scpi_devpd 0>; 284 out-ports { 285 port { 286 cluster0_etm0_out_port: endpoint { 287 remote-endpoint = <&cluster0_funnel_in_port0>; 288 }; 289 }; 290 }; 291 }; 292 293 funnel@220c0000 { /* cluster0 funnel */ 294 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 295 reg = <0 0x220c0000 0 0x1000>; 296 297 clocks = <&soc_smc50mhz>; 298 clock-names = "apb_pclk"; 299 power-domains = <&scpi_devpd 0>; 300 out-ports { 301 port { 302 cluster0_funnel_out_port: endpoint { 303 remote-endpoint = <&main_funnel_in_port0>; 304 }; 305 }; 306 }; 307 308 in-ports { 309 #address-cells = <1>; 310 #size-cells = <0>; 311 312 port@0 { 313 reg = <0>; 314 cluster0_funnel_in_port0: endpoint { 315 remote-endpoint = <&cluster0_etm0_out_port>; 316 }; 317 }; 318 319 port@1 { 320 reg = <1>; 321 cluster0_funnel_in_port1: endpoint { 322 remote-endpoint = <&cluster0_etm1_out_port>; 323 }; 324 }; 325 }; 326 }; 327 328 cpu_debug1: cpu-debug@22110000 { 329 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 330 reg = <0x0 0x22110000 0x0 0x1000>; 331 332 clocks = <&soc_smc50mhz>; 333 clock-names = "apb_pclk"; 334 power-domains = <&scpi_devpd 0>; 335 }; 336 337 etm1: etm@22140000 { 338 compatible = "arm,coresight-etm4x", "arm,primecell"; 339 reg = <0 0x22140000 0 0x1000>; 340 341 clocks = <&soc_smc50mhz>; 342 clock-names = "apb_pclk"; 343 power-domains = <&scpi_devpd 0>; 344 out-ports { 345 port { 346 cluster0_etm1_out_port: endpoint { 347 remote-endpoint = <&cluster0_funnel_in_port1>; 348 }; 349 }; 350 }; 351 }; 352 353 cpu_debug2: cpu-debug@23010000 { 354 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 355 reg = <0x0 0x23010000 0x0 0x1000>; 356 357 clocks = <&soc_smc50mhz>; 358 clock-names = "apb_pclk"; 359 power-domains = <&scpi_devpd 0>; 360 }; 361 362 etm2: etm@23040000 { 363 compatible = "arm,coresight-etm4x", "arm,primecell"; 364 reg = <0 0x23040000 0 0x1000>; 365 366 clocks = <&soc_smc50mhz>; 367 clock-names = "apb_pclk"; 368 power-domains = <&scpi_devpd 0>; 369 out-ports { 370 port { 371 cluster1_etm0_out_port: endpoint { 372 remote-endpoint = <&cluster1_funnel_in_port0>; 373 }; 374 }; 375 }; 376 }; 377 378 funnel@230c0000 { /* cluster1 funnel */ 379 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 380 reg = <0 0x230c0000 0 0x1000>; 381 382 clocks = <&soc_smc50mhz>; 383 clock-names = "apb_pclk"; 384 power-domains = <&scpi_devpd 0>; 385 out-ports { 386 port { 387 cluster1_funnel_out_port: endpoint { 388 remote-endpoint = <&main_funnel_in_port1>; 389 }; 390 }; 391 }; 392 393 in-ports { 394 #address-cells = <1>; 395 #size-cells = <0>; 396 397 port@0 { 398 reg = <0>; 399 cluster1_funnel_in_port0: endpoint { 400 remote-endpoint = <&cluster1_etm0_out_port>; 401 }; 402 }; 403 404 port@1 { 405 reg = <1>; 406 cluster1_funnel_in_port1: endpoint { 407 remote-endpoint = <&cluster1_etm1_out_port>; 408 }; 409 }; 410 port@2 { 411 reg = <2>; 412 cluster1_funnel_in_port2: endpoint { 413 remote-endpoint = <&cluster1_etm2_out_port>; 414 }; 415 }; 416 port@3 { 417 reg = <3>; 418 cluster1_funnel_in_port3: endpoint { 419 remote-endpoint = <&cluster1_etm3_out_port>; 420 }; 421 }; 422 }; 423 }; 424 425 cpu_debug3: cpu-debug@23110000 { 426 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 427 reg = <0x0 0x23110000 0x0 0x1000>; 428 429 clocks = <&soc_smc50mhz>; 430 clock-names = "apb_pclk"; 431 power-domains = <&scpi_devpd 0>; 432 }; 433 434 etm3: etm@23140000 { 435 compatible = "arm,coresight-etm4x", "arm,primecell"; 436 reg = <0 0x23140000 0 0x1000>; 437 438 clocks = <&soc_smc50mhz>; 439 clock-names = "apb_pclk"; 440 power-domains = <&scpi_devpd 0>; 441 out-ports { 442 port { 443 cluster1_etm1_out_port: endpoint { 444 remote-endpoint = <&cluster1_funnel_in_port1>; 445 }; 446 }; 447 }; 448 }; 449 450 cpu_debug4: cpu-debug@23210000 { 451 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 452 reg = <0x0 0x23210000 0x0 0x1000>; 453 454 clocks = <&soc_smc50mhz>; 455 clock-names = "apb_pclk"; 456 power-domains = <&scpi_devpd 0>; 457 }; 458 459 etm4: etm@23240000 { 460 compatible = "arm,coresight-etm4x", "arm,primecell"; 461 reg = <0 0x23240000 0 0x1000>; 462 463 clocks = <&soc_smc50mhz>; 464 clock-names = "apb_pclk"; 465 power-domains = <&scpi_devpd 0>; 466 out-ports { 467 port { 468 cluster1_etm2_out_port: endpoint { 469 remote-endpoint = <&cluster1_funnel_in_port2>; 470 }; 471 }; 472 }; 473 }; 474 475 cpu_debug5: cpu-debug@23310000 { 476 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 477 reg = <0x0 0x23310000 0x0 0x1000>; 478 479 clocks = <&soc_smc50mhz>; 480 clock-names = "apb_pclk"; 481 power-domains = <&scpi_devpd 0>; 482 }; 483 484 etm5: etm@23340000 { 485 compatible = "arm,coresight-etm4x", "arm,primecell"; 486 reg = <0 0x23340000 0 0x1000>; 487 488 clocks = <&soc_smc50mhz>; 489 clock-names = "apb_pclk"; 490 power-domains = <&scpi_devpd 0>; 491 out-ports { 492 port { 493 cluster1_etm3_out_port: endpoint { 494 remote-endpoint = <&cluster1_funnel_in_port3>; 495 }; 496 }; 497 }; 498 }; 499 500 gpu: gpu@2d000000 { 501 compatible = "arm,juno-mali", "arm,mali-t624"; 502 reg = <0 0x2d000000 0 0x10000>; 503 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 506 interrupt-names = "job", "mmu", "gpu"; 507 clocks = <&scpi_dvfs 2>; 508 power-domains = <&scpi_devpd 1>; 509 dma-coherent; 510 /* The SMMU is only really of interest to bare-metal hypervisors */ 511 /* iommus = <&smmu_gpu 0>; */ 512 status = "disabled"; 513 }; 514 515 sram: sram@2e000000 { 516 compatible = "arm,juno-sram-ns", "mmio-sram"; 517 reg = <0x0 0x2e000000 0x0 0x8000>; 518 519 #address-cells = <1>; 520 #size-cells = <1>; 521 ranges = <0 0x0 0x2e000000 0x8000>; 522 523 cpu_scp_lpri: scp-sram@0 { 524 compatible = "arm,juno-scp-shmem"; 525 reg = <0x0 0x200>; 526 }; 527 528 cpu_scp_hpri: scp-sram@200 { 529 compatible = "arm,juno-scp-shmem"; 530 reg = <0x200 0x200>; 531 }; 532 }; 533 534 pcie_ctlr: pcie@40000000 { 535 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic"; 536 device_type = "pci"; 537 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */ 538 bus-range = <0 255>; 539 linux,pci-domain = <0>; 540 #address-cells = <3>; 541 #size-cells = <2>; 542 dma-coherent; 543 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>, 544 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, 545 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; 546 /* Standard AXI Translation entries as programmed by EDK2 */ 547 dma-ranges = <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>, 548 <0x43000000 0x8 0x00000000 0x8 0x00000000 0x2 0x00000000>; 549 #interrupt-cells = <1>; 550 interrupt-map-mask = <0 0 0 7>; 551 interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 552 <0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 553 <0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 554 <0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 555 msi-parent = <&v2m_0>; 556 status = "disabled"; 557 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */ 558 iommu-map = <0x0 &smmu_pcie 0x0 0x1>; 559 }; 560 561 scpi { 562 compatible = "arm,scpi"; 563 mboxes = <&mailbox 1>; 564 shmem = <&cpu_scp_hpri>; 565 566 clocks { 567 compatible = "arm,scpi-clocks"; 568 569 scpi_dvfs: clocks-0 { 570 compatible = "arm,scpi-dvfs-clocks"; 571 #clock-cells = <1>; 572 clock-indices = <0>, <1>, <2>; 573 clock-output-names = "atlclk", "aplclk","gpuclk"; 574 }; 575 scpi_clk: clocks-1 { 576 compatible = "arm,scpi-variable-clocks"; 577 #clock-cells = <1>; 578 clock-indices = <3>; 579 clock-output-names = "pxlclk"; 580 }; 581 }; 582 583 scpi_devpd: power-controller { 584 compatible = "arm,scpi-power-domains"; 585 num-domains = <2>; 586 #power-domain-cells = <1>; 587 }; 588 589 scpi_sensors0: sensors { 590 compatible = "arm,scpi-sensors"; 591 #thermal-sensor-cells = <1>; 592 }; 593 }; 594 595 thermal-zones { 596 pmic { 597 polling-delay = <1000>; 598 polling-delay-passive = <100>; 599 thermal-sensors = <&scpi_sensors0 0>; 600 trips { 601 pmic_crit0: trip0 { 602 temperature = <90000>; 603 hysteresis = <2000>; 604 type = "critical"; 605 }; 606 }; 607 }; 608 609 soc { 610 polling-delay = <1000>; 611 polling-delay-passive = <100>; 612 thermal-sensors = <&scpi_sensors0 3>; 613 trips { 614 soc_crit0: trip0 { 615 temperature = <80000>; 616 hysteresis = <2000>; 617 type = "critical"; 618 }; 619 }; 620 }; 621 622 big_cluster_thermal_zone: big-cluster { 623 polling-delay = <1000>; 624 polling-delay-passive = <100>; 625 thermal-sensors = <&scpi_sensors0 21>; 626 status = "disabled"; 627 }; 628 629 little_cluster_thermal_zone: little-cluster { 630 polling-delay = <1000>; 631 polling-delay-passive = <100>; 632 thermal-sensors = <&scpi_sensors0 22>; 633 status = "disabled"; 634 }; 635 636 gpu0_thermal_zone: gpu0 { 637 polling-delay = <1000>; 638 polling-delay-passive = <100>; 639 thermal-sensors = <&scpi_sensors0 23>; 640 status = "disabled"; 641 }; 642 643 gpu1_thermal_zone: gpu1 { 644 polling-delay = <1000>; 645 polling-delay-passive = <100>; 646 thermal-sensors = <&scpi_sensors0 24>; 647 status = "disabled"; 648 }; 649 }; 650 651 smmu_dma: iommu@7fb00000 { 652 compatible = "arm,mmu-401", "arm,smmu-v1"; 653 reg = <0x0 0x7fb00000 0x0 0x10000>; 654 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 656 #iommu-cells = <1>; 657 #global-interrupts = <1>; 658 dma-coherent; 659 }; 660 661 smmu_hdlcd1: iommu@7fb10000 { 662 compatible = "arm,mmu-401", "arm,smmu-v1"; 663 reg = <0x0 0x7fb10000 0x0 0x10000>; 664 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 666 #iommu-cells = <1>; 667 #global-interrupts = <1>; 668 }; 669 670 smmu_hdlcd0: iommu@7fb20000 { 671 compatible = "arm,mmu-401", "arm,smmu-v1"; 672 reg = <0x0 0x7fb20000 0x0 0x10000>; 673 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 675 #iommu-cells = <1>; 676 #global-interrupts = <1>; 677 }; 678 679 smmu_usb: iommu@7fb30000 { 680 compatible = "arm,mmu-401", "arm,smmu-v1"; 681 reg = <0x0 0x7fb30000 0x0 0x10000>; 682 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 684 #iommu-cells = <1>; 685 #global-interrupts = <1>; 686 dma-coherent; 687 }; 688 689 dma@7ff00000 { 690 compatible = "arm,pl330", "arm,primecell"; 691 reg = <0x0 0x7ff00000 0 0x1000>; 692 #dma-cells = <1>; 693 #dma-channels = <8>; 694 #dma-requests = <32>; 695 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 704 iommus = <&smmu_dma 0>, 705 <&smmu_dma 1>, 706 <&smmu_dma 2>, 707 <&smmu_dma 3>, 708 <&smmu_dma 4>, 709 <&smmu_dma 5>, 710 <&smmu_dma 6>, 711 <&smmu_dma 7>, 712 <&smmu_dma 8>; 713 clocks = <&soc_faxiclk>; 714 clock-names = "apb_pclk"; 715 }; 716 717 hdlcd@7ff50000 { 718 compatible = "arm,hdlcd"; 719 reg = <0 0x7ff50000 0 0x1000>; 720 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 721 iommus = <&smmu_hdlcd1 0>; 722 clocks = <&scpi_clk 3>; 723 clock-names = "pxlclk"; 724 725 port { 726 hdlcd1_output: endpoint { 727 remote-endpoint = <&tda998x_1_input>; 728 }; 729 }; 730 }; 731 732 hdlcd@7ff60000 { 733 compatible = "arm,hdlcd"; 734 reg = <0 0x7ff60000 0 0x1000>; 735 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 736 iommus = <&smmu_hdlcd0 0>; 737 clocks = <&scpi_clk 3>; 738 clock-names = "pxlclk"; 739 740 port { 741 hdlcd0_output: endpoint { 742 remote-endpoint = <&tda998x_0_input>; 743 }; 744 }; 745 }; 746 747 soc_uart0: serial@7ff80000 { 748 compatible = "arm,pl011", "arm,primecell"; 749 reg = <0x0 0x7ff80000 0x0 0x1000>; 750 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&soc_uartclk>, <&soc_refclk100mhz>; 752 clock-names = "uartclk", "apb_pclk"; 753 }; 754 755 i2c@7ffa0000 { 756 compatible = "snps,designware-i2c"; 757 reg = <0x0 0x7ffa0000 0x0 0x1000>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 761 clock-frequency = <400000>; 762 i2c-sda-hold-time-ns = <500>; 763 clocks = <&soc_smc50mhz>; 764 765 hdmi-transmitter@70 { 766 compatible = "nxp,tda998x"; 767 reg = <0x70>; 768 port { 769 tda998x_0_input: endpoint { 770 remote-endpoint = <&hdlcd0_output>; 771 }; 772 }; 773 }; 774 775 hdmi-transmitter@71 { 776 compatible = "nxp,tda998x"; 777 reg = <0x71>; 778 port { 779 tda998x_1_input: endpoint { 780 remote-endpoint = <&hdlcd1_output>; 781 }; 782 }; 783 }; 784 }; 785 786 usb@7ffb0000 { 787 compatible = "generic-ohci"; 788 reg = <0x0 0x7ffb0000 0x0 0x10000>; 789 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 790 iommus = <&smmu_usb 0>; 791 clocks = <&soc_usb48mhz>; 792 }; 793 794 usb@7ffc0000 { 795 compatible = "generic-ehci"; 796 reg = <0x0 0x7ffc0000 0x0 0x10000>; 797 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 798 iommus = <&smmu_usb 0>; 799 clocks = <&soc_usb48mhz>; 800 }; 801 802 memory-controller@7ffd0000 { 803 compatible = "arm,pl354", "arm,primecell"; 804 reg = <0 0x7ffd0000 0 0x1000>; 805 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&soc_smc50mhz>; 808 clock-names = "apb_pclk"; 809 }; 810 811 memory@80000000 { 812 device_type = "memory"; 813 /* last 16MB of the first memory area is reserved for secure world use by firmware */ 814 reg = <0x00000000 0x80000000 0x0 0x7f000000>, 815 <0x00000008 0x80000000 0x1 0x80000000>; 816 }; 817 818 bus@8000000 { 819 #interrupt-cells = <1>; 820 interrupt-map-mask = <0 0 15>; 821 interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 822 <0 0 1 &gic 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 823 <0 0 2 &gic 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 824 <0 0 3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 825 <0 0 4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 826 <0 0 5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 827 <0 0 6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 828 <0 0 7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 829 <0 0 8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 830 <0 0 9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 831 <0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 832 <0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 833 <0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 834 }; 835 836 site2: tlx-bus@60000000 { 837 compatible = "simple-bus"; 838 #address-cells = <1>; 839 #size-cells = <1>; 840 ranges = <0 0 0x60000000 0x10000000>; 841 #interrupt-cells = <1>; 842 interrupt-map-mask = <0 0>; 843 interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 844 }; 845}; 846