1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2017-2020 NXP 7 * 8 * Abhimanyu Saini <abhimanyu.saini@nxp.com> 9 * 10 */ 11 12#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 13#include <dt-bindings/thermal/thermal.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15 16/ { 17 compatible = "fsl,ls2080a"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 crypto = &crypto; 24 rtc1 = &ftm_alarm0; 25 serial0 = &serial0; 26 serial1 = &serial1; 27 serial2 = &serial2; 28 serial3 = &serial3; 29 }; 30 31 cpu: cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 }; 35 36 memory@80000000 { 37 device_type = "memory"; 38 reg = <0x00000000 0x80000000 0 0x80000000>; 39 /* DRAM space - 1, size : 2 GB DRAM */ 40 }; 41 42 sysclk: sysclk { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <100000000>; 46 clock-output-names = "sysclk"; 47 }; 48 49 gic: interrupt-controller@6000000 { 50 compatible = "arm,gic-v3"; 51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ 53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 56 #interrupt-cells = <3>; 57 #address-cells = <2>; 58 #size-cells = <2>; 59 ranges; 60 interrupt-controller; 61 interrupts = <1 9 0x4>; 62 63 its: gic-its@6020000 { 64 compatible = "arm,gic-v3-its"; 65 msi-controller; 66 reg = <0x0 0x6020000 0 0x20000>; 67 }; 68 }; 69 70 rstcr: syscon@1e60000 { 71 compatible = "fsl,ls2080a-rstcr", "syscon"; 72 reg = <0x0 0x1e60000 0x0 0x4>; 73 }; 74 75 reboot { 76 compatible ="syscon-reboot"; 77 regmap = <&rstcr>; 78 offset = <0x0>; 79 mask = <0x2>; 80 }; 81 82 thermal-zones { 83 ddr-controller1 { 84 polling-delay-passive = <1000>; 85 polling-delay = <5000>; 86 thermal-sensors = <&tmu 1>; 87 88 trips { 89 ddr-ctrler1-crit { 90 temperature = <95000>; 91 hysteresis = <2000>; 92 type = "critical"; 93 }; 94 }; 95 }; 96 97 ddr-controller2 { 98 polling-delay-passive = <1000>; 99 polling-delay = <5000>; 100 thermal-sensors = <&tmu 2>; 101 102 trips { 103 ddr-ctrler2-crit { 104 temperature = <95000>; 105 hysteresis = <2000>; 106 type = "critical"; 107 }; 108 }; 109 }; 110 111 ddr-controller3 { 112 polling-delay-passive = <1000>; 113 polling-delay = <5000>; 114 thermal-sensors = <&tmu 3>; 115 116 trips { 117 ddr-ctrler3-crit { 118 temperature = <95000>; 119 hysteresis = <2000>; 120 type = "critical"; 121 }; 122 }; 123 }; 124 125 core-cluster1 { 126 polling-delay-passive = <1000>; 127 polling-delay = <5000>; 128 thermal-sensors = <&tmu 4>; 129 130 trips { 131 core_cluster1_alert: core-cluster1-alert { 132 temperature = <85000>; 133 hysteresis = <2000>; 134 type = "passive"; 135 }; 136 137 core-cluster1-crit { 138 temperature = <95000>; 139 hysteresis = <2000>; 140 type = "critical"; 141 }; 142 }; 143 144 cooling-maps { 145 map0 { 146 trip = <&core_cluster1_alert>; 147 cooling-device = 148 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 149 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 150 }; 151 }; 152 }; 153 154 core-cluster2 { 155 polling-delay-passive = <1000>; 156 polling-delay = <5000>; 157 thermal-sensors = <&tmu 5>; 158 159 trips { 160 core_cluster2_alert: core-cluster2-alert { 161 temperature = <85000>; 162 hysteresis = <2000>; 163 type = "passive"; 164 }; 165 166 core-cluster2-crit { 167 temperature = <95000>; 168 hysteresis = <2000>; 169 type = "critical"; 170 }; 171 }; 172 173 cooling-maps { 174 map0 { 175 trip = <&core_cluster2_alert>; 176 cooling-device = 177 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 178 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 179 }; 180 }; 181 }; 182 183 core-cluster3 { 184 polling-delay-passive = <1000>; 185 polling-delay = <5000>; 186 thermal-sensors = <&tmu 6>; 187 188 trips { 189 core_cluster3_alert: core-cluster3-alert { 190 temperature = <85000>; 191 hysteresis = <2000>; 192 type = "passive"; 193 }; 194 195 core-cluster3-crit { 196 temperature = <95000>; 197 hysteresis = <2000>; 198 type = "critical"; 199 }; 200 }; 201 202 cooling-maps { 203 map0 { 204 trip = <&core_cluster3_alert>; 205 cooling-device = 206 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 207 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 208 }; 209 }; 210 }; 211 212 core-cluster4 { 213 polling-delay-passive = <1000>; 214 polling-delay = <5000>; 215 thermal-sensors = <&tmu 7>; 216 217 trips { 218 core_cluster4_alert: core-cluster4-alert { 219 temperature = <85000>; 220 hysteresis = <2000>; 221 type = "passive"; 222 }; 223 224 core-cluster4-crit { 225 temperature = <95000>; 226 hysteresis = <2000>; 227 type = "critical"; 228 }; 229 }; 230 231 cooling-maps { 232 map0 { 233 trip = <&core_cluster4_alert>; 234 cooling-device = 235 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 236 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 237 }; 238 }; 239 }; 240 }; 241 242 timer { 243 compatible = "arm,armv8-timer"; 244 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ 245 <1 14 4>, /* Physical Non-Secure PPI, active-low */ 246 <1 11 4>, /* Virtual PPI, active-low */ 247 <1 10 4>; /* Hypervisor PPI, active-low */ 248 fsl,erratum-a008585; 249 }; 250 251 pmu { 252 compatible = "arm,armv8-pmuv3"; 253 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ 254 }; 255 256 psci { 257 compatible = "arm,psci-0.2"; 258 method = "smc"; 259 }; 260 261 soc { 262 compatible = "simple-bus"; 263 #address-cells = <2>; 264 #size-cells = <2>; 265 ranges; 266 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 267 268 clockgen: clocking@1300000 { 269 compatible = "fsl,ls2080a-clockgen"; 270 reg = <0 0x1300000 0 0xa0000>; 271 #clock-cells = <2>; 272 clocks = <&sysclk>; 273 }; 274 275 dcfg: dcfg@1e00000 { 276 compatible = "fsl,ls2080a-dcfg", "syscon"; 277 reg = <0x0 0x1e00000 0x0 0x10000>; 278 little-endian; 279 }; 280 281 isc: syscon@1f70000 { 282 compatible = "fsl,ls2080a-isc", "syscon"; 283 reg = <0x0 0x1f70000 0x0 0x10000>; 284 little-endian; 285 #address-cells = <1>; 286 #size-cells = <1>; 287 ranges = <0x0 0x0 0x1f70000 0x10000>; 288 289 extirq: interrupt-controller@14 { 290 compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq"; 291 #interrupt-cells = <2>; 292 #address-cells = <0>; 293 interrupt-controller; 294 reg = <0x14 4>; 295 interrupt-map = 296 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 297 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 298 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 299 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 300 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 301 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 302 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 303 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 304 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 305 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 306 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 307 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 308 interrupt-map-mask = <0xffffffff 0x0>; 309 }; 310 }; 311 312 tmu: tmu@1f80000 { 313 compatible = "fsl,qoriq-tmu"; 314 reg = <0x0 0x1f80000 0x0 0x10000>; 315 interrupts = <0 23 0x4>; 316 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 317 fsl,tmu-calibration = <0x00000000 0x00000026 318 0x00000001 0x0000002d 319 0x00000002 0x00000032 320 0x00000003 0x00000039 321 0x00000004 0x0000003f 322 0x00000005 0x00000046 323 0x00000006 0x0000004d 324 0x00000007 0x00000054 325 0x00000008 0x0000005a 326 0x00000009 0x00000061 327 0x0000000a 0x0000006a 328 0x0000000b 0x00000071 329 330 0x00010000 0x00000025 331 0x00010001 0x0000002c 332 0x00010002 0x00000035 333 0x00010003 0x0000003d 334 0x00010004 0x00000045 335 0x00010005 0x0000004e 336 0x00010006 0x00000057 337 0x00010007 0x00000061 338 0x00010008 0x0000006b 339 0x00010009 0x00000076 340 341 0x00020000 0x00000029 342 0x00020001 0x00000033 343 0x00020002 0x0000003d 344 0x00020003 0x00000049 345 0x00020004 0x00000056 346 0x00020005 0x00000061 347 0x00020006 0x0000006d 348 349 0x00030000 0x00000021 350 0x00030001 0x0000002a 351 0x00030002 0x0000003c 352 0x00030003 0x0000004e>; 353 little-endian; 354 #thermal-sensor-cells = <1>; 355 }; 356 357 serial0: serial@21c0500 { 358 compatible = "fsl,ns16550", "ns16550a"; 359 reg = <0x0 0x21c0500 0x0 0x100>; 360 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 361 QORIQ_CLK_PLL_DIV(4)>; 362 interrupts = <0 32 0x4>; /* Level high type */ 363 }; 364 365 serial1: serial@21c0600 { 366 compatible = "fsl,ns16550", "ns16550a"; 367 reg = <0x0 0x21c0600 0x0 0x100>; 368 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 369 QORIQ_CLK_PLL_DIV(4)>; 370 interrupts = <0 32 0x4>; /* Level high type */ 371 }; 372 373 serial2: serial@21d0500 { 374 compatible = "fsl,ns16550", "ns16550a"; 375 reg = <0x0 0x21d0500 0x0 0x100>; 376 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 377 QORIQ_CLK_PLL_DIV(4)>; 378 interrupts = <0 33 0x4>; /* Level high type */ 379 }; 380 381 serial3: serial@21d0600 { 382 compatible = "fsl,ns16550", "ns16550a"; 383 reg = <0x0 0x21d0600 0x0 0x100>; 384 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 385 QORIQ_CLK_PLL_DIV(4)>; 386 interrupts = <0 33 0x4>; /* Level high type */ 387 }; 388 389 cluster1_core0_watchdog: wdt@c000000 { 390 compatible = "arm,sp805", "arm,primecell"; 391 reg = <0x0 0xc000000 0x0 0x1000>; 392 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 393 QORIQ_CLK_PLL_DIV(4)>, 394 <&clockgen QORIQ_CLK_PLATFORM_PLL 395 QORIQ_CLK_PLL_DIV(4)>; 396 clock-names = "wdog_clk", "apb_pclk"; 397 }; 398 399 cluster1_core1_watchdog: wdt@c010000 { 400 compatible = "arm,sp805", "arm,primecell"; 401 reg = <0x0 0xc010000 0x0 0x1000>; 402 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 403 QORIQ_CLK_PLL_DIV(4)>, 404 <&clockgen QORIQ_CLK_PLATFORM_PLL 405 QORIQ_CLK_PLL_DIV(4)>; 406 clock-names = "wdog_clk", "apb_pclk"; 407 }; 408 409 cluster2_core0_watchdog: wdt@c100000 { 410 compatible = "arm,sp805", "arm,primecell"; 411 reg = <0x0 0xc100000 0x0 0x1000>; 412 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 413 QORIQ_CLK_PLL_DIV(4)>, 414 <&clockgen QORIQ_CLK_PLATFORM_PLL 415 QORIQ_CLK_PLL_DIV(4)>; 416 clock-names = "wdog_clk", "apb_pclk"; 417 }; 418 419 cluster2_core1_watchdog: wdt@c110000 { 420 compatible = "arm,sp805", "arm,primecell"; 421 reg = <0x0 0xc110000 0x0 0x1000>; 422 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 423 QORIQ_CLK_PLL_DIV(4)>, 424 <&clockgen QORIQ_CLK_PLATFORM_PLL 425 QORIQ_CLK_PLL_DIV(4)>; 426 clock-names = "wdog_clk", "apb_pclk"; 427 }; 428 429 cluster3_core0_watchdog: wdt@c200000 { 430 compatible = "arm,sp805", "arm,primecell"; 431 reg = <0x0 0xc200000 0x0 0x1000>; 432 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 433 QORIQ_CLK_PLL_DIV(4)>, 434 <&clockgen QORIQ_CLK_PLATFORM_PLL 435 QORIQ_CLK_PLL_DIV(4)>; 436 clock-names = "wdog_clk", "apb_pclk"; 437 }; 438 439 cluster3_core1_watchdog: wdt@c210000 { 440 compatible = "arm,sp805", "arm,primecell"; 441 reg = <0x0 0xc210000 0x0 0x1000>; 442 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 443 QORIQ_CLK_PLL_DIV(4)>, 444 <&clockgen QORIQ_CLK_PLATFORM_PLL 445 QORIQ_CLK_PLL_DIV(4)>; 446 clock-names = "wdog_clk", "apb_pclk"; 447 }; 448 449 cluster4_core0_watchdog: wdt@c300000 { 450 compatible = "arm,sp805", "arm,primecell"; 451 reg = <0x0 0xc300000 0x0 0x1000>; 452 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 453 QORIQ_CLK_PLL_DIV(4)>, 454 <&clockgen QORIQ_CLK_PLATFORM_PLL 455 QORIQ_CLK_PLL_DIV(4)>; 456 clock-names = "wdog_clk", "apb_pclk"; 457 }; 458 459 cluster4_core1_watchdog: wdt@c310000 { 460 compatible = "arm,sp805", "arm,primecell"; 461 reg = <0x0 0xc310000 0x0 0x1000>; 462 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 463 QORIQ_CLK_PLL_DIV(4)>, 464 <&clockgen QORIQ_CLK_PLATFORM_PLL 465 QORIQ_CLK_PLL_DIV(4)>; 466 clock-names = "wdog_clk", "apb_pclk"; 467 }; 468 469 crypto: crypto@8000000 { 470 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 471 fsl,sec-era = <8>; 472 #address-cells = <1>; 473 #size-cells = <1>; 474 ranges = <0x0 0x00 0x8000000 0x100000>; 475 reg = <0x00 0x8000000 0x0 0x100000>; 476 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 477 dma-coherent; 478 479 sec_jr0: jr@10000 { 480 compatible = "fsl,sec-v5.0-job-ring", 481 "fsl,sec-v4.0-job-ring"; 482 reg = <0x10000 0x10000>; 483 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 484 }; 485 486 sec_jr1: jr@20000 { 487 compatible = "fsl,sec-v5.0-job-ring", 488 "fsl,sec-v4.0-job-ring"; 489 reg = <0x20000 0x10000>; 490 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 491 }; 492 493 sec_jr2: jr@30000 { 494 compatible = "fsl,sec-v5.0-job-ring", 495 "fsl,sec-v4.0-job-ring"; 496 reg = <0x30000 0x10000>; 497 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 498 }; 499 500 sec_jr3: jr@40000 { 501 compatible = "fsl,sec-v5.0-job-ring", 502 "fsl,sec-v4.0-job-ring"; 503 reg = <0x40000 0x10000>; 504 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 505 }; 506 }; 507 508 console@8340020 { 509 compatible = "fsl,dpaa2-console"; 510 reg = <0x00000000 0x08340020 0 0x2>; 511 }; 512 513 ptp-timer@8b95000 { 514 compatible = "fsl,dpaa2-ptp"; 515 reg = <0x0 0x8b95000 0x0 0x100>; 516 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 517 QORIQ_CLK_PLL_DIV(2)>; 518 little-endian; 519 fsl,extts-fifo; 520 }; 521 522 emdio1: mdio@8b96000 { 523 compatible = "fsl,fman-memac-mdio"; 524 reg = <0x0 0x8b96000 0x0 0x1000>; 525 little-endian; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 clock-frequency = <2500000>; 529 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 530 QORIQ_CLK_PLL_DIV(2)>; 531 status = "disabled"; 532 }; 533 534 emdio2: mdio@8b97000 { 535 compatible = "fsl,fman-memac-mdio"; 536 reg = <0x0 0x8b97000 0x0 0x1000>; 537 little-endian; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 clock-frequency = <2500000>; 541 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 542 QORIQ_CLK_PLL_DIV(2)>; 543 status = "disabled"; 544 }; 545 546 pcs_mdio1: mdio@8c07000 { 547 compatible = "fsl,fman-memac-mdio"; 548 reg = <0x0 0x8c07000 0x0 0x1000>; 549 little-endian; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 status = "disabled"; 553 554 pcs1: ethernet-phy@0 { 555 reg = <0>; 556 }; 557 }; 558 559 pcs_mdio2: mdio@8c0b000 { 560 compatible = "fsl,fman-memac-mdio"; 561 reg = <0x0 0x8c0b000 0x0 0x1000>; 562 little-endian; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 status = "disabled"; 566 567 pcs2: ethernet-phy@0 { 568 reg = <0>; 569 }; 570 }; 571 572 pcs_mdio3: mdio@8c0f000 { 573 compatible = "fsl,fman-memac-mdio"; 574 reg = <0x0 0x8c0f000 0x0 0x1000>; 575 little-endian; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 status = "disabled"; 579 580 pcs3: ethernet-phy@0 { 581 reg = <0>; 582 }; 583 }; 584 585 pcs_mdio4: mdio@8c13000 { 586 compatible = "fsl,fman-memac-mdio"; 587 reg = <0x0 0x8c13000 0x0 0x1000>; 588 little-endian; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 status = "disabled"; 592 593 pcs4: ethernet-phy@0 { 594 reg = <0>; 595 }; 596 }; 597 598 pcs_mdio5: mdio@8c17000 { 599 compatible = "fsl,fman-memac-mdio"; 600 reg = <0x0 0x8c17000 0x0 0x1000>; 601 little-endian; 602 #address-cells = <1>; 603 #size-cells = <0>; 604 status = "disabled"; 605 606 pcs5: ethernet-phy@0 { 607 reg = <0>; 608 }; 609 }; 610 611 pcs_mdio6: mdio@8c1b000 { 612 compatible = "fsl,fman-memac-mdio"; 613 reg = <0x0 0x8c1b000 0x0 0x1000>; 614 little-endian; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 status = "disabled"; 618 619 pcs6: ethernet-phy@0 { 620 reg = <0>; 621 }; 622 }; 623 624 pcs_mdio7: mdio@8c1f000 { 625 compatible = "fsl,fman-memac-mdio"; 626 reg = <0x0 0x8c1f000 0x0 0x1000>; 627 little-endian; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 status = "disabled"; 631 632 pcs7: ethernet-phy@0 { 633 reg = <0>; 634 }; 635 }; 636 637 pcs_mdio8: mdio@8c23000 { 638 compatible = "fsl,fman-memac-mdio"; 639 reg = <0x0 0x8c23000 0x0 0x1000>; 640 little-endian; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 status = "disabled"; 644 645 pcs8: ethernet-phy@0 { 646 reg = <0>; 647 }; 648 }; 649 650 pcs_mdio9: mdio@8c27000 { 651 compatible = "fsl,fman-memac-mdio"; 652 reg = <0x0 0x8c27000 0x0 0x1000>; 653 little-endian; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 status = "disabled"; 657 658 pcs9: ethernet-phy@0 { 659 reg = <0>; 660 }; 661 }; 662 663 pcs_mdio10: mdio@8c2b000 { 664 compatible = "fsl,fman-memac-mdio"; 665 reg = <0x0 0x8c2b000 0x0 0x1000>; 666 little-endian; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 status = "disabled"; 670 671 pcs10: ethernet-phy@0 { 672 reg = <0>; 673 }; 674 }; 675 676 pcs_mdio11: mdio@8c2f000 { 677 compatible = "fsl,fman-memac-mdio"; 678 reg = <0x0 0x8c2f000 0x0 0x1000>; 679 little-endian; 680 #address-cells = <1>; 681 #size-cells = <0>; 682 status = "disabled"; 683 684 pcs11: ethernet-phy@0 { 685 reg = <0>; 686 }; 687 }; 688 689 pcs_mdio12: mdio@8c33000 { 690 compatible = "fsl,fman-memac-mdio"; 691 reg = <0x0 0x8c33000 0x0 0x1000>; 692 little-endian; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 status = "disabled"; 696 697 pcs12: ethernet-phy@0 { 698 reg = <0>; 699 }; 700 }; 701 702 pcs_mdio13: mdio@8c37000 { 703 compatible = "fsl,fman-memac-mdio"; 704 reg = <0x0 0x8c37000 0x0 0x1000>; 705 little-endian; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 status = "disabled"; 709 710 pcs13: ethernet-phy@0 { 711 reg = <0>; 712 }; 713 }; 714 715 pcs_mdio14: mdio@8c3b000 { 716 compatible = "fsl,fman-memac-mdio"; 717 reg = <0x0 0x8c3b000 0x0 0x1000>; 718 little-endian; 719 #address-cells = <1>; 720 #size-cells = <0>; 721 status = "disabled"; 722 723 pcs14: ethernet-phy@0 { 724 reg = <0>; 725 }; 726 }; 727 728 pcs_mdio15: mdio@8c3f000 { 729 compatible = "fsl,fman-memac-mdio"; 730 reg = <0x0 0x8c3f000 0x0 0x1000>; 731 little-endian; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 status = "disabled"; 735 736 pcs15: ethernet-phy@0 { 737 reg = <0>; 738 }; 739 }; 740 741 pcs_mdio16: mdio@8c43000 { 742 compatible = "fsl,fman-memac-mdio"; 743 reg = <0x0 0x8c43000 0x0 0x1000>; 744 little-endian; 745 #address-cells = <1>; 746 #size-cells = <0>; 747 status = "disabled"; 748 749 pcs16: ethernet-phy@0 { 750 reg = <0>; 751 }; 752 }; 753 754 fsl_mc: fsl-mc@80c000000 { 755 compatible = "fsl,qoriq-mc"; 756 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 757 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 758 msi-parent = <&its>; 759 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ 760 dma-coherent; 761 #address-cells = <3>; 762 #size-cells = <1>; 763 764 /* 765 * Region type 0x0 - MC portals 766 * Region type 0x1 - QBMAN portals 767 */ 768 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 769 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 770 771 /* 772 * Define the maximum number of MACs present on the SoC. 773 */ 774 dpmacs { 775 #address-cells = <1>; 776 #size-cells = <0>; 777 778 dpmac1: ethernet@1 { 779 compatible = "fsl,qoriq-mc-dpmac"; 780 reg = <0x1>; 781 pcs-handle = <&pcs1>; 782 }; 783 784 dpmac2: ethernet@2 { 785 compatible = "fsl,qoriq-mc-dpmac"; 786 reg = <0x2>; 787 pcs-handle = <&pcs2>; 788 }; 789 790 dpmac3: ethernet@3 { 791 compatible = "fsl,qoriq-mc-dpmac"; 792 reg = <0x3>; 793 pcs-handle = <&pcs3>; 794 }; 795 796 dpmac4: ethernet@4 { 797 compatible = "fsl,qoriq-mc-dpmac"; 798 reg = <0x4>; 799 pcs-handle = <&pcs4>; 800 }; 801 802 dpmac5: ethernet@5 { 803 compatible = "fsl,qoriq-mc-dpmac"; 804 reg = <0x5>; 805 pcs-handle = <&pcs5>; 806 }; 807 808 dpmac6: ethernet@6 { 809 compatible = "fsl,qoriq-mc-dpmac"; 810 reg = <0x6>; 811 pcs-handle = <&pcs6>; 812 }; 813 814 dpmac7: ethernet@7 { 815 compatible = "fsl,qoriq-mc-dpmac"; 816 reg = <0x7>; 817 pcs-handle = <&pcs7>; 818 }; 819 820 dpmac8: ethernet@8 { 821 compatible = "fsl,qoriq-mc-dpmac"; 822 reg = <0x8>; 823 pcs-handle = <&pcs8>; 824 }; 825 826 dpmac9: ethernet@9 { 827 compatible = "fsl,qoriq-mc-dpmac"; 828 reg = <0x9>; 829 pcs-handle = <&pcs9>; 830 }; 831 832 dpmac10: ethernet@a { 833 compatible = "fsl,qoriq-mc-dpmac"; 834 reg = <0xa>; 835 pcs-handle = <&pcs10>; 836 }; 837 838 dpmac11: ethernet@b { 839 compatible = "fsl,qoriq-mc-dpmac"; 840 reg = <0xb>; 841 pcs-handle = <&pcs11>; 842 }; 843 844 dpmac12: ethernet@c { 845 compatible = "fsl,qoriq-mc-dpmac"; 846 reg = <0xc>; 847 pcs-handle = <&pcs12>; 848 }; 849 850 dpmac13: ethernet@d { 851 compatible = "fsl,qoriq-mc-dpmac"; 852 reg = <0xd>; 853 pcs-handle = <&pcs13>; 854 }; 855 856 dpmac14: ethernet@e { 857 compatible = "fsl,qoriq-mc-dpmac"; 858 reg = <0xe>; 859 pcs-handle = <&pcs14>; 860 }; 861 862 dpmac15: ethernet@f { 863 compatible = "fsl,qoriq-mc-dpmac"; 864 reg = <0xf>; 865 pcs-handle = <&pcs15>; 866 }; 867 868 dpmac16: ethernet@10 { 869 compatible = "fsl,qoriq-mc-dpmac"; 870 reg = <0x10>; 871 pcs-handle = <&pcs16>; 872 }; 873 }; 874 }; 875 876 smmu: iommu@5000000 { 877 compatible = "arm,mmu-500"; 878 reg = <0 0x5000000 0 0x800000>; 879 #global-interrupts = <12>; 880 #iommu-cells = <1>; 881 stream-match-mask = <0x7C00>; 882 dma-coherent; 883 interrupts = <0 13 4>, /* global secure fault */ 884 <0 14 4>, /* combined secure interrupt */ 885 <0 15 4>, /* global non-secure fault */ 886 <0 16 4>, /* combined non-secure interrupt */ 887 /* performance counter interrupts 0-7 */ 888 <0 211 4>, <0 212 4>, 889 <0 213 4>, <0 214 4>, 890 <0 215 4>, <0 216 4>, 891 <0 217 4>, <0 218 4>, 892 /* per context interrupt, 64 interrupts */ 893 <0 146 4>, <0 147 4>, 894 <0 148 4>, <0 149 4>, 895 <0 150 4>, <0 151 4>, 896 <0 152 4>, <0 153 4>, 897 <0 154 4>, <0 155 4>, 898 <0 156 4>, <0 157 4>, 899 <0 158 4>, <0 159 4>, 900 <0 160 4>, <0 161 4>, 901 <0 162 4>, <0 163 4>, 902 <0 164 4>, <0 165 4>, 903 <0 166 4>, <0 167 4>, 904 <0 168 4>, <0 169 4>, 905 <0 170 4>, <0 171 4>, 906 <0 172 4>, <0 173 4>, 907 <0 174 4>, <0 175 4>, 908 <0 176 4>, <0 177 4>, 909 <0 178 4>, <0 179 4>, 910 <0 180 4>, <0 181 4>, 911 <0 182 4>, <0 183 4>, 912 <0 184 4>, <0 185 4>, 913 <0 186 4>, <0 187 4>, 914 <0 188 4>, <0 189 4>, 915 <0 190 4>, <0 191 4>, 916 <0 192 4>, <0 193 4>, 917 <0 194 4>, <0 195 4>, 918 <0 196 4>, <0 197 4>, 919 <0 198 4>, <0 199 4>, 920 <0 200 4>, <0 201 4>, 921 <0 202 4>, <0 203 4>, 922 <0 204 4>, <0 205 4>, 923 <0 206 4>, <0 207 4>, 924 <0 208 4>, <0 209 4>; 925 }; 926 927 dspi: spi@2100000 { 928 status = "disabled"; 929 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 reg = <0x0 0x2100000 0x0 0x10000>; 933 interrupts = <0 26 0x4>; /* Level high type */ 934 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 935 QORIQ_CLK_PLL_DIV(4)>; 936 clock-names = "dspi"; 937 spi-num-chipselects = <5>; 938 }; 939 940 esdhc: esdhc@2140000 { 941 status = "disabled"; 942 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; 943 reg = <0x0 0x2140000 0x0 0x10000>; 944 interrupts = <0 28 0x4>; /* Level high type */ 945 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 946 QORIQ_CLK_PLL_DIV(2)>; 947 voltage-ranges = <1800 1800 3300 3300>; 948 sdhci,auto-cmd12; 949 little-endian; 950 bus-width = <4>; 951 }; 952 953 gpio0: gpio@2300000 { 954 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 955 reg = <0x0 0x2300000 0x0 0x10000>; 956 interrupts = <0 36 0x4>; /* Level high type */ 957 gpio-controller; 958 little-endian; 959 #gpio-cells = <2>; 960 interrupt-controller; 961 #interrupt-cells = <2>; 962 }; 963 964 gpio1: gpio@2310000 { 965 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 966 reg = <0x0 0x2310000 0x0 0x10000>; 967 interrupts = <0 36 0x4>; /* Level high type */ 968 gpio-controller; 969 little-endian; 970 #gpio-cells = <2>; 971 interrupt-controller; 972 #interrupt-cells = <2>; 973 }; 974 975 gpio2: gpio@2320000 { 976 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 977 reg = <0x0 0x2320000 0x0 0x10000>; 978 interrupts = <0 37 0x4>; /* Level high type */ 979 gpio-controller; 980 little-endian; 981 #gpio-cells = <2>; 982 interrupt-controller; 983 #interrupt-cells = <2>; 984 }; 985 986 gpio3: gpio@2330000 { 987 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 988 reg = <0x0 0x2330000 0x0 0x10000>; 989 interrupts = <0 37 0x4>; /* Level high type */ 990 gpio-controller; 991 little-endian; 992 #gpio-cells = <2>; 993 interrupt-controller; 994 #interrupt-cells = <2>; 995 }; 996 997 i2c0: i2c@2000000 { 998 status = "disabled"; 999 compatible = "fsl,vf610-i2c"; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 reg = <0x0 0x2000000 0x0 0x10000>; 1003 interrupts = <0 34 0x4>; /* Level high type */ 1004 clock-names = "i2c"; 1005 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1006 QORIQ_CLK_PLL_DIV(4)>; 1007 }; 1008 1009 i2c1: i2c@2010000 { 1010 status = "disabled"; 1011 compatible = "fsl,vf610-i2c"; 1012 #address-cells = <1>; 1013 #size-cells = <0>; 1014 reg = <0x0 0x2010000 0x0 0x10000>; 1015 interrupts = <0 34 0x4>; /* Level high type */ 1016 clock-names = "i2c"; 1017 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1018 QORIQ_CLK_PLL_DIV(4)>; 1019 }; 1020 1021 i2c2: i2c@2020000 { 1022 status = "disabled"; 1023 compatible = "fsl,vf610-i2c"; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 reg = <0x0 0x2020000 0x0 0x10000>; 1027 interrupts = <0 35 0x4>; /* Level high type */ 1028 clock-names = "i2c"; 1029 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1030 QORIQ_CLK_PLL_DIV(4)>; 1031 }; 1032 1033 i2c3: i2c@2030000 { 1034 status = "disabled"; 1035 compatible = "fsl,vf610-i2c"; 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 reg = <0x0 0x2030000 0x0 0x10000>; 1039 interrupts = <0 35 0x4>; /* Level high type */ 1040 clock-names = "i2c"; 1041 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1042 QORIQ_CLK_PLL_DIV(4)>; 1043 }; 1044 1045 ifc: ifc@2240000 { 1046 compatible = "fsl,ifc", "simple-bus"; 1047 reg = <0x0 0x2240000 0x0 0x20000>; 1048 interrupts = <0 21 0x4>; /* Level high type */ 1049 little-endian; 1050 #address-cells = <2>; 1051 #size-cells = <1>; 1052 1053 ranges = <0 0 0x5 0x80000000 0x08000000 1054 2 0 0x5 0x30000000 0x00010000 1055 3 0 0x5 0x20000000 0x00010000>; 1056 }; 1057 1058 qspi: spi@20c0000 { 1059 compatible = "fsl,ls2080a-qspi"; 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 reg = <0x0 0x20c0000 0x0 0x10000>, 1063 <0x0 0x20000000 0x0 0x10000000>; 1064 reg-names = "QuadSPI", "QuadSPI-memory"; 1065 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1066 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1067 QORIQ_CLK_PLL_DIV(4)>, 1068 <&clockgen QORIQ_CLK_PLATFORM_PLL 1069 QORIQ_CLK_PLL_DIV(4)>; 1070 clock-names = "qspi_en", "qspi"; 1071 status = "disabled"; 1072 }; 1073 1074 pcie1: pcie@3400000 { 1075 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; 1076 reg-names = "regs", "config"; 1077 interrupts = <0 108 0x4>; /* Level high type */ 1078 interrupt-names = "intr"; 1079 #address-cells = <3>; 1080 #size-cells = <2>; 1081 device_type = "pci"; 1082 dma-coherent; 1083 num-viewport = <6>; 1084 bus-range = <0x0 0xff>; 1085 msi-parent = <&its>; 1086 #interrupt-cells = <1>; 1087 interrupt-map-mask = <0 0 0 7>; 1088 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, 1089 <0000 0 0 2 &gic 0 0 0 110 4>, 1090 <0000 0 0 3 &gic 0 0 0 111 4>, 1091 <0000 0 0 4 &gic 0 0 0 112 4>; 1092 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1093 status = "disabled"; 1094 }; 1095 1096 pcie2: pcie@3500000 { 1097 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; 1098 reg-names = "regs", "config"; 1099 interrupts = <0 113 0x4>; /* Level high type */ 1100 interrupt-names = "intr"; 1101 #address-cells = <3>; 1102 #size-cells = <2>; 1103 device_type = "pci"; 1104 dma-coherent; 1105 num-viewport = <6>; 1106 bus-range = <0x0 0xff>; 1107 msi-parent = <&its>; 1108 #interrupt-cells = <1>; 1109 interrupt-map-mask = <0 0 0 7>; 1110 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, 1111 <0000 0 0 2 &gic 0 0 0 115 4>, 1112 <0000 0 0 3 &gic 0 0 0 116 4>, 1113 <0000 0 0 4 &gic 0 0 0 117 4>; 1114 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1115 status = "disabled"; 1116 }; 1117 1118 pcie3: pcie@3600000 { 1119 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; 1120 reg-names = "regs", "config"; 1121 interrupts = <0 118 0x4>; /* Level high type */ 1122 interrupt-names = "intr"; 1123 #address-cells = <3>; 1124 #size-cells = <2>; 1125 device_type = "pci"; 1126 dma-coherent; 1127 num-viewport = <256>; 1128 bus-range = <0x0 0xff>; 1129 msi-parent = <&its>; 1130 #interrupt-cells = <1>; 1131 interrupt-map-mask = <0 0 0 7>; 1132 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, 1133 <0000 0 0 2 &gic 0 0 0 120 4>, 1134 <0000 0 0 3 &gic 0 0 0 121 4>, 1135 <0000 0 0 4 &gic 0 0 0 122 4>; 1136 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1137 status = "disabled"; 1138 }; 1139 1140 pcie4: pcie@3700000 { 1141 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; 1142 reg-names = "regs", "config"; 1143 interrupts = <0 123 0x4>; /* Level high type */ 1144 interrupt-names = "intr"; 1145 #address-cells = <3>; 1146 #size-cells = <2>; 1147 device_type = "pci"; 1148 dma-coherent; 1149 num-viewport = <6>; 1150 bus-range = <0x0 0xff>; 1151 msi-parent = <&its>; 1152 #interrupt-cells = <1>; 1153 interrupt-map-mask = <0 0 0 7>; 1154 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, 1155 <0000 0 0 2 &gic 0 0 0 125 4>, 1156 <0000 0 0 3 &gic 0 0 0 126 4>, 1157 <0000 0 0 4 &gic 0 0 0 127 4>; 1158 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1159 status = "disabled"; 1160 }; 1161 1162 sata0: sata@3200000 { 1163 status = "disabled"; 1164 compatible = "fsl,ls2080a-ahci"; 1165 reg = <0x0 0x3200000 0x0 0x10000>; 1166 interrupts = <0 133 0x4>; /* Level high type */ 1167 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1168 QORIQ_CLK_PLL_DIV(4)>; 1169 dma-coherent; 1170 }; 1171 1172 sata1: sata@3210000 { 1173 status = "disabled"; 1174 compatible = "fsl,ls2080a-ahci"; 1175 reg = <0x0 0x3210000 0x0 0x10000>; 1176 interrupts = <0 136 0x4>; /* Level high type */ 1177 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1178 QORIQ_CLK_PLL_DIV(4)>; 1179 dma-coherent; 1180 }; 1181 1182 bus: bus { 1183 #address-cells = <2>; 1184 #size-cells = <2>; 1185 compatible = "simple-bus"; 1186 ranges; 1187 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; 1188 1189 usb0: usb@3100000 { 1190 compatible = "snps,dwc3"; 1191 reg = <0x0 0x3100000 0x0 0x10000>; 1192 interrupts = <0 80 0x4>; /* Level high type */ 1193 dr_mode = "host"; 1194 snps,quirk-frame-length-adjustment = <0x20>; 1195 snps,dis_rxdet_inp3_quirk; 1196 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1197 status = "disabled"; 1198 }; 1199 1200 usb1: usb@3110000 { 1201 compatible = "snps,dwc3"; 1202 reg = <0x0 0x3110000 0x0 0x10000>; 1203 interrupts = <0 81 0x4>; /* Level high type */ 1204 dr_mode = "host"; 1205 snps,quirk-frame-length-adjustment = <0x20>; 1206 snps,dis_rxdet_inp3_quirk; 1207 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1208 status = "disabled"; 1209 }; 1210 }; 1211 1212 ccn@4000000 { 1213 compatible = "arm,ccn-504"; 1214 reg = <0x0 0x04000000 0x0 0x01000000>; 1215 interrupts = <0 12 4>; 1216 }; 1217 1218 rcpm: power-controller@1e34040 { 1219 compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+"; 1220 reg = <0x0 0x1e34040 0x0 0x18>; 1221 #fsl,rcpm-wakeup-cells = <6>; 1222 little-endian; 1223 }; 1224 1225 ftm_alarm0: timer@2800000 { 1226 compatible = "fsl,ls208xa-ftm-alarm"; 1227 reg = <0x0 0x2800000 0x0 0x10000>; 1228 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; 1229 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1230 }; 1231 }; 1232 1233 ddr1: memory-controller@1080000 { 1234 compatible = "fsl,qoriq-memory-controller"; 1235 reg = <0x0 0x1080000 0x0 0x1000>; 1236 interrupts = <0 17 0x4>; 1237 little-endian; 1238 }; 1239 1240 ddr2: memory-controller@1090000 { 1241 compatible = "fsl,qoriq-memory-controller"; 1242 reg = <0x0 0x1090000 0x0 0x1000>; 1243 interrupts = <0 18 0x4>; 1244 little-endian; 1245 }; 1246 1247 firmware { 1248 optee { 1249 compatible = "linaro,optee-tz"; 1250 method = "smc"; 1251 }; 1252 }; 1253}; 1254