1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/gce/mt8183-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8183-larb-port.h> 13#include <dt-bindings/power/mt8183-power.h> 14#include <dt-bindings/reset-controller/mt8183-resets.h> 15#include <dt-bindings/phy/phy.h> 16#include <dt-bindings/thermal/thermal.h> 17#include <dt-bindings/pinctrl/mt8183-pinfunc.h> 18 19/ { 20 compatible = "mediatek,mt8183"; 21 interrupt-parent = <&sysirq>; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 aliases { 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 i2c6 = &i2c6; 33 i2c7 = &i2c7; 34 i2c8 = &i2c8; 35 i2c9 = &i2c9; 36 i2c10 = &i2c10; 37 i2c11 = &i2c11; 38 ovl0 = &ovl0; 39 ovl-2l0 = &ovl_2l0; 40 ovl-2l1 = &ovl_2l1; 41 rdma0 = &rdma0; 42 rdma1 = &rdma1; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu-map { 50 cluster0 { 51 core0 { 52 cpu = <&cpu0>; 53 }; 54 core1 { 55 cpu = <&cpu1>; 56 }; 57 core2 { 58 cpu = <&cpu2>; 59 }; 60 core3 { 61 cpu = <&cpu3>; 62 }; 63 }; 64 65 cluster1 { 66 core0 { 67 cpu = <&cpu4>; 68 }; 69 core1 { 70 cpu = <&cpu5>; 71 }; 72 core2 { 73 cpu = <&cpu6>; 74 }; 75 core3 { 76 cpu = <&cpu7>; 77 }; 78 }; 79 }; 80 81 cpu0: cpu@0 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x000>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <741>; 87 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 88 dynamic-power-coefficient = <84>; 89 #cooling-cells = <2>; 90 }; 91 92 cpu1: cpu@1 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a53"; 95 reg = <0x001>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <741>; 98 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 99 dynamic-power-coefficient = <84>; 100 #cooling-cells = <2>; 101 }; 102 103 cpu2: cpu@2 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a53"; 106 reg = <0x002>; 107 enable-method = "psci"; 108 capacity-dmips-mhz = <741>; 109 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 110 dynamic-power-coefficient = <84>; 111 #cooling-cells = <2>; 112 }; 113 114 cpu3: cpu@3 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a53"; 117 reg = <0x003>; 118 enable-method = "psci"; 119 capacity-dmips-mhz = <741>; 120 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 121 dynamic-power-coefficient = <84>; 122 #cooling-cells = <2>; 123 }; 124 125 cpu4: cpu@100 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a73"; 128 reg = <0x100>; 129 enable-method = "psci"; 130 capacity-dmips-mhz = <1024>; 131 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 132 dynamic-power-coefficient = <211>; 133 #cooling-cells = <2>; 134 }; 135 136 cpu5: cpu@101 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a73"; 139 reg = <0x101>; 140 enable-method = "psci"; 141 capacity-dmips-mhz = <1024>; 142 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 143 dynamic-power-coefficient = <211>; 144 #cooling-cells = <2>; 145 }; 146 147 cpu6: cpu@102 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a73"; 150 reg = <0x102>; 151 enable-method = "psci"; 152 capacity-dmips-mhz = <1024>; 153 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 154 dynamic-power-coefficient = <211>; 155 #cooling-cells = <2>; 156 }; 157 158 cpu7: cpu@103 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a73"; 161 reg = <0x103>; 162 enable-method = "psci"; 163 capacity-dmips-mhz = <1024>; 164 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 165 dynamic-power-coefficient = <211>; 166 #cooling-cells = <2>; 167 }; 168 169 idle-states { 170 entry-method = "psci"; 171 172 CPU_SLEEP: cpu-sleep { 173 compatible = "arm,idle-state"; 174 local-timer-stop; 175 arm,psci-suspend-param = <0x00010001>; 176 entry-latency-us = <200>; 177 exit-latency-us = <200>; 178 min-residency-us = <800>; 179 }; 180 181 CLUSTER_SLEEP0: cluster-sleep-0 { 182 compatible = "arm,idle-state"; 183 local-timer-stop; 184 arm,psci-suspend-param = <0x01010001>; 185 entry-latency-us = <250>; 186 exit-latency-us = <400>; 187 min-residency-us = <1000>; 188 }; 189 CLUSTER_SLEEP1: cluster-sleep-1 { 190 compatible = "arm,idle-state"; 191 local-timer-stop; 192 arm,psci-suspend-param = <0x01010001>; 193 entry-latency-us = <250>; 194 exit-latency-us = <400>; 195 min-residency-us = <1300>; 196 }; 197 }; 198 }; 199 200 gpu_opp_table: opp_table0 { 201 compatible = "operating-points-v2"; 202 opp-shared; 203 204 opp-300000000 { 205 opp-hz = /bits/ 64 <300000000>; 206 opp-microvolt = <625000>, <850000>; 207 }; 208 209 opp-320000000 { 210 opp-hz = /bits/ 64 <320000000>; 211 opp-microvolt = <631250>, <850000>; 212 }; 213 214 opp-340000000 { 215 opp-hz = /bits/ 64 <340000000>; 216 opp-microvolt = <637500>, <850000>; 217 }; 218 219 opp-360000000 { 220 opp-hz = /bits/ 64 <360000000>; 221 opp-microvolt = <643750>, <850000>; 222 }; 223 224 opp-380000000 { 225 opp-hz = /bits/ 64 <380000000>; 226 opp-microvolt = <650000>, <850000>; 227 }; 228 229 opp-400000000 { 230 opp-hz = /bits/ 64 <400000000>; 231 opp-microvolt = <656250>, <850000>; 232 }; 233 234 opp-420000000 { 235 opp-hz = /bits/ 64 <420000000>; 236 opp-microvolt = <662500>, <850000>; 237 }; 238 239 opp-460000000 { 240 opp-hz = /bits/ 64 <460000000>; 241 opp-microvolt = <675000>, <850000>; 242 }; 243 244 opp-500000000 { 245 opp-hz = /bits/ 64 <500000000>; 246 opp-microvolt = <687500>, <850000>; 247 }; 248 249 opp-540000000 { 250 opp-hz = /bits/ 64 <540000000>; 251 opp-microvolt = <700000>, <850000>; 252 }; 253 254 opp-580000000 { 255 opp-hz = /bits/ 64 <580000000>; 256 opp-microvolt = <712500>, <850000>; 257 }; 258 259 opp-620000000 { 260 opp-hz = /bits/ 64 <620000000>; 261 opp-microvolt = <725000>, <850000>; 262 }; 263 264 opp-653000000 { 265 opp-hz = /bits/ 64 <653000000>; 266 opp-microvolt = <743750>, <850000>; 267 }; 268 269 opp-698000000 { 270 opp-hz = /bits/ 64 <698000000>; 271 opp-microvolt = <768750>, <868750>; 272 }; 273 274 opp-743000000 { 275 opp-hz = /bits/ 64 <743000000>; 276 opp-microvolt = <793750>, <893750>; 277 }; 278 279 opp-800000000 { 280 opp-hz = /bits/ 64 <800000000>; 281 opp-microvolt = <825000>, <925000>; 282 }; 283 }; 284 285 pmu-a53 { 286 compatible = "arm,cortex-a53-pmu"; 287 interrupt-parent = <&gic>; 288 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 289 }; 290 291 pmu-a73 { 292 compatible = "arm,cortex-a73-pmu"; 293 interrupt-parent = <&gic>; 294 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 295 }; 296 297 psci { 298 compatible = "arm,psci-1.0"; 299 method = "smc"; 300 }; 301 302 clk13m: fixed-factor-clock-13m { 303 compatible = "fixed-factor-clock"; 304 #clock-cells = <0>; 305 clocks = <&clk26m>; 306 clock-div = <2>; 307 clock-mult = <1>; 308 clock-output-names = "clk13m"; 309 }; 310 311 clk26m: oscillator { 312 compatible = "fixed-clock"; 313 #clock-cells = <0>; 314 clock-frequency = <26000000>; 315 clock-output-names = "clk26m"; 316 }; 317 318 timer { 319 compatible = "arm,armv8-timer"; 320 interrupt-parent = <&gic>; 321 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 322 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 323 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 324 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 325 }; 326 327 soc { 328 #address-cells = <2>; 329 #size-cells = <2>; 330 compatible = "simple-bus"; 331 ranges; 332 333 soc_data: soc_data@8000000 { 334 compatible = "mediatek,mt8183-efuse", 335 "mediatek,efuse"; 336 reg = <0 0x08000000 0 0x0010>; 337 #address-cells = <1>; 338 #size-cells = <1>; 339 status = "disabled"; 340 }; 341 342 gic: interrupt-controller@c000000 { 343 compatible = "arm,gic-v3"; 344 #interrupt-cells = <4>; 345 interrupt-parent = <&gic>; 346 interrupt-controller; 347 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 348 <0 0x0c100000 0 0x200000>, /* GICR */ 349 <0 0x0c400000 0 0x2000>, /* GICC */ 350 <0 0x0c410000 0 0x1000>, /* GICH */ 351 <0 0x0c420000 0 0x2000>; /* GICV */ 352 353 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 354 ppi-partitions { 355 ppi_cluster0: interrupt-partition-0 { 356 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 357 }; 358 ppi_cluster1: interrupt-partition-1 { 359 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 360 }; 361 }; 362 }; 363 364 mcucfg: syscon@c530000 { 365 compatible = "mediatek,mt8183-mcucfg", "syscon"; 366 reg = <0 0x0c530000 0 0x1000>; 367 #clock-cells = <1>; 368 }; 369 370 sysirq: interrupt-controller@c530a80 { 371 compatible = "mediatek,mt8183-sysirq", 372 "mediatek,mt6577-sysirq"; 373 interrupt-controller; 374 #interrupt-cells = <3>; 375 interrupt-parent = <&gic>; 376 reg = <0 0x0c530a80 0 0x50>; 377 }; 378 379 topckgen: syscon@10000000 { 380 compatible = "mediatek,mt8183-topckgen", "syscon"; 381 reg = <0 0x10000000 0 0x1000>; 382 #clock-cells = <1>; 383 }; 384 385 infracfg: syscon@10001000 { 386 compatible = "mediatek,mt8183-infracfg", "syscon"; 387 reg = <0 0x10001000 0 0x1000>; 388 #clock-cells = <1>; 389 #reset-cells = <1>; 390 }; 391 392 pericfg: syscon@10003000 { 393 compatible = "mediatek,mt8183-pericfg", "syscon"; 394 reg = <0 0x10003000 0 0x1000>; 395 #clock-cells = <1>; 396 }; 397 398 pio: pinctrl@10005000 { 399 compatible = "mediatek,mt8183-pinctrl"; 400 reg = <0 0x10005000 0 0x1000>, 401 <0 0x11f20000 0 0x1000>, 402 <0 0x11e80000 0 0x1000>, 403 <0 0x11e70000 0 0x1000>, 404 <0 0x11e90000 0 0x1000>, 405 <0 0x11d30000 0 0x1000>, 406 <0 0x11d20000 0 0x1000>, 407 <0 0x11c50000 0 0x1000>, 408 <0 0x11f30000 0 0x1000>, 409 <0 0x1000b000 0 0x1000>; 410 reg-names = "iocfg0", "iocfg1", "iocfg2", 411 "iocfg3", "iocfg4", "iocfg5", 412 "iocfg6", "iocfg7", "iocfg8", 413 "eint"; 414 gpio-controller; 415 #gpio-cells = <2>; 416 gpio-ranges = <&pio 0 0 192>; 417 interrupt-controller; 418 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 419 #interrupt-cells = <2>; 420 }; 421 422 scpsys: syscon@10006000 { 423 compatible = "syscon", "simple-mfd"; 424 reg = <0 0x10006000 0 0x1000>; 425 #power-domain-cells = <1>; 426 427 /* System Power Manager */ 428 spm: power-controller { 429 compatible = "mediatek,mt8183-power-controller"; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 #power-domain-cells = <1>; 433 434 /* power domain of the SoC */ 435 power-domain@MT8183_POWER_DOMAIN_AUDIO { 436 reg = <MT8183_POWER_DOMAIN_AUDIO>; 437 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 438 <&infracfg CLK_INFRA_AUDIO>, 439 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>; 440 clock-names = "audio", "audio1", "audio2"; 441 #power-domain-cells = <0>; 442 }; 443 444 power-domain@MT8183_POWER_DOMAIN_CONN { 445 reg = <MT8183_POWER_DOMAIN_CONN>; 446 mediatek,infracfg = <&infracfg>; 447 #power-domain-cells = <0>; 448 }; 449 450 power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { 451 reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>; 452 clocks = <&topckgen CLK_TOP_MUX_MFG>; 453 clock-names = "mfg"; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 #power-domain-cells = <1>; 457 458 mfg: power-domain@MT8183_POWER_DOMAIN_MFG { 459 reg = <MT8183_POWER_DOMAIN_MFG>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 #power-domain-cells = <1>; 463 464 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 { 465 reg = <MT8183_POWER_DOMAIN_MFG_CORE0>; 466 #power-domain-cells = <0>; 467 }; 468 469 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 { 470 reg = <MT8183_POWER_DOMAIN_MFG_CORE1>; 471 #power-domain-cells = <0>; 472 }; 473 474 power-domain@MT8183_POWER_DOMAIN_MFG_2D { 475 reg = <MT8183_POWER_DOMAIN_MFG_2D>; 476 mediatek,infracfg = <&infracfg>; 477 #power-domain-cells = <0>; 478 }; 479 }; 480 }; 481 482 power-domain@MT8183_POWER_DOMAIN_DISP { 483 reg = <MT8183_POWER_DOMAIN_DISP>; 484 clocks = <&topckgen CLK_TOP_MUX_MM>, 485 <&mmsys CLK_MM_SMI_COMMON>, 486 <&mmsys CLK_MM_SMI_LARB0>, 487 <&mmsys CLK_MM_SMI_LARB1>, 488 <&mmsys CLK_MM_GALS_COMM0>, 489 <&mmsys CLK_MM_GALS_COMM1>, 490 <&mmsys CLK_MM_GALS_CCU2MM>, 491 <&mmsys CLK_MM_GALS_IPU12MM>, 492 <&mmsys CLK_MM_GALS_IMG2MM>, 493 <&mmsys CLK_MM_GALS_CAM2MM>, 494 <&mmsys CLK_MM_GALS_IPU2MM>; 495 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3", 496 "mm-4", "mm-5", "mm-6", "mm-7", 497 "mm-8", "mm-9"; 498 mediatek,infracfg = <&infracfg>; 499 mediatek,smi = <&smi_common>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 #power-domain-cells = <1>; 503 504 power-domain@MT8183_POWER_DOMAIN_CAM { 505 reg = <MT8183_POWER_DOMAIN_CAM>; 506 clocks = <&topckgen CLK_TOP_MUX_CAM>, 507 <&camsys CLK_CAM_LARB6>, 508 <&camsys CLK_CAM_LARB3>, 509 <&camsys CLK_CAM_SENINF>, 510 <&camsys CLK_CAM_CAMSV0>, 511 <&camsys CLK_CAM_CAMSV1>, 512 <&camsys CLK_CAM_CAMSV2>, 513 <&camsys CLK_CAM_CCU>; 514 clock-names = "cam", "cam-0", "cam-1", 515 "cam-2", "cam-3", "cam-4", 516 "cam-5", "cam-6"; 517 mediatek,infracfg = <&infracfg>; 518 mediatek,smi = <&smi_common>; 519 #power-domain-cells = <0>; 520 }; 521 522 power-domain@MT8183_POWER_DOMAIN_ISP { 523 reg = <MT8183_POWER_DOMAIN_ISP>; 524 clocks = <&topckgen CLK_TOP_MUX_IMG>, 525 <&imgsys CLK_IMG_LARB5>, 526 <&imgsys CLK_IMG_LARB2>; 527 clock-names = "isp", "isp-0", "isp-1"; 528 mediatek,infracfg = <&infracfg>; 529 mediatek,smi = <&smi_common>; 530 #power-domain-cells = <0>; 531 }; 532 533 power-domain@MT8183_POWER_DOMAIN_VDEC { 534 reg = <MT8183_POWER_DOMAIN_VDEC>; 535 mediatek,smi = <&smi_common>; 536 #power-domain-cells = <0>; 537 }; 538 539 power-domain@MT8183_POWER_DOMAIN_VENC { 540 reg = <MT8183_POWER_DOMAIN_VENC>; 541 mediatek,smi = <&smi_common>; 542 #power-domain-cells = <0>; 543 }; 544 545 power-domain@MT8183_POWER_DOMAIN_VPU_TOP { 546 reg = <MT8183_POWER_DOMAIN_VPU_TOP>; 547 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>, 548 <&topckgen CLK_TOP_MUX_DSP>, 549 <&ipu_conn CLK_IPU_CONN_IPU>, 550 <&ipu_conn CLK_IPU_CONN_AHB>, 551 <&ipu_conn CLK_IPU_CONN_AXI>, 552 <&ipu_conn CLK_IPU_CONN_ISP>, 553 <&ipu_conn CLK_IPU_CONN_CAM_ADL>, 554 <&ipu_conn CLK_IPU_CONN_IMG_ADL>; 555 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1", 556 "vpu-2", "vpu-3", "vpu-4", "vpu-5"; 557 mediatek,infracfg = <&infracfg>; 558 mediatek,smi = <&smi_common>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 #power-domain-cells = <1>; 562 563 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 { 564 reg = <MT8183_POWER_DOMAIN_VPU_CORE0>; 565 clocks = <&topckgen CLK_TOP_MUX_DSP1>; 566 clock-names = "vpu2"; 567 mediatek,infracfg = <&infracfg>; 568 #power-domain-cells = <0>; 569 }; 570 571 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 { 572 reg = <MT8183_POWER_DOMAIN_VPU_CORE1>; 573 clocks = <&topckgen CLK_TOP_MUX_DSP2>; 574 clock-names = "vpu3"; 575 mediatek,infracfg = <&infracfg>; 576 #power-domain-cells = <0>; 577 }; 578 }; 579 }; 580 }; 581 }; 582 583 watchdog: watchdog@10007000 { 584 compatible = "mediatek,mt8183-wdt"; 585 reg = <0 0x10007000 0 0x100>; 586 #reset-cells = <1>; 587 }; 588 589 apmixedsys: syscon@1000c000 { 590 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 591 reg = <0 0x1000c000 0 0x1000>; 592 #clock-cells = <1>; 593 }; 594 595 pwrap: pwrap@1000d000 { 596 compatible = "mediatek,mt8183-pwrap"; 597 reg = <0 0x1000d000 0 0x1000>; 598 reg-names = "pwrap"; 599 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 601 <&infracfg CLK_INFRA_PMIC_AP>; 602 clock-names = "spi", "wrap"; 603 }; 604 605 scp: scp@10500000 { 606 compatible = "mediatek,mt8183-scp"; 607 reg = <0 0x10500000 0 0x80000>, 608 <0 0x105c0000 0 0x19080>; 609 reg-names = "sram", "cfg"; 610 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&infracfg CLK_INFRA_SCPSYS>; 612 clock-names = "main"; 613 memory-region = <&scp_mem_reserved>; 614 status = "disabled"; 615 }; 616 617 systimer: timer@10017000 { 618 compatible = "mediatek,mt8183-timer", 619 "mediatek,mt6765-timer"; 620 reg = <0 0x10017000 0 0x1000>; 621 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&clk13m>; 623 }; 624 625 iommu: iommu@10205000 { 626 compatible = "mediatek,mt8183-m4u"; 627 reg = <0 0x10205000 0 0x1000>; 628 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; 629 mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 630 &larb4 &larb5 &larb6>; 631 #iommu-cells = <1>; 632 }; 633 634 gce: mailbox@10238000 { 635 compatible = "mediatek,mt8183-gce"; 636 reg = <0 0x10238000 0 0x4000>; 637 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 638 #mbox-cells = <2>; 639 clocks = <&infracfg CLK_INFRA_GCE>; 640 clock-names = "gce"; 641 }; 642 643 auxadc: auxadc@11001000 { 644 compatible = "mediatek,mt8183-auxadc", 645 "mediatek,mt8173-auxadc"; 646 reg = <0 0x11001000 0 0x1000>; 647 clocks = <&infracfg CLK_INFRA_AUXADC>; 648 clock-names = "main"; 649 #io-channel-cells = <1>; 650 status = "disabled"; 651 }; 652 653 uart0: serial@11002000 { 654 compatible = "mediatek,mt8183-uart", 655 "mediatek,mt6577-uart"; 656 reg = <0 0x11002000 0 0x1000>; 657 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 658 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 659 clock-names = "baud", "bus"; 660 status = "disabled"; 661 }; 662 663 uart1: serial@11003000 { 664 compatible = "mediatek,mt8183-uart", 665 "mediatek,mt6577-uart"; 666 reg = <0 0x11003000 0 0x1000>; 667 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 668 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 669 clock-names = "baud", "bus"; 670 status = "disabled"; 671 }; 672 673 uart2: serial@11004000 { 674 compatible = "mediatek,mt8183-uart", 675 "mediatek,mt6577-uart"; 676 reg = <0 0x11004000 0 0x1000>; 677 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 678 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 679 clock-names = "baud", "bus"; 680 status = "disabled"; 681 }; 682 683 i2c6: i2c@11005000 { 684 compatible = "mediatek,mt8183-i2c"; 685 reg = <0 0x11005000 0 0x1000>, 686 <0 0x11000600 0 0x80>; 687 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 688 clocks = <&infracfg CLK_INFRA_I2C6>, 689 <&infracfg CLK_INFRA_AP_DMA>; 690 clock-names = "main", "dma"; 691 clock-div = <1>; 692 #address-cells = <1>; 693 #size-cells = <0>; 694 status = "disabled"; 695 }; 696 697 i2c0: i2c@11007000 { 698 compatible = "mediatek,mt8183-i2c"; 699 reg = <0 0x11007000 0 0x1000>, 700 <0 0x11000080 0 0x80>; 701 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 702 clocks = <&infracfg CLK_INFRA_I2C0>, 703 <&infracfg CLK_INFRA_AP_DMA>; 704 clock-names = "main", "dma"; 705 clock-div = <1>; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 status = "disabled"; 709 }; 710 711 i2c4: i2c@11008000 { 712 compatible = "mediatek,mt8183-i2c"; 713 reg = <0 0x11008000 0 0x1000>, 714 <0 0x11000100 0 0x80>; 715 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 716 clocks = <&infracfg CLK_INFRA_I2C1>, 717 <&infracfg CLK_INFRA_AP_DMA>, 718 <&infracfg CLK_INFRA_I2C1_ARBITER>; 719 clock-names = "main", "dma","arb"; 720 clock-div = <1>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 status = "disabled"; 724 }; 725 726 i2c2: i2c@11009000 { 727 compatible = "mediatek,mt8183-i2c"; 728 reg = <0 0x11009000 0 0x1000>, 729 <0 0x11000280 0 0x80>; 730 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 731 clocks = <&infracfg CLK_INFRA_I2C2>, 732 <&infracfg CLK_INFRA_AP_DMA>, 733 <&infracfg CLK_INFRA_I2C2_ARBITER>; 734 clock-names = "main", "dma", "arb"; 735 clock-div = <1>; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 status = "disabled"; 739 }; 740 741 spi0: spi@1100a000 { 742 compatible = "mediatek,mt8183-spi"; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 reg = <0 0x1100a000 0 0x1000>; 746 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 747 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 748 <&topckgen CLK_TOP_MUX_SPI>, 749 <&infracfg CLK_INFRA_SPI0>; 750 clock-names = "parent-clk", "sel-clk", "spi-clk"; 751 status = "disabled"; 752 }; 753 754 thermal: thermal@1100b000 { 755 #thermal-sensor-cells = <1>; 756 compatible = "mediatek,mt8183-thermal"; 757 reg = <0 0x1100b000 0 0x1000>; 758 clocks = <&infracfg CLK_INFRA_THERM>, 759 <&infracfg CLK_INFRA_AUXADC>; 760 clock-names = "therm", "auxadc"; 761 resets = <&infracfg MT8183_INFRACFG_AO_THERM_SW_RST>; 762 interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>; 763 mediatek,auxadc = <&auxadc>; 764 mediatek,apmixedsys = <&apmixedsys>; 765 nvmem-cells = <&thermal_calibration>; 766 nvmem-cell-names = "calibration-data"; 767 }; 768 769 pwm0: pwm@1100e000 { 770 compatible = "mediatek,mt8183-disp-pwm"; 771 reg = <0 0x1100e000 0 0x1000>; 772 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 773 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 774 #pwm-cells = <2>; 775 clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, 776 <&infracfg CLK_INFRA_DISP_PWM>; 777 clock-names = "main", "mm"; 778 }; 779 780 pwm1: pwm@11006000 { 781 compatible = "mediatek,mt8183-pwm"; 782 reg = <0 0x11006000 0 0x1000>; 783 #pwm-cells = <2>; 784 clocks = <&infracfg CLK_INFRA_PWM>, 785 <&infracfg CLK_INFRA_PWM_HCLK>, 786 <&infracfg CLK_INFRA_PWM1>, 787 <&infracfg CLK_INFRA_PWM2>, 788 <&infracfg CLK_INFRA_PWM3>, 789 <&infracfg CLK_INFRA_PWM4>; 790 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 791 "pwm4"; 792 }; 793 794 i2c3: i2c@1100f000 { 795 compatible = "mediatek,mt8183-i2c"; 796 reg = <0 0x1100f000 0 0x1000>, 797 <0 0x11000400 0 0x80>; 798 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 799 clocks = <&infracfg CLK_INFRA_I2C3>, 800 <&infracfg CLK_INFRA_AP_DMA>; 801 clock-names = "main", "dma"; 802 clock-div = <1>; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 status = "disabled"; 806 }; 807 808 spi1: spi@11010000 { 809 compatible = "mediatek,mt8183-spi"; 810 #address-cells = <1>; 811 #size-cells = <0>; 812 reg = <0 0x11010000 0 0x1000>; 813 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 814 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 815 <&topckgen CLK_TOP_MUX_SPI>, 816 <&infracfg CLK_INFRA_SPI1>; 817 clock-names = "parent-clk", "sel-clk", "spi-clk"; 818 status = "disabled"; 819 }; 820 821 i2c1: i2c@11011000 { 822 compatible = "mediatek,mt8183-i2c"; 823 reg = <0 0x11011000 0 0x1000>, 824 <0 0x11000480 0 0x80>; 825 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 826 clocks = <&infracfg CLK_INFRA_I2C4>, 827 <&infracfg CLK_INFRA_AP_DMA>; 828 clock-names = "main", "dma"; 829 clock-div = <1>; 830 #address-cells = <1>; 831 #size-cells = <0>; 832 status = "disabled"; 833 }; 834 835 spi2: spi@11012000 { 836 compatible = "mediatek,mt8183-spi"; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 reg = <0 0x11012000 0 0x1000>; 840 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 841 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 842 <&topckgen CLK_TOP_MUX_SPI>, 843 <&infracfg CLK_INFRA_SPI2>; 844 clock-names = "parent-clk", "sel-clk", "spi-clk"; 845 status = "disabled"; 846 }; 847 848 spi3: spi@11013000 { 849 compatible = "mediatek,mt8183-spi"; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 reg = <0 0x11013000 0 0x1000>; 853 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 854 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 855 <&topckgen CLK_TOP_MUX_SPI>, 856 <&infracfg CLK_INFRA_SPI3>; 857 clock-names = "parent-clk", "sel-clk", "spi-clk"; 858 status = "disabled"; 859 }; 860 861 i2c9: i2c@11014000 { 862 compatible = "mediatek,mt8183-i2c"; 863 reg = <0 0x11014000 0 0x1000>, 864 <0 0x11000180 0 0x80>; 865 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 866 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 867 <&infracfg CLK_INFRA_AP_DMA>, 868 <&infracfg CLK_INFRA_I2C1_ARBITER>; 869 clock-names = "main", "dma", "arb"; 870 clock-div = <1>; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 status = "disabled"; 874 }; 875 876 i2c10: i2c@11015000 { 877 compatible = "mediatek,mt8183-i2c"; 878 reg = <0 0x11015000 0 0x1000>, 879 <0 0x11000300 0 0x80>; 880 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 881 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 882 <&infracfg CLK_INFRA_AP_DMA>, 883 <&infracfg CLK_INFRA_I2C2_ARBITER>; 884 clock-names = "main", "dma", "arb"; 885 clock-div = <1>; 886 #address-cells = <1>; 887 #size-cells = <0>; 888 status = "disabled"; 889 }; 890 891 i2c5: i2c@11016000 { 892 compatible = "mediatek,mt8183-i2c"; 893 reg = <0 0x11016000 0 0x1000>, 894 <0 0x11000500 0 0x80>; 895 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 896 clocks = <&infracfg CLK_INFRA_I2C5>, 897 <&infracfg CLK_INFRA_AP_DMA>, 898 <&infracfg CLK_INFRA_I2C5_ARBITER>; 899 clock-names = "main", "dma", "arb"; 900 clock-div = <1>; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 status = "disabled"; 904 }; 905 906 i2c11: i2c@11017000 { 907 compatible = "mediatek,mt8183-i2c"; 908 reg = <0 0x11017000 0 0x1000>, 909 <0 0x11000580 0 0x80>; 910 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 911 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 912 <&infracfg CLK_INFRA_AP_DMA>, 913 <&infracfg CLK_INFRA_I2C5_ARBITER>; 914 clock-names = "main", "dma", "arb"; 915 clock-div = <1>; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 status = "disabled"; 919 }; 920 921 spi4: spi@11018000 { 922 compatible = "mediatek,mt8183-spi"; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 reg = <0 0x11018000 0 0x1000>; 926 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 927 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 928 <&topckgen CLK_TOP_MUX_SPI>, 929 <&infracfg CLK_INFRA_SPI4>; 930 clock-names = "parent-clk", "sel-clk", "spi-clk"; 931 status = "disabled"; 932 }; 933 934 spi5: spi@11019000 { 935 compatible = "mediatek,mt8183-spi"; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 reg = <0 0x11019000 0 0x1000>; 939 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 940 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 941 <&topckgen CLK_TOP_MUX_SPI>, 942 <&infracfg CLK_INFRA_SPI5>; 943 clock-names = "parent-clk", "sel-clk", "spi-clk"; 944 status = "disabled"; 945 }; 946 947 i2c7: i2c@1101a000 { 948 compatible = "mediatek,mt8183-i2c"; 949 reg = <0 0x1101a000 0 0x1000>, 950 <0 0x11000680 0 0x80>; 951 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 952 clocks = <&infracfg CLK_INFRA_I2C7>, 953 <&infracfg CLK_INFRA_AP_DMA>; 954 clock-names = "main", "dma"; 955 clock-div = <1>; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 status = "disabled"; 959 }; 960 961 i2c8: i2c@1101b000 { 962 compatible = "mediatek,mt8183-i2c"; 963 reg = <0 0x1101b000 0 0x1000>, 964 <0 0x11000700 0 0x80>; 965 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 966 clocks = <&infracfg CLK_INFRA_I2C8>, 967 <&infracfg CLK_INFRA_AP_DMA>; 968 clock-names = "main", "dma"; 969 clock-div = <1>; 970 #address-cells = <1>; 971 #size-cells = <0>; 972 status = "disabled"; 973 }; 974 975 ssusb: usb@11201000 { 976 compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; 977 reg = <0 0x11201000 0 0x2e00>, 978 <0 0x11203e00 0 0x0100>; 979 reg-names = "mac", "ippc"; 980 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 981 phys = <&u2port0 PHY_TYPE_USB2>, 982 <&u3port0 PHY_TYPE_USB3>; 983 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 984 <&infracfg CLK_INFRA_USB>; 985 clock-names = "sys_ck", "ref_ck"; 986 mediatek,syscon-wakeup = <&pericfg 0x420 101>; 987 #address-cells = <2>; 988 #size-cells = <2>; 989 ranges; 990 status = "disabled"; 991 992 usb_host: usb@11200000 { 993 compatible = "mediatek,mt8183-xhci", 994 "mediatek,mtk-xhci"; 995 reg = <0 0x11200000 0 0x1000>; 996 reg-names = "mac"; 997 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 998 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 999 <&infracfg CLK_INFRA_USB>; 1000 clock-names = "sys_ck", "ref_ck"; 1001 status = "disabled"; 1002 }; 1003 }; 1004 1005 audiosys: syscon@11220000 { 1006 compatible = "mediatek,mt8183-audiosys", "syscon"; 1007 reg = <0 0x11220000 0 0x1000>; 1008 #clock-cells = <1>; 1009 }; 1010 1011 mmc0: mmc@11230000 { 1012 compatible = "mediatek,mt8183-mmc"; 1013 reg = <0 0x11230000 0 0x1000>, 1014 <0 0x11f50000 0 0x1000>; 1015 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 1016 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, 1017 <&infracfg CLK_INFRA_MSDC0>, 1018 <&infracfg CLK_INFRA_MSDC0_SCK>; 1019 clock-names = "source", "hclk", "source_cg"; 1020 status = "disabled"; 1021 }; 1022 1023 mmc1: mmc@11240000 { 1024 compatible = "mediatek,mt8183-mmc"; 1025 reg = <0 0x11240000 0 0x1000>, 1026 <0 0x11e10000 0 0x1000>; 1027 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 1028 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, 1029 <&infracfg CLK_INFRA_MSDC1>, 1030 <&infracfg CLK_INFRA_MSDC1_SCK>; 1031 clock-names = "source", "hclk", "source_cg"; 1032 status = "disabled"; 1033 }; 1034 1035 mipi_tx0: dsi-phy@11e50000 { 1036 compatible = "mediatek,mt8183-mipi-tx"; 1037 reg = <0 0x11e50000 0 0x1000>; 1038 clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>; 1039 #clock-cells = <0>; 1040 #phy-cells = <0>; 1041 clock-output-names = "mipi_tx0_pll"; 1042 nvmem-cells = <&mipi_tx_calibration>; 1043 nvmem-cell-names = "calibration-data"; 1044 }; 1045 1046 efuse: efuse@11f10000 { 1047 compatible = "mediatek,mt8183-efuse", 1048 "mediatek,efuse"; 1049 reg = <0 0x11f10000 0 0x1000>; 1050 #address-cells = <1>; 1051 #size-cells = <1>; 1052 thermal_calibration: calib@180 { 1053 reg = <0x180 0xc>; 1054 }; 1055 1056 mipi_tx_calibration: calib@190 { 1057 reg = <0x190 0xc>; 1058 }; 1059 }; 1060 1061 u3phy: t-phy@11f40000 { 1062 compatible = "mediatek,mt8183-tphy", 1063 "mediatek,generic-tphy-v2"; 1064 #address-cells = <1>; 1065 #size-cells = <1>; 1066 ranges = <0 0 0x11f40000 0x1000>; 1067 status = "okay"; 1068 1069 u2port0: usb-phy@0 { 1070 reg = <0x0 0x700>; 1071 clocks = <&clk26m>; 1072 clock-names = "ref"; 1073 #phy-cells = <1>; 1074 mediatek,discth = <15>; 1075 status = "okay"; 1076 }; 1077 1078 u3port0: usb-phy@700 { 1079 reg = <0x0700 0x900>; 1080 clocks = <&clk26m>; 1081 clock-names = "ref"; 1082 #phy-cells = <1>; 1083 status = "okay"; 1084 }; 1085 }; 1086 1087 mfgcfg: syscon@13000000 { 1088 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 1089 reg = <0 0x13000000 0 0x1000>; 1090 #clock-cells = <1>; 1091 }; 1092 1093 gpu: gpu@13040000 { 1094 compatible = "mediatek,mt8183-mali", "arm,mali-bifrost"; 1095 reg = <0 0x13040000 0 0x4000>; 1096 interrupts = 1097 <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>, 1098 <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>, 1099 <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>; 1100 interrupt-names = "job", "mmu", "gpu"; 1101 1102 clocks = <&mfgcfg CLK_MFG_BG3D>; 1103 1104 power-domains = 1105 <&spm MT8183_POWER_DOMAIN_MFG_CORE0>, 1106 <&spm MT8183_POWER_DOMAIN_MFG_CORE1>, 1107 <&spm MT8183_POWER_DOMAIN_MFG_2D>; 1108 power-domain-names = "core0", "core1", "core2"; 1109 1110 operating-points-v2 = <&gpu_opp_table>; 1111 }; 1112 1113 mmsys: syscon@14000000 { 1114 compatible = "mediatek,mt8183-mmsys", "syscon"; 1115 reg = <0 0x14000000 0 0x1000>; 1116 #clock-cells = <1>; 1117 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1118 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1119 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1120 }; 1121 1122 ovl0: ovl@14008000 { 1123 compatible = "mediatek,mt8183-disp-ovl"; 1124 reg = <0 0x14008000 0 0x1000>; 1125 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; 1126 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1127 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1128 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1129 mediatek,larb = <&larb0>; 1130 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1131 }; 1132 1133 ovl_2l0: ovl@14009000 { 1134 compatible = "mediatek,mt8183-disp-ovl-2l"; 1135 reg = <0 0x14009000 0 0x1000>; 1136 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; 1137 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1138 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1139 iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; 1140 mediatek,larb = <&larb0>; 1141 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1142 }; 1143 1144 ovl_2l1: ovl@1400a000 { 1145 compatible = "mediatek,mt8183-disp-ovl-2l"; 1146 reg = <0 0x1400a000 0 0x1000>; 1147 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; 1148 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1149 clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; 1150 iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; 1151 mediatek,larb = <&larb0>; 1152 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1153 }; 1154 1155 rdma0: rdma@1400b000 { 1156 compatible = "mediatek,mt8183-disp-rdma"; 1157 reg = <0 0x1400b000 0 0x1000>; 1158 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; 1159 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1160 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1161 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1162 mediatek,larb = <&larb0>; 1163 mediatek,rdma-fifo-size = <5120>; 1164 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1165 }; 1166 1167 rdma1: rdma@1400c000 { 1168 compatible = "mediatek,mt8183-disp-rdma"; 1169 reg = <0 0x1400c000 0 0x1000>; 1170 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 1171 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1172 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1173 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1174 mediatek,larb = <&larb0>; 1175 mediatek,rdma-fifo-size = <2048>; 1176 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1177 }; 1178 1179 color0: color@1400e000 { 1180 compatible = "mediatek,mt8183-disp-color", 1181 "mediatek,mt8173-disp-color"; 1182 reg = <0 0x1400e000 0 0x1000>; 1183 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; 1184 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1185 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1186 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1187 }; 1188 1189 ccorr0: ccorr@1400f000 { 1190 compatible = "mediatek,mt8183-disp-ccorr"; 1191 reg = <0 0x1400f000 0 0x1000>; 1192 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; 1193 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1194 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1195 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1196 }; 1197 1198 aal0: aal@14010000 { 1199 compatible = "mediatek,mt8183-disp-aal", 1200 "mediatek,mt8173-disp-aal"; 1201 reg = <0 0x14010000 0 0x1000>; 1202 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; 1203 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1204 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1205 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1206 }; 1207 1208 gamma0: gamma@14011000 { 1209 compatible = "mediatek,mt8183-disp-gamma"; 1210 reg = <0 0x14011000 0 0x1000>; 1211 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; 1212 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1213 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1214 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1215 }; 1216 1217 dither0: dither@14012000 { 1218 compatible = "mediatek,mt8183-disp-dither"; 1219 reg = <0 0x14012000 0 0x1000>; 1220 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; 1221 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1222 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1223 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 1224 }; 1225 1226 dsi0: dsi@14014000 { 1227 compatible = "mediatek,mt8183-dsi"; 1228 reg = <0 0x14014000 0 0x1000>; 1229 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; 1230 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1231 mediatek,syscon-dsi = <&mmsys 0x140>; 1232 clocks = <&mmsys CLK_MM_DSI0_MM>, 1233 <&mmsys CLK_MM_DSI0_IF>, 1234 <&mipi_tx0>; 1235 clock-names = "engine", "digital", "hs"; 1236 phys = <&mipi_tx0>; 1237 phy-names = "dphy"; 1238 }; 1239 1240 mutex: mutex@14016000 { 1241 compatible = "mediatek,mt8183-disp-mutex"; 1242 reg = <0 0x14016000 0 0x1000>; 1243 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; 1244 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1245 mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>, 1246 <CMDQ_EVENT_MUTEX_STREAM_DONE1>; 1247 }; 1248 1249 larb0: larb@14017000 { 1250 compatible = "mediatek,mt8183-smi-larb"; 1251 reg = <0 0x14017000 0 0x1000>; 1252 mediatek,smi = <&smi_common>; 1253 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1254 <&mmsys CLK_MM_SMI_LARB0>; 1255 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1256 clock-names = "apb", "smi"; 1257 }; 1258 1259 smi_common: smi@14019000 { 1260 compatible = "mediatek,mt8183-smi-common"; 1261 reg = <0 0x14019000 0 0x1000>; 1262 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1263 <&mmsys CLK_MM_SMI_COMMON>, 1264 <&mmsys CLK_MM_GALS_COMM0>, 1265 <&mmsys CLK_MM_GALS_COMM1>; 1266 clock-names = "apb", "smi", "gals0", "gals1"; 1267 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1268 }; 1269 1270 imgsys: syscon@15020000 { 1271 compatible = "mediatek,mt8183-imgsys", "syscon"; 1272 reg = <0 0x15020000 0 0x1000>; 1273 #clock-cells = <1>; 1274 }; 1275 1276 larb5: larb@15021000 { 1277 compatible = "mediatek,mt8183-smi-larb"; 1278 reg = <0 0x15021000 0 0x1000>; 1279 mediatek,smi = <&smi_common>; 1280 clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>, 1281 <&mmsys CLK_MM_GALS_IMG2MM>; 1282 clock-names = "apb", "smi", "gals"; 1283 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1284 }; 1285 1286 larb2: larb@1502f000 { 1287 compatible = "mediatek,mt8183-smi-larb"; 1288 reg = <0 0x1502f000 0 0x1000>; 1289 mediatek,smi = <&smi_common>; 1290 clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>, 1291 <&mmsys CLK_MM_GALS_IPU2MM>; 1292 clock-names = "apb", "smi", "gals"; 1293 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 1294 }; 1295 1296 vdecsys: syscon@16000000 { 1297 compatible = "mediatek,mt8183-vdecsys", "syscon"; 1298 reg = <0 0x16000000 0 0x1000>; 1299 #clock-cells = <1>; 1300 }; 1301 1302 larb1: larb@16010000 { 1303 compatible = "mediatek,mt8183-smi-larb"; 1304 reg = <0 0x16010000 0 0x1000>; 1305 mediatek,smi = <&smi_common>; 1306 clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>; 1307 clock-names = "apb", "smi"; 1308 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; 1309 }; 1310 1311 vencsys: syscon@17000000 { 1312 compatible = "mediatek,mt8183-vencsys", "syscon"; 1313 reg = <0 0x17000000 0 0x1000>; 1314 #clock-cells = <1>; 1315 }; 1316 1317 larb4: larb@17010000 { 1318 compatible = "mediatek,mt8183-smi-larb"; 1319 reg = <0 0x17010000 0 0x1000>; 1320 mediatek,smi = <&smi_common>; 1321 clocks = <&vencsys CLK_VENC_LARB>, 1322 <&vencsys CLK_VENC_LARB>; 1323 clock-names = "apb", "smi"; 1324 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 1325 }; 1326 1327 ipu_conn: syscon@19000000 { 1328 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 1329 reg = <0 0x19000000 0 0x1000>; 1330 #clock-cells = <1>; 1331 }; 1332 1333 ipu_adl: syscon@19010000 { 1334 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 1335 reg = <0 0x19010000 0 0x1000>; 1336 #clock-cells = <1>; 1337 }; 1338 1339 ipu_core0: syscon@19180000 { 1340 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 1341 reg = <0 0x19180000 0 0x1000>; 1342 #clock-cells = <1>; 1343 }; 1344 1345 ipu_core1: syscon@19280000 { 1346 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 1347 reg = <0 0x19280000 0 0x1000>; 1348 #clock-cells = <1>; 1349 }; 1350 1351 camsys: syscon@1a000000 { 1352 compatible = "mediatek,mt8183-camsys", "syscon"; 1353 reg = <0 0x1a000000 0 0x1000>; 1354 #clock-cells = <1>; 1355 }; 1356 1357 larb6: larb@1a001000 { 1358 compatible = "mediatek,mt8183-smi-larb"; 1359 reg = <0 0x1a001000 0 0x1000>; 1360 mediatek,smi = <&smi_common>; 1361 clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>, 1362 <&mmsys CLK_MM_GALS_CAM2MM>; 1363 clock-names = "apb", "smi", "gals"; 1364 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 1365 }; 1366 1367 larb3: larb@1a002000 { 1368 compatible = "mediatek,mt8183-smi-larb"; 1369 reg = <0 0x1a002000 0 0x1000>; 1370 mediatek,smi = <&smi_common>; 1371 clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>, 1372 <&mmsys CLK_MM_GALS_IPU12MM>; 1373 clock-names = "apb", "smi", "gals"; 1374 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 1375 }; 1376 }; 1377 1378 thermal_zones: thermal-zones { 1379 cpu_thermal: cpu-thermal { 1380 polling-delay-passive = <100>; 1381 polling-delay = <500>; 1382 thermal-sensors = <&thermal 0>; 1383 sustainable-power = <5000>; 1384 1385 trips { 1386 threshold: trip-point0 { 1387 temperature = <68000>; 1388 hysteresis = <2000>; 1389 type = "passive"; 1390 }; 1391 1392 target: trip-point1 { 1393 temperature = <80000>; 1394 hysteresis = <2000>; 1395 type = "passive"; 1396 }; 1397 1398 cpu_crit: cpu-crit { 1399 temperature = <115000>; 1400 hysteresis = <2000>; 1401 type = "critical"; 1402 }; 1403 }; 1404 1405 cooling-maps { 1406 map0 { 1407 trip = <&target>; 1408 cooling-device = <&cpu0 1409 THERMAL_NO_LIMIT 1410 THERMAL_NO_LIMIT>, 1411 <&cpu1 1412 THERMAL_NO_LIMIT 1413 THERMAL_NO_LIMIT>, 1414 <&cpu2 1415 THERMAL_NO_LIMIT 1416 THERMAL_NO_LIMIT>, 1417 <&cpu3 1418 THERMAL_NO_LIMIT 1419 THERMAL_NO_LIMIT>; 1420 contribution = <3072>; 1421 }; 1422 map1 { 1423 trip = <&target>; 1424 cooling-device = <&cpu4 1425 THERMAL_NO_LIMIT 1426 THERMAL_NO_LIMIT>, 1427 <&cpu5 1428 THERMAL_NO_LIMIT 1429 THERMAL_NO_LIMIT>, 1430 <&cpu6 1431 THERMAL_NO_LIMIT 1432 THERMAL_NO_LIMIT>, 1433 <&cpu7 1434 THERMAL_NO_LIMIT 1435 THERMAL_NO_LIMIT>; 1436 contribution = <1024>; 1437 }; 1438 }; 1439 }; 1440 1441 /* The tzts1 ~ tzts6 don't need to polling */ 1442 /* The tzts1 ~ tzts6 don't need to thermal throttle */ 1443 1444 tzts1: tzts1 { 1445 polling-delay-passive = <0>; 1446 polling-delay = <0>; 1447 thermal-sensors = <&thermal 1>; 1448 sustainable-power = <5000>; 1449 trips {}; 1450 cooling-maps {}; 1451 }; 1452 1453 tzts2: tzts2 { 1454 polling-delay-passive = <0>; 1455 polling-delay = <0>; 1456 thermal-sensors = <&thermal 2>; 1457 sustainable-power = <5000>; 1458 trips {}; 1459 cooling-maps {}; 1460 }; 1461 1462 tzts3: tzts3 { 1463 polling-delay-passive = <0>; 1464 polling-delay = <0>; 1465 thermal-sensors = <&thermal 3>; 1466 sustainable-power = <5000>; 1467 trips {}; 1468 cooling-maps {}; 1469 }; 1470 1471 tzts4: tzts4 { 1472 polling-delay-passive = <0>; 1473 polling-delay = <0>; 1474 thermal-sensors = <&thermal 4>; 1475 sustainable-power = <5000>; 1476 trips {}; 1477 cooling-maps {}; 1478 }; 1479 1480 tzts5: tzts5 { 1481 polling-delay-passive = <0>; 1482 polling-delay = <0>; 1483 thermal-sensors = <&thermal 5>; 1484 sustainable-power = <5000>; 1485 trips {}; 1486 cooling-maps {}; 1487 }; 1488 1489 tztsABB: tztsABB { 1490 polling-delay-passive = <0>; 1491 polling-delay = <0>; 1492 thermal-sensors = <&thermal 6>; 1493 sustainable-power = <5000>; 1494 trips {}; 1495 cooling-maps {}; 1496 }; 1497 }; 1498}; 1499