1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ6018 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,gcc-ipq6018.h> 10#include <dt-bindings/reset/qcom,gcc-ipq6018.h> 11#include <dt-bindings/clock/qcom,apss-ipq.h> 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&intc>; 17 18 clocks { 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; 21 clock-frequency = <32000>; 22 #clock-cells = <0>; 23 }; 24 25 xo: xo { 26 compatible = "fixed-clock"; 27 clock-frequency = <24000000>; 28 #clock-cells = <0>; 29 }; 30 }; 31 32 cpus: cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 CPU0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a53"; 39 reg = <0x0>; 40 enable-method = "psci"; 41 next-level-cache = <&L2_0>; 42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 43 clock-names = "cpu"; 44 operating-points-v2 = <&cpu_opp_table>; 45 cpu-supply = <&ipq6018_s2>; 46 }; 47 48 CPU1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 enable-method = "psci"; 52 reg = <0x1>; 53 next-level-cache = <&L2_0>; 54 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 55 clock-names = "cpu"; 56 operating-points-v2 = <&cpu_opp_table>; 57 cpu-supply = <&ipq6018_s2>; 58 }; 59 60 CPU2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 enable-method = "psci"; 64 reg = <0x2>; 65 next-level-cache = <&L2_0>; 66 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 67 clock-names = "cpu"; 68 operating-points-v2 = <&cpu_opp_table>; 69 cpu-supply = <&ipq6018_s2>; 70 }; 71 72 CPU3: cpu@3 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 enable-method = "psci"; 76 reg = <0x3>; 77 next-level-cache = <&L2_0>; 78 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 79 clock-names = "cpu"; 80 operating-points-v2 = <&cpu_opp_table>; 81 cpu-supply = <&ipq6018_s2>; 82 }; 83 84 L2_0: l2-cache { 85 compatible = "cache"; 86 cache-level = <0x2>; 87 }; 88 }; 89 90 cpu_opp_table: cpu_opp_table { 91 compatible = "operating-points-v2"; 92 opp-shared; 93 94 opp-864000000 { 95 opp-hz = /bits/ 64 <864000000>; 96 opp-microvolt = <725000>; 97 clock-latency-ns = <200000>; 98 }; 99 opp-1056000000 { 100 opp-hz = /bits/ 64 <1056000000>; 101 opp-microvolt = <787500>; 102 clock-latency-ns = <200000>; 103 }; 104 opp-1320000000 { 105 opp-hz = /bits/ 64 <1320000000>; 106 opp-microvolt = <862500>; 107 clock-latency-ns = <200000>; 108 }; 109 opp-1440000000 { 110 opp-hz = /bits/ 64 <1440000000>; 111 opp-microvolt = <925000>; 112 clock-latency-ns = <200000>; 113 }; 114 opp-1608000000 { 115 opp-hz = /bits/ 64 <1608000000>; 116 opp-microvolt = <987500>; 117 clock-latency-ns = <200000>; 118 }; 119 opp-1800000000 { 120 opp-hz = /bits/ 64 <1800000000>; 121 opp-microvolt = <1062500>; 122 clock-latency-ns = <200000>; 123 }; 124 }; 125 126 firmware { 127 scm { 128 compatible = "qcom,scm"; 129 }; 130 }; 131 132 pmuv8: pmu { 133 compatible = "arm,cortex-a53-pmu"; 134 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 135 IRQ_TYPE_LEVEL_HIGH)>; 136 }; 137 138 psci: psci { 139 compatible = "arm,psci-1.0"; 140 method = "smc"; 141 }; 142 143 reserved-memory { 144 #address-cells = <2>; 145 #size-cells = <2>; 146 ranges; 147 148 rpm_msg_ram: memory@60000 { 149 reg = <0x0 0x60000 0x0 0x6000>; 150 no-map; 151 }; 152 153 tz: memory@4a600000 { 154 reg = <0x0 0x4a600000 0x0 0x00400000>; 155 no-map; 156 }; 157 158 smem_region: memory@4aa00000 { 159 reg = <0x0 0x4aa00000 0x0 0x00100000>; 160 no-map; 161 }; 162 163 q6_region: memory@4ab00000 { 164 reg = <0x0 0x4ab00000 0x0 0x05500000>; 165 no-map; 166 }; 167 }; 168 169 smem { 170 compatible = "qcom,smem"; 171 memory-region = <&smem_region>; 172 hwlocks = <&tcsr_mutex 3>; 173 }; 174 175 soc: soc { 176 #address-cells = <2>; 177 #size-cells = <2>; 178 ranges = <0 0 0 0 0x0 0xffffffff>; 179 dma-ranges; 180 compatible = "simple-bus"; 181 182 prng: qrng@e1000 { 183 compatible = "qcom,prng-ee"; 184 reg = <0x0 0xe3000 0x0 0x1000>; 185 clocks = <&gcc GCC_PRNG_AHB_CLK>; 186 clock-names = "core"; 187 }; 188 189 cryptobam: dma-controller@704000 { 190 compatible = "qcom,bam-v1.7.0"; 191 reg = <0x0 0x00704000 0x0 0x20000>; 192 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 194 clock-names = "bam_clk"; 195 #dma-cells = <1>; 196 qcom,ee = <1>; 197 qcom,controlled-remotely; 198 qcom,config-pipe-trust-reg = <0>; 199 }; 200 201 crypto: crypto@73a000 { 202 compatible = "qcom,crypto-v5.1"; 203 reg = <0x0 0x0073a000 0x0 0x6000>; 204 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 205 <&gcc GCC_CRYPTO_AXI_CLK>, 206 <&gcc GCC_CRYPTO_CLK>; 207 clock-names = "iface", "bus", "core"; 208 dmas = <&cryptobam 2>, <&cryptobam 3>; 209 dma-names = "rx", "tx"; 210 }; 211 212 tlmm: pinctrl@1000000 { 213 compatible = "qcom,ipq6018-pinctrl"; 214 reg = <0x0 0x01000000 0x0 0x300000>; 215 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 216 gpio-controller; 217 #gpio-cells = <2>; 218 gpio-ranges = <&tlmm 0 0 80>; 219 interrupt-controller; 220 #interrupt-cells = <2>; 221 222 serial_3_pins: serial3-pinmux { 223 pins = "gpio44", "gpio45"; 224 function = "blsp2_uart"; 225 drive-strength = <8>; 226 bias-pull-down; 227 }; 228 229 qpic_pins: qpic-pins { 230 pins = "gpio1", "gpio3", "gpio4", 231 "gpio5", "gpio6", "gpio7", 232 "gpio8", "gpio10", "gpio11", 233 "gpio12", "gpio13", "gpio14", 234 "gpio15", "gpio17"; 235 function = "qpic_pad"; 236 drive-strength = <8>; 237 bias-disable; 238 }; 239 }; 240 241 gcc: gcc@1800000 { 242 compatible = "qcom,gcc-ipq6018"; 243 reg = <0x0 0x01800000 0x0 0x80000>; 244 clocks = <&xo>, <&sleep_clk>; 245 clock-names = "xo", "sleep_clk"; 246 #clock-cells = <1>; 247 #reset-cells = <1>; 248 }; 249 250 tcsr_mutex: hwlock@1905000 { 251 compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex"; 252 reg = <0x0 0x01905000 0x0 0x20000>; 253 #hwlock-cells = <1>; 254 }; 255 256 tcsr: syscon@1937000 { 257 compatible = "syscon"; 258 reg = <0x0 0x01937000 0x0 0x21000>; 259 }; 260 261 blsp_dma: dma-controller@7884000 { 262 compatible = "qcom,bam-v1.7.0"; 263 reg = <0x0 0x07884000 0x0 0x2b000>; 264 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 266 clock-names = "bam_clk"; 267 #dma-cells = <1>; 268 qcom,ee = <0>; 269 }; 270 271 blsp1_uart3: serial@78b1000 { 272 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 273 reg = <0x0 0x078b1000 0x0 0x200>; 274 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 276 <&gcc GCC_BLSP1_AHB_CLK>; 277 clock-names = "core", "iface"; 278 status = "disabled"; 279 }; 280 281 spi_0: spi@78b5000 { 282 compatible = "qcom,spi-qup-v2.2.1"; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 reg = <0x0 0x078b5000 0x0 0x600>; 286 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 287 spi-max-frequency = <50000000>; 288 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 289 <&gcc GCC_BLSP1_AHB_CLK>; 290 clock-names = "core", "iface"; 291 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 292 dma-names = "tx", "rx"; 293 status = "disabled"; 294 }; 295 296 spi_1: spi@78b6000 { 297 compatible = "qcom,spi-qup-v2.2.1"; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 reg = <0x0 0x078b6000 0x0 0x600>; 301 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 302 spi-max-frequency = <50000000>; 303 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 304 <&gcc GCC_BLSP1_AHB_CLK>; 305 clock-names = "core", "iface"; 306 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 307 dma-names = "tx", "rx"; 308 status = "disabled"; 309 }; 310 311 i2c_0: i2c@78b6000 { 312 compatible = "qcom,i2c-qup-v2.2.1"; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 reg = <0x0 0x078b6000 0x0 0x600>; 316 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 318 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 319 clock-names = "iface", "core"; 320 clock-frequency = <400000>; 321 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 322 dma-names = "rx", "tx"; 323 status = "disabled"; 324 }; 325 326 i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */ 327 compatible = "qcom,i2c-qup-v2.2.1"; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 reg = <0x0 0x078b7000 0x0 0x600>; 331 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 333 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 334 clock-names = "iface", "core"; 335 clock-frequency = <400000>; 336 dmas = <&blsp_dma 17>, <&blsp_dma 16>; 337 dma-names = "rx", "tx"; 338 status = "disabled"; 339 }; 340 341 qpic_bam: dma-controller@7984000 { 342 compatible = "qcom,bam-v1.7.0"; 343 reg = <0x0 0x07984000 0x0 0x1a000>; 344 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&gcc GCC_QPIC_CLK>, 346 <&gcc GCC_QPIC_AHB_CLK>; 347 clock-names = "iface_clk", "bam_clk"; 348 #dma-cells = <1>; 349 qcom,ee = <0>; 350 status = "disabled"; 351 }; 352 353 qpic_nand: nand@79b0000 { 354 compatible = "qcom,ipq6018-nand"; 355 reg = <0x0 0x079b0000 0x0 0x10000>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 clocks = <&gcc GCC_QPIC_CLK>, 359 <&gcc GCC_QPIC_AHB_CLK>; 360 clock-names = "core", "aon"; 361 362 dmas = <&qpic_bam 0>, 363 <&qpic_bam 1>, 364 <&qpic_bam 2>; 365 dma-names = "tx", "rx", "cmd"; 366 pinctrl-0 = <&qpic_pins>; 367 pinctrl-names = "default"; 368 status = "disabled"; 369 }; 370 371 intc: interrupt-controller@b000000 { 372 compatible = "qcom,msm-qgic2"; 373 interrupt-controller; 374 #interrupt-cells = <0x3>; 375 reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ 376 <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ 377 <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ 378 <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ 379 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 380 }; 381 382 pcie_phy: phy@84000 { 383 compatible = "qcom,ipq6018-qmp-pcie-phy"; 384 reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */ 385 status = "disabled"; 386 #address-cells = <2>; 387 #size-cells = <2>; 388 ranges; 389 390 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 391 <&gcc GCC_PCIE0_AHB_CLK>; 392 clock-names = "aux", "cfg_ahb"; 393 394 resets = <&gcc GCC_PCIE0_PHY_BCR>, 395 <&gcc GCC_PCIE0PHY_PHY_BCR>; 396 reset-names = "phy", 397 "common"; 398 399 pcie_phy0: phy@84200 { 400 reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */ 401 <0x0 0x84400 0x0 0x200>, /* Serdes Rx */ 402 <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */ 403 #phy-cells = <0>; 404 405 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 406 clock-names = "pipe0"; 407 clock-output-names = "gcc_pcie0_pipe_clk_src"; 408 #clock-cells = <0>; 409 }; 410 }; 411 412 pcie0: pci@20000000 { 413 compatible = "qcom,pcie-ipq6018"; 414 reg = <0x0 0x20000000 0x0 0xf1d>, 415 <0x0 0x20000f20 0x0 0xa8>, 416 <0x0 0x20001000 0x0 0x1000>, 417 <0x0 0x80000 0x0 0x4000>, 418 <0x0 0x20100000 0x0 0x1000>; 419 reg-names = "dbi", "elbi", "atu", "parf", "config"; 420 421 device_type = "pci"; 422 linux,pci-domain = <0>; 423 bus-range = <0x00 0xff>; 424 num-lanes = <1>; 425 #address-cells = <3>; 426 #size-cells = <2>; 427 428 phys = <&pcie_phy0>; 429 phy-names = "pciephy"; 430 431 ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>, 432 <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>; 433 434 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 435 interrupt-names = "msi"; 436 437 #interrupt-cells = <1>; 438 interrupt-map-mask = <0 0 0 0x7>; 439 interrupt-map = <0 0 0 1 &intc 0 75 440 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 441 <0 0 0 2 &intc 0 78 442 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 443 <0 0 0 3 &intc 0 79 444 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 445 <0 0 0 4 &intc 0 83 446 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 447 448 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 449 <&gcc GCC_PCIE0_AXI_M_CLK>, 450 <&gcc GCC_PCIE0_AXI_S_CLK>, 451 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 452 <&gcc PCIE0_RCHNG_CLK>; 453 clock-names = "iface", 454 "axi_m", 455 "axi_s", 456 "axi_bridge", 457 "rchng"; 458 459 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 460 <&gcc GCC_PCIE0_SLEEP_ARES>, 461 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 462 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 463 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 464 <&gcc GCC_PCIE0_AHB_ARES>, 465 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 466 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 467 reset-names = "pipe", 468 "sleep", 469 "sticky", 470 "axi_m", 471 "axi_s", 472 "ahb", 473 "axi_m_sticky", 474 "axi_s_sticky"; 475 476 status = "disabled"; 477 }; 478 479 watchdog@b017000 { 480 compatible = "qcom,kpss-wdt"; 481 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 482 reg = <0x0 0x0b017000 0x0 0x40>; 483 clocks = <&sleep_clk>; 484 timeout-sec = <10>; 485 }; 486 487 apcs_glb: mailbox@b111000 { 488 compatible = "qcom,ipq6018-apcs-apps-global"; 489 reg = <0x0 0x0b111000 0x0 0x1000>; 490 #clock-cells = <1>; 491 clocks = <&a53pll>, <&xo>; 492 clock-names = "pll", "xo"; 493 #mbox-cells = <1>; 494 }; 495 496 a53pll: clock@b116000 { 497 compatible = "qcom,ipq6018-a53pll"; 498 reg = <0x0 0x0b116000 0x0 0x40>; 499 #clock-cells = <0>; 500 clocks = <&xo>; 501 clock-names = "xo"; 502 }; 503 504 timer { 505 compatible = "arm,armv8-timer"; 506 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 507 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 508 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 509 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 510 }; 511 512 timer@b120000 { 513 #address-cells = <2>; 514 #size-cells = <2>; 515 ranges; 516 compatible = "arm,armv7-timer-mem"; 517 reg = <0x0 0x0b120000 0x0 0x1000>; 518 clock-frequency = <19200000>; 519 520 frame@b120000 { 521 frame-number = <0>; 522 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 524 reg = <0x0 0x0b121000 0x0 0x1000>, 525 <0x0 0x0b122000 0x0 0x1000>; 526 }; 527 528 frame@b123000 { 529 frame-number = <1>; 530 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 531 reg = <0x0 0xb123000 0x0 0x1000>; 532 status = "disabled"; 533 }; 534 535 frame@b124000 { 536 frame-number = <2>; 537 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 538 reg = <0x0 0x0b124000 0x0 0x1000>; 539 status = "disabled"; 540 }; 541 542 frame@b125000 { 543 frame-number = <3>; 544 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 545 reg = <0x0 0x0b125000 0x0 0x1000>; 546 status = "disabled"; 547 }; 548 549 frame@b126000 { 550 frame-number = <4>; 551 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 552 reg = <0x0 0x0b126000 0x0 0x1000>; 553 status = "disabled"; 554 }; 555 556 frame@b127000 { 557 frame-number = <5>; 558 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 559 reg = <0x0 0x0b127000 0x0 0x1000>; 560 status = "disabled"; 561 }; 562 563 frame@b128000 { 564 frame-number = <6>; 565 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 566 reg = <0x0 0x0b128000 0x0 0x1000>; 567 status = "disabled"; 568 }; 569 }; 570 571 q6v5_wcss: remoteproc@cd00000 { 572 compatible = "qcom,ipq6018-wcss-pil"; 573 reg = <0x0 0x0cd00000 0x0 0x4040>, 574 <0x0 0x004ab000 0x0 0x20>; 575 reg-names = "qdsp6", 576 "rmb"; 577 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 578 <&wcss_smp2p_in 0 0>, 579 <&wcss_smp2p_in 1 0>, 580 <&wcss_smp2p_in 2 0>, 581 <&wcss_smp2p_in 3 0>; 582 interrupt-names = "wdog", 583 "fatal", 584 "ready", 585 "handover", 586 "stop-ack"; 587 588 resets = <&gcc GCC_WCSSAON_RESET>, 589 <&gcc GCC_WCSS_BCR>, 590 <&gcc GCC_WCSS_Q6_BCR>; 591 592 reset-names = "wcss_aon_reset", 593 "wcss_reset", 594 "wcss_q6_reset"; 595 596 clocks = <&gcc GCC_PRNG_AHB_CLK>; 597 clock-names = "prng"; 598 599 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>; 600 601 qcom,smem-states = <&wcss_smp2p_out 0>, 602 <&wcss_smp2p_out 1>; 603 qcom,smem-state-names = "shutdown", 604 "stop"; 605 606 memory-region = <&q6_region>; 607 608 glink-edge { 609 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>; 610 qcom,remote-pid = <1>; 611 mboxes = <&apcs_glb 8>; 612 613 qrtr_requests { 614 qcom,glink-channels = "IPCRTR"; 615 }; 616 }; 617 }; 618 619 qusb_phy_1: qusb@59000 { 620 compatible = "qcom,ipq6018-qusb2-phy"; 621 reg = <0x0 0x059000 0x0 0x180>; 622 #phy-cells = <0>; 623 624 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 625 <&xo>; 626 clock-names = "cfg_ahb", "ref"; 627 628 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 629 status = "disabled"; 630 }; 631 632 usb2: usb2@7000000 { 633 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; 634 reg = <0x0 0x070F8800 0x0 0x400>; 635 #address-cells = <2>; 636 #size-cells = <2>; 637 ranges; 638 clocks = <&gcc GCC_USB1_MASTER_CLK>, 639 <&gcc GCC_USB1_SLEEP_CLK>, 640 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 641 clock-names = "master", 642 "sleep", 643 "mock_utmi"; 644 645 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, 646 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 647 assigned-clock-rates = <133330000>, 648 <24000000>; 649 resets = <&gcc GCC_USB1_BCR>; 650 status = "disabled"; 651 652 dwc_1: usb@7000000 { 653 compatible = "snps,dwc3"; 654 reg = <0x0 0x7000000 0x0 0xcd00>; 655 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 656 phys = <&qusb_phy_1>; 657 phy-names = "usb2-phy"; 658 tx-fifo-resize; 659 snps,is-utmi-l1-suspend; 660 snps,hird-threshold = /bits/ 8 <0x0>; 661 snps,dis_u2_susphy_quirk; 662 snps,dis_u3_susphy_quirk; 663 dr_mode = "host"; 664 }; 665 }; 666 667 }; 668 669 wcss: wcss-smp2p { 670 compatible = "qcom,smp2p"; 671 qcom,smem = <435>, <428>; 672 673 interrupt-parent = <&intc>; 674 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>; 675 676 mboxes = <&apcs_glb 9>; 677 678 qcom,local-pid = <0>; 679 qcom,remote-pid = <1>; 680 681 wcss_smp2p_out: master-kernel { 682 qcom,entry-name = "master-kernel"; 683 #qcom,smem-state-cells = <1>; 684 }; 685 686 wcss_smp2p_in: slave-kernel { 687 qcom,entry-name = "slave-kernel"; 688 interrupt-controller; 689 #interrupt-cells = <2>; 690 }; 691 }; 692 693 rpm-glink { 694 compatible = "qcom,glink-rpm"; 695 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 696 qcom,rpm-msg-ram = <&rpm_msg_ram>; 697 mboxes = <&apcs_glb 0>; 698 699 rpm_requests: glink-channel { 700 compatible = "qcom,rpm-ipq6018"; 701 qcom,glink-channels = "rpm_requests"; 702 703 regulators { 704 compatible = "qcom,rpm-mp5496-regulators"; 705 706 ipq6018_s2: s2 { 707 regulator-min-microvolt = <725000>; 708 regulator-max-microvolt = <1062500>; 709 regulator-always-on; 710 }; 711 }; 712 }; 713 }; 714}; 715