1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 8 9/ { 10 model = "Qualcomm Technologies, Inc. IPQ8074"; 11 compatible = "qcom,ipq8074"; 12 13 clocks { 14 sleep_clk: sleep_clk { 15 compatible = "fixed-clock"; 16 clock-frequency = <32768>; 17 #clock-cells = <0>; 18 }; 19 20 xo: xo { 21 compatible = "fixed-clock"; 22 clock-frequency = <19200000>; 23 #clock-cells = <0>; 24 }; 25 }; 26 27 cpus { 28 #address-cells = <0x1>; 29 #size-cells = <0x0>; 30 31 CPU0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a53"; 34 reg = <0x0>; 35 next-level-cache = <&L2_0>; 36 enable-method = "psci"; 37 }; 38 39 CPU1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 enable-method = "psci"; 43 reg = <0x1>; 44 next-level-cache = <&L2_0>; 45 }; 46 47 CPU2: cpu@2 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a53"; 50 enable-method = "psci"; 51 reg = <0x2>; 52 next-level-cache = <&L2_0>; 53 }; 54 55 CPU3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a53"; 58 enable-method = "psci"; 59 reg = <0x3>; 60 next-level-cache = <&L2_0>; 61 }; 62 63 L2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <0x2>; 66 }; 67 }; 68 69 pmu { 70 compatible = "arm,cortex-a53-pmu"; 71 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 72 }; 73 74 psci { 75 compatible = "arm,psci-1.0"; 76 method = "smc"; 77 }; 78 79 firmware { 80 scm { 81 compatible = "qcom,scm-ipq8074", "qcom,scm"; 82 }; 83 }; 84 85 soc: soc { 86 #address-cells = <0x1>; 87 #size-cells = <0x1>; 88 ranges = <0 0 0 0xffffffff>; 89 compatible = "simple-bus"; 90 91 ssphy_1: phy@58000 { 92 compatible = "qcom,ipq8074-qmp-usb3-phy"; 93 reg = <0x00058000 0x1c4>; 94 #clock-cells = <1>; 95 #address-cells = <1>; 96 #size-cells = <1>; 97 ranges; 98 99 clocks = <&gcc GCC_USB1_AUX_CLK>, 100 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 101 <&xo>; 102 clock-names = "aux", "cfg_ahb", "ref"; 103 104 resets = <&gcc GCC_USB1_PHY_BCR>, 105 <&gcc GCC_USB3PHY_1_PHY_BCR>; 106 reset-names = "phy","common"; 107 status = "disabled"; 108 109 usb1_ssphy: phy@58200 { 110 reg = <0x00058200 0x130>, /* Tx */ 111 <0x00058400 0x200>, /* Rx */ 112 <0x00058800 0x1f8>, /* PCS */ 113 <0x00058600 0x044>; /* PCS misc*/ 114 #phy-cells = <0>; 115 clocks = <&gcc GCC_USB1_PIPE_CLK>; 116 clock-names = "pipe0"; 117 clock-output-names = "usb3phy_1_cc_pipe_clk"; 118 }; 119 }; 120 121 qusb_phy_1: phy@59000 { 122 compatible = "qcom,ipq8074-qusb2-phy"; 123 reg = <0x00059000 0x180>; 124 #phy-cells = <0>; 125 126 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 127 <&xo>; 128 clock-names = "cfg_ahb", "ref"; 129 130 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 131 status = "disabled"; 132 }; 133 134 ssphy_0: phy@78000 { 135 compatible = "qcom,ipq8074-qmp-usb3-phy"; 136 reg = <0x00078000 0x1c4>; 137 #clock-cells = <1>; 138 #address-cells = <1>; 139 #size-cells = <1>; 140 ranges; 141 142 clocks = <&gcc GCC_USB0_AUX_CLK>, 143 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 144 <&xo>; 145 clock-names = "aux", "cfg_ahb", "ref"; 146 147 resets = <&gcc GCC_USB0_PHY_BCR>, 148 <&gcc GCC_USB3PHY_0_PHY_BCR>; 149 reset-names = "phy","common"; 150 status = "disabled"; 151 152 usb0_ssphy: phy@78200 { 153 reg = <0x00078200 0x130>, /* Tx */ 154 <0x00078400 0x200>, /* Rx */ 155 <0x00078800 0x1f8>, /* PCS */ 156 <0x00078600 0x044>; /* PCS misc*/ 157 #phy-cells = <0>; 158 clocks = <&gcc GCC_USB0_PIPE_CLK>; 159 clock-names = "pipe0"; 160 clock-output-names = "usb3phy_0_cc_pipe_clk"; 161 }; 162 }; 163 164 qusb_phy_0: phy@79000 { 165 compatible = "qcom,ipq8074-qusb2-phy"; 166 reg = <0x00079000 0x180>; 167 #phy-cells = <0>; 168 169 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 170 <&xo>; 171 clock-names = "cfg_ahb", "ref"; 172 173 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 174 status = "disabled"; 175 }; 176 177 pcie_qmp0: phy@84000 { 178 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; 179 reg = <0x00084000 0x1bc>; 180 #address-cells = <1>; 181 #size-cells = <1>; 182 ranges; 183 184 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 185 <&gcc GCC_PCIE0_AHB_CLK>; 186 clock-names = "aux", "cfg_ahb"; 187 resets = <&gcc GCC_PCIE0_PHY_BCR>, 188 <&gcc GCC_PCIE0PHY_PHY_BCR>; 189 reset-names = "phy", 190 "common"; 191 status = "disabled"; 192 193 pcie_phy0: phy@84200 { 194 reg = <0x84200 0x16c>, 195 <0x84400 0x200>, 196 <0x84800 0x1f0>, 197 <0x84c00 0xf4>; 198 #phy-cells = <0>; 199 #clock-cells = <0>; 200 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 201 clock-names = "pipe0"; 202 clock-output-names = "pcie20_phy0_pipe_clk"; 203 }; 204 }; 205 206 pcie_qmp1: phy@8e000 { 207 compatible = "qcom,ipq8074-qmp-pcie-phy"; 208 reg = <0x0008e000 0x1c4>; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 ranges; 212 213 clocks = <&gcc GCC_PCIE1_AUX_CLK>, 214 <&gcc GCC_PCIE1_AHB_CLK>; 215 clock-names = "aux", "cfg_ahb"; 216 resets = <&gcc GCC_PCIE1_PHY_BCR>, 217 <&gcc GCC_PCIE1PHY_PHY_BCR>; 218 reset-names = "phy", 219 "common"; 220 status = "disabled"; 221 222 pcie_phy1: phy@8e200 { 223 reg = <0x8e200 0x130>, 224 <0x8e400 0x200>, 225 <0x8e800 0x1f8>; 226 #phy-cells = <0>; 227 #clock-cells = <0>; 228 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 229 clock-names = "pipe0"; 230 clock-output-names = "pcie20_phy1_pipe_clk"; 231 }; 232 }; 233 234 prng: rng@e3000 { 235 compatible = "qcom,prng-ee"; 236 reg = <0x000e3000 0x1000>; 237 clocks = <&gcc GCC_PRNG_AHB_CLK>; 238 clock-names = "core"; 239 status = "disabled"; 240 }; 241 242 cryptobam: dma@704000 { 243 compatible = "qcom,bam-v1.7.0"; 244 reg = <0x00704000 0x20000>; 245 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 247 clock-names = "bam_clk"; 248 #dma-cells = <1>; 249 qcom,ee = <1>; 250 qcom,controlled-remotely; 251 status = "disabled"; 252 }; 253 254 crypto: crypto@73a000 { 255 compatible = "qcom,crypto-v5.1"; 256 reg = <0x0073a000 0x6000>; 257 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 258 <&gcc GCC_CRYPTO_AXI_CLK>, 259 <&gcc GCC_CRYPTO_CLK>; 260 clock-names = "iface", "bus", "core"; 261 dmas = <&cryptobam 2>, <&cryptobam 3>; 262 dma-names = "rx", "tx"; 263 status = "disabled"; 264 }; 265 266 tlmm: pinctrl@1000000 { 267 compatible = "qcom,ipq8074-pinctrl"; 268 reg = <0x01000000 0x300000>; 269 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 270 gpio-controller; 271 gpio-ranges = <&tlmm 0 0 70>; 272 #gpio-cells = <0x2>; 273 interrupt-controller; 274 #interrupt-cells = <0x2>; 275 276 serial_4_pins: serial4-pinmux { 277 pins = "gpio23", "gpio24"; 278 function = "blsp4_uart1"; 279 drive-strength = <8>; 280 bias-disable; 281 }; 282 283 i2c_0_pins: i2c-0-pinmux { 284 pins = "gpio42", "gpio43"; 285 function = "blsp1_i2c"; 286 drive-strength = <8>; 287 bias-disable; 288 }; 289 290 spi_0_pins: spi-0-pins { 291 pins = "gpio38", "gpio39", "gpio40", "gpio41"; 292 function = "blsp0_spi"; 293 drive-strength = <8>; 294 bias-disable; 295 }; 296 297 hsuart_pins: hsuart-pins { 298 pins = "gpio46", "gpio47", "gpio48", "gpio49"; 299 function = "blsp2_uart"; 300 drive-strength = <8>; 301 bias-disable; 302 }; 303 304 qpic_pins: qpic-pins { 305 pins = "gpio1", "gpio3", "gpio4", 306 "gpio5", "gpio6", "gpio7", 307 "gpio8", "gpio10", "gpio11", 308 "gpio12", "gpio13", "gpio14", 309 "gpio15", "gpio16", "gpio17"; 310 function = "qpic"; 311 drive-strength = <8>; 312 bias-disable; 313 }; 314 }; 315 316 gcc: gcc@1800000 { 317 compatible = "qcom,gcc-ipq8074"; 318 reg = <0x01800000 0x80000>; 319 #clock-cells = <0x1>; 320 #reset-cells = <0x1>; 321 }; 322 323 sdhc_1: sdhci@7824900 { 324 compatible = "qcom,sdhci-msm-v4"; 325 reg = <0x7824900 0x500>, <0x7824000 0x800>; 326 reg-names = "hc_mem", "core_mem"; 327 328 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 330 interrupt-names = "hc_irq", "pwr_irq"; 331 332 clocks = <&xo>, 333 <&gcc GCC_SDCC1_AHB_CLK>, 334 <&gcc GCC_SDCC1_APPS_CLK>; 335 clock-names = "xo", "iface", "core"; 336 max-frequency = <384000000>; 337 mmc-ddr-1_8v; 338 mmc-hs200-1_8v; 339 mmc-hs400-1_8v; 340 bus-width = <8>; 341 342 status = "disabled"; 343 }; 344 345 blsp_dma: dma-controller@7884000 { 346 compatible = "qcom,bam-v1.7.0"; 347 reg = <0x07884000 0x2b000>; 348 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 350 clock-names = "bam_clk"; 351 #dma-cells = <1>; 352 qcom,ee = <0>; 353 }; 354 355 blsp1_uart1: serial@78af000 { 356 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 357 reg = <0x078af000 0x200>; 358 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 360 <&gcc GCC_BLSP1_AHB_CLK>; 361 clock-names = "core", "iface"; 362 status = "disabled"; 363 }; 364 365 blsp1_uart3: serial@78b1000 { 366 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 367 reg = <0x078b1000 0x200>; 368 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 370 <&gcc GCC_BLSP1_AHB_CLK>; 371 clock-names = "core", "iface"; 372 dmas = <&blsp_dma 4>, 373 <&blsp_dma 5>; 374 dma-names = "tx", "rx"; 375 pinctrl-0 = <&hsuart_pins>; 376 pinctrl-names = "default"; 377 status = "disabled"; 378 }; 379 380 blsp1_uart5: serial@78b3000 { 381 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 382 reg = <0x078b3000 0x200>; 383 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 385 <&gcc GCC_BLSP1_AHB_CLK>; 386 clock-names = "core", "iface"; 387 pinctrl-0 = <&serial_4_pins>; 388 pinctrl-names = "default"; 389 status = "disabled"; 390 }; 391 392 blsp1_spi1: spi@78b5000 { 393 compatible = "qcom,spi-qup-v2.2.1"; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 reg = <0x078b5000 0x600>; 397 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 398 spi-max-frequency = <50000000>; 399 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 400 <&gcc GCC_BLSP1_AHB_CLK>; 401 clock-names = "core", "iface"; 402 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 403 dma-names = "tx", "rx"; 404 pinctrl-0 = <&spi_0_pins>; 405 pinctrl-names = "default"; 406 status = "disabled"; 407 }; 408 409 blsp1_i2c2: i2c@78b6000 { 410 compatible = "qcom,i2c-qup-v2.2.1"; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 reg = <0x078b6000 0x600>; 414 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 416 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 417 clock-names = "iface", "core"; 418 clock-frequency = <400000>; 419 dmas = <&blsp_dma 15>, <&blsp_dma 14>; 420 dma-names = "rx", "tx"; 421 pinctrl-0 = <&i2c_0_pins>; 422 pinctrl-names = "default"; 423 status = "disabled"; 424 }; 425 426 blsp1_i2c3: i2c@78b7000 { 427 compatible = "qcom,i2c-qup-v2.2.1"; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 reg = <0x078b7000 0x600>; 431 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 433 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 434 clock-names = "iface", "core"; 435 clock-frequency = <100000>; 436 dmas = <&blsp_dma 17>, <&blsp_dma 16>; 437 dma-names = "rx", "tx"; 438 status = "disabled"; 439 }; 440 441 blsp1_i2c6: i2c@78ba000 { 442 compatible = "qcom,i2c-qup-v2.2.1"; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 reg = <0x078ba000 0x600>; 446 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 448 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; 449 clock-names = "iface", "core"; 450 clock-frequency = <100000>; 451 dmas = <&blsp_dma 23>, <&blsp_dma 22>; 452 dma-names = "rx", "tx"; 453 status = "disabled"; 454 }; 455 456 qpic_bam: dma-controller@7984000 { 457 compatible = "qcom,bam-v1.7.0"; 458 reg = <0x07984000 0x1a000>; 459 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&gcc GCC_QPIC_AHB_CLK>; 461 clock-names = "bam_clk"; 462 #dma-cells = <1>; 463 qcom,ee = <0>; 464 status = "disabled"; 465 }; 466 467 qpic_nand: nand-controller@79b0000 { 468 compatible = "qcom,ipq8074-nand"; 469 reg = <0x079b0000 0x10000>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 clocks = <&gcc GCC_QPIC_CLK>, 473 <&gcc GCC_QPIC_AHB_CLK>; 474 clock-names = "core", "aon"; 475 476 dmas = <&qpic_bam 0>, 477 <&qpic_bam 1>, 478 <&qpic_bam 2>; 479 dma-names = "tx", "rx", "cmd"; 480 pinctrl-0 = <&qpic_pins>; 481 pinctrl-names = "default"; 482 status = "disabled"; 483 }; 484 485 usb_0: usb@8af8800 { 486 compatible = "qcom,dwc3"; 487 reg = <0x08af8800 0x400>; 488 #address-cells = <1>; 489 #size-cells = <1>; 490 ranges; 491 492 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 493 <&gcc GCC_USB0_MASTER_CLK>, 494 <&gcc GCC_USB0_SLEEP_CLK>, 495 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 496 clock-names = "sys_noc_axi", 497 "master", 498 "sleep", 499 "mock_utmi"; 500 501 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 502 <&gcc GCC_USB0_MASTER_CLK>, 503 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 504 assigned-clock-rates = <133330000>, 505 <133330000>, 506 <19200000>; 507 508 resets = <&gcc GCC_USB0_BCR>; 509 status = "disabled"; 510 511 dwc_0: dwc3@8a00000 { 512 compatible = "snps,dwc3"; 513 reg = <0x8a00000 0xcd00>; 514 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 515 phys = <&qusb_phy_0>, <&usb0_ssphy>; 516 phy-names = "usb2-phy", "usb3-phy"; 517 snps,is-utmi-l1-suspend; 518 snps,hird-threshold = /bits/ 8 <0x0>; 519 snps,dis_u2_susphy_quirk; 520 snps,dis_u3_susphy_quirk; 521 dr_mode = "host"; 522 }; 523 }; 524 525 usb_1: usb@8cf8800 { 526 compatible = "qcom,dwc3"; 527 reg = <0x08cf8800 0x400>; 528 #address-cells = <1>; 529 #size-cells = <1>; 530 ranges; 531 532 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 533 <&gcc GCC_USB1_MASTER_CLK>, 534 <&gcc GCC_USB1_SLEEP_CLK>, 535 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 536 clock-names = "sys_noc_axi", 537 "master", 538 "sleep", 539 "mock_utmi"; 540 541 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 542 <&gcc GCC_USB1_MASTER_CLK>, 543 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 544 assigned-clock-rates = <133330000>, 545 <133330000>, 546 <19200000>; 547 548 resets = <&gcc GCC_USB1_BCR>; 549 status = "disabled"; 550 551 dwc_1: dwc3@8c00000 { 552 compatible = "snps,dwc3"; 553 reg = <0x8c00000 0xcd00>; 554 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 555 phys = <&qusb_phy_1>, <&usb1_ssphy>; 556 phy-names = "usb2-phy", "usb3-phy"; 557 snps,is-utmi-l1-suspend; 558 snps,hird-threshold = /bits/ 8 <0x0>; 559 snps,dis_u2_susphy_quirk; 560 snps,dis_u3_susphy_quirk; 561 dr_mode = "host"; 562 }; 563 }; 564 565 intc: interrupt-controller@b000000 { 566 compatible = "qcom,msm-qgic2"; 567 interrupt-controller; 568 #interrupt-cells = <0x3>; 569 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 570 }; 571 572 timer { 573 compatible = "arm,armv8-timer"; 574 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 575 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 576 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 577 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 578 }; 579 580 watchdog: watchdog@b017000 { 581 compatible = "qcom,kpss-wdt"; 582 reg = <0xb017000 0x1000>; 583 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 584 clocks = <&sleep_clk>; 585 timeout-sec = <30>; 586 }; 587 588 timer@b120000 { 589 #address-cells = <1>; 590 #size-cells = <1>; 591 ranges; 592 compatible = "arm,armv7-timer-mem"; 593 reg = <0x0b120000 0x1000>; 594 clock-frequency = <19200000>; 595 596 frame@b120000 { 597 frame-number = <0>; 598 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 600 reg = <0x0b121000 0x1000>, 601 <0x0b122000 0x1000>; 602 }; 603 604 frame@b123000 { 605 frame-number = <1>; 606 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 607 reg = <0x0b123000 0x1000>; 608 status = "disabled"; 609 }; 610 611 frame@b124000 { 612 frame-number = <2>; 613 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 614 reg = <0x0b124000 0x1000>; 615 status = "disabled"; 616 }; 617 618 frame@b125000 { 619 frame-number = <3>; 620 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 621 reg = <0x0b125000 0x1000>; 622 status = "disabled"; 623 }; 624 625 frame@b126000 { 626 frame-number = <4>; 627 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 628 reg = <0x0b126000 0x1000>; 629 status = "disabled"; 630 }; 631 632 frame@b127000 { 633 frame-number = <5>; 634 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 635 reg = <0x0b127000 0x1000>; 636 status = "disabled"; 637 }; 638 639 frame@b128000 { 640 frame-number = <6>; 641 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 642 reg = <0x0b128000 0x1000>; 643 status = "disabled"; 644 }; 645 }; 646 647 pcie1: pci@10000000 { 648 compatible = "qcom,pcie-ipq8074"; 649 reg = <0x10000000 0xf1d>, 650 <0x10000f20 0xa8>, 651 <0x00088000 0x2000>, 652 <0x10100000 0x1000>; 653 reg-names = "dbi", "elbi", "parf", "config"; 654 device_type = "pci"; 655 linux,pci-domain = <1>; 656 bus-range = <0x00 0xff>; 657 num-lanes = <1>; 658 #address-cells = <3>; 659 #size-cells = <2>; 660 661 phys = <&pcie_phy1>; 662 phy-names = "pciephy"; 663 664 ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ 665 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */ 666 667 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 668 interrupt-names = "msi"; 669 #interrupt-cells = <1>; 670 interrupt-map-mask = <0 0 0 0x7>; 671 interrupt-map = <0 0 0 1 &intc 0 142 672 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 673 <0 0 0 2 &intc 0 143 674 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 675 <0 0 0 3 &intc 0 144 676 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 677 <0 0 0 4 &intc 0 145 678 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 679 680 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 681 <&gcc GCC_PCIE1_AXI_M_CLK>, 682 <&gcc GCC_PCIE1_AXI_S_CLK>, 683 <&gcc GCC_PCIE1_AHB_CLK>, 684 <&gcc GCC_PCIE1_AUX_CLK>; 685 clock-names = "iface", 686 "axi_m", 687 "axi_s", 688 "ahb", 689 "aux"; 690 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 691 <&gcc GCC_PCIE1_SLEEP_ARES>, 692 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 693 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 694 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 695 <&gcc GCC_PCIE1_AHB_ARES>, 696 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 697 reset-names = "pipe", 698 "sleep", 699 "sticky", 700 "axi_m", 701 "axi_s", 702 "ahb", 703 "axi_m_sticky"; 704 status = "disabled"; 705 }; 706 707 pcie0: pci@20000000 { 708 compatible = "qcom,pcie-ipq8074-gen3"; 709 reg = <0x20000000 0xf1d>, 710 <0x20000f20 0xa8>, 711 <0x20001000 0x1000>, 712 <0x00080000 0x4000>, 713 <0x20100000 0x1000>; 714 reg-names = "dbi", "elbi", "atu", "parf", "config"; 715 device_type = "pci"; 716 linux,pci-domain = <0>; 717 bus-range = <0x00 0xff>; 718 num-lanes = <1>; 719 max-link-speed = <3>; 720 #address-cells = <3>; 721 #size-cells = <2>; 722 723 phys = <&pcie_phy0>; 724 phy-names = "pciephy"; 725 726 ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ 727 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */ 728 729 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 730 interrupt-names = "msi"; 731 #interrupt-cells = <1>; 732 interrupt-map-mask = <0 0 0 0x7>; 733 interrupt-map = <0 0 0 1 &intc 0 75 734 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 735 <0 0 0 2 &intc 0 78 736 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 737 <0 0 0 3 &intc 0 79 738 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 739 <0 0 0 4 &intc 0 83 740 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 741 742 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 743 <&gcc GCC_PCIE0_AXI_M_CLK>, 744 <&gcc GCC_PCIE0_AXI_S_CLK>, 745 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 746 <&gcc GCC_PCIE0_RCHNG_CLK>; 747 clock-names = "iface", 748 "axi_m", 749 "axi_s", 750 "axi_bridge", 751 "rchng"; 752 753 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 754 <&gcc GCC_PCIE0_SLEEP_ARES>, 755 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 756 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 757 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 758 <&gcc GCC_PCIE0_AHB_ARES>, 759 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 760 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 761 reset-names = "pipe", 762 "sleep", 763 "sticky", 764 "axi_m", 765 "axi_s", 766 "ahb", 767 "axi_m_sticky", 768 "axi_s_sticky"; 769 status = "disabled"; 770 }; 771 }; 772}; 773