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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 */
5
6#include <dt-bindings/arm/coresight-cti-dt.h>
7#include <dt-bindings/clock/qcom,gcc-msm8916.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/interconnect/qcom,msm8916.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/power/qcom-rpmpd.h>
12#include <dt-bindings/reset/qcom,gcc-msm8916.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16	interrupt-parent = <&intc>;
17
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	aliases {
22		mmc0 = &sdhc_1; /* SDC1 eMMC slot */
23		mmc1 = &sdhc_2; /* SDC2 SD card slot */
24	};
25
26	chosen { };
27
28	memory@80000000 {
29		device_type = "memory";
30		/* We expect the bootloader to fill in the reg */
31		reg = <0 0x80000000 0 0>;
32	};
33
34	reserved-memory {
35		#address-cells = <2>;
36		#size-cells = <2>;
37		ranges;
38
39		tz-apps@86000000 {
40			reg = <0x0 0x86000000 0x0 0x300000>;
41			no-map;
42		};
43
44		smem_mem: smem_region@86300000 {
45			reg = <0x0 0x86300000 0x0 0x100000>;
46			no-map;
47		};
48
49		hypervisor@86400000 {
50			reg = <0x0 0x86400000 0x0 0x100000>;
51			no-map;
52		};
53
54		tz@86500000 {
55			reg = <0x0 0x86500000 0x0 0x180000>;
56			no-map;
57		};
58
59		reserved@86680000 {
60			reg = <0x0 0x86680000 0x0 0x80000>;
61			no-map;
62		};
63
64		rmtfs@86700000 {
65			compatible = "qcom,rmtfs-mem";
66			reg = <0x0 0x86700000 0x0 0xe0000>;
67			no-map;
68
69			qcom,client-id = <1>;
70		};
71
72		rfsa@867e0000 {
73			reg = <0x0 0x867e0000 0x0 0x20000>;
74			no-map;
75		};
76
77		mpss_mem: mpss@86800000 {
78			reg = <0x0 0x86800000 0x0 0x2b00000>;
79			no-map;
80		};
81
82		wcnss_mem: wcnss@89300000 {
83			reg = <0x0 0x89300000 0x0 0x600000>;
84			no-map;
85		};
86
87		venus_mem: venus@89900000 {
88			reg = <0x0 0x89900000 0x0 0x600000>;
89			no-map;
90		};
91
92		mba_mem: mba@8ea00000 {
93			no-map;
94			reg = <0 0x8ea00000 0 0x100000>;
95		};
96	};
97
98	clocks {
99		xo_board: xo-board {
100			compatible = "fixed-clock";
101			#clock-cells = <0>;
102			clock-frequency = <19200000>;
103		};
104
105		sleep_clk: sleep-clk {
106			compatible = "fixed-clock";
107			#clock-cells = <0>;
108			clock-frequency = <32768>;
109		};
110	};
111
112	cpus {
113		#address-cells = <1>;
114		#size-cells = <0>;
115
116		CPU0: cpu@0 {
117			device_type = "cpu";
118			compatible = "arm,cortex-a53";
119			reg = <0x0>;
120			next-level-cache = <&L2_0>;
121			enable-method = "psci";
122			clocks = <&apcs>;
123			operating-points-v2 = <&cpu_opp_table>;
124			#cooling-cells = <2>;
125			power-domains = <&CPU_PD0>;
126			power-domain-names = "psci";
127		};
128
129		CPU1: cpu@1 {
130			device_type = "cpu";
131			compatible = "arm,cortex-a53";
132			reg = <0x1>;
133			next-level-cache = <&L2_0>;
134			enable-method = "psci";
135			clocks = <&apcs>;
136			operating-points-v2 = <&cpu_opp_table>;
137			#cooling-cells = <2>;
138			power-domains = <&CPU_PD1>;
139			power-domain-names = "psci";
140		};
141
142		CPU2: cpu@2 {
143			device_type = "cpu";
144			compatible = "arm,cortex-a53";
145			reg = <0x2>;
146			next-level-cache = <&L2_0>;
147			enable-method = "psci";
148			clocks = <&apcs>;
149			operating-points-v2 = <&cpu_opp_table>;
150			#cooling-cells = <2>;
151			power-domains = <&CPU_PD2>;
152			power-domain-names = "psci";
153		};
154
155		CPU3: cpu@3 {
156			device_type = "cpu";
157			compatible = "arm,cortex-a53";
158			reg = <0x3>;
159			next-level-cache = <&L2_0>;
160			enable-method = "psci";
161			clocks = <&apcs>;
162			operating-points-v2 = <&cpu_opp_table>;
163			#cooling-cells = <2>;
164			power-domains = <&CPU_PD3>;
165			power-domain-names = "psci";
166		};
167
168		L2_0: l2-cache {
169			compatible = "cache";
170			cache-level = <2>;
171		};
172
173		idle-states {
174			entry-method = "psci";
175
176			CPU_SLEEP_0: cpu-sleep-0 {
177				compatible = "arm,idle-state";
178				idle-state-name = "standalone-power-collapse";
179				arm,psci-suspend-param = <0x40000002>;
180				entry-latency-us = <130>;
181				exit-latency-us = <150>;
182				min-residency-us = <2000>;
183				local-timer-stop;
184			};
185		};
186
187		domain-idle-states {
188
189			CLUSTER_RET: cluster-retention {
190				compatible = "domain-idle-state";
191				arm,psci-suspend-param = <0x41000012>;
192				entry-latency-us = <500>;
193				exit-latency-us = <500>;
194				min-residency-us = <2000>;
195			};
196
197			CLUSTER_PWRDN: cluster-gdhs {
198				compatible = "domain-idle-state";
199				arm,psci-suspend-param = <0x41000032>;
200				entry-latency-us = <2000>;
201				exit-latency-us = <2000>;
202				min-residency-us = <6000>;
203			};
204		};
205	};
206
207	cpu_opp_table: cpu-opp-table {
208		compatible = "operating-points-v2";
209		opp-shared;
210
211		opp-200000000 {
212			opp-hz = /bits/ 64 <200000000>;
213		};
214		opp-400000000 {
215			opp-hz = /bits/ 64 <400000000>;
216		};
217		opp-800000000 {
218			opp-hz = /bits/ 64 <800000000>;
219		};
220		opp-998400000 {
221			opp-hz = /bits/ 64 <998400000>;
222		};
223	};
224
225	firmware {
226		scm: scm {
227			compatible = "qcom,scm-msm8916", "qcom,scm";
228			clocks = <&gcc GCC_CRYPTO_CLK>,
229				 <&gcc GCC_CRYPTO_AXI_CLK>,
230				 <&gcc GCC_CRYPTO_AHB_CLK>;
231			clock-names = "core", "bus", "iface";
232			#reset-cells = <1>;
233
234			qcom,dload-mode = <&tcsr 0x6100>;
235		};
236	};
237
238	pmu {
239		compatible = "arm,cortex-a53-pmu";
240		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
241	};
242
243	psci {
244		compatible = "arm,psci-1.0";
245		method = "smc";
246
247		CPU_PD0: power-domain-cpu0 {
248			#power-domain-cells = <0>;
249			power-domains = <&CLUSTER_PD>;
250			domain-idle-states = <&CPU_SLEEP_0>;
251		};
252
253		CPU_PD1: power-domain-cpu1 {
254			#power-domain-cells = <0>;
255			power-domains = <&CLUSTER_PD>;
256			domain-idle-states = <&CPU_SLEEP_0>;
257		};
258
259		CPU_PD2: power-domain-cpu2 {
260			#power-domain-cells = <0>;
261			power-domains = <&CLUSTER_PD>;
262			domain-idle-states = <&CPU_SLEEP_0>;
263		};
264
265		CPU_PD3: power-domain-cpu3 {
266			#power-domain-cells = <0>;
267			power-domains = <&CLUSTER_PD>;
268			domain-idle-states = <&CPU_SLEEP_0>;
269		};
270
271		CLUSTER_PD: power-domain-cluster {
272			#power-domain-cells = <0>;
273			domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
274		};
275	};
276
277	smd {
278		compatible = "qcom,smd";
279
280		rpm {
281			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
282			qcom,ipc = <&apcs 8 0>;
283			qcom,smd-edge = <15>;
284
285			rpm_requests: rpm-requests {
286				compatible = "qcom,rpm-msm8916";
287				qcom,smd-channels = "rpm_requests";
288
289				rpmcc: clock-controller {
290					compatible = "qcom,rpmcc-msm8916";
291					#clock-cells = <1>;
292				};
293
294				rpmpd: power-controller {
295					compatible = "qcom,msm8916-rpmpd";
296					#power-domain-cells = <1>;
297					operating-points-v2 = <&rpmpd_opp_table>;
298
299					rpmpd_opp_table: opp-table {
300						compatible = "operating-points-v2";
301
302						rpmpd_opp_ret: opp1 {
303							opp-level = <1>;
304						};
305						rpmpd_opp_svs_krait: opp2 {
306							opp-level = <2>;
307						};
308						rpmpd_opp_svs_soc: opp3 {
309							opp-level = <3>;
310						};
311						rpmpd_opp_nom: opp4 {
312							opp-level = <4>;
313						};
314						rpmpd_opp_turbo: opp5 {
315							opp-level = <5>;
316						};
317						rpmpd_opp_super_turbo: opp6 {
318							opp-level = <6>;
319						};
320					};
321				};
322			};
323		};
324	};
325
326	smem {
327		compatible = "qcom,smem";
328
329		memory-region = <&smem_mem>;
330		qcom,rpm-msg-ram = <&rpm_msg_ram>;
331
332		hwlocks = <&tcsr_mutex 3>;
333	};
334
335	smp2p-hexagon {
336		compatible = "qcom,smp2p";
337		qcom,smem = <435>, <428>;
338
339		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
340
341		qcom,ipc = <&apcs 8 14>;
342
343		qcom,local-pid = <0>;
344		qcom,remote-pid = <1>;
345
346		hexagon_smp2p_out: master-kernel {
347			qcom,entry-name = "master-kernel";
348
349			#qcom,smem-state-cells = <1>;
350		};
351
352		hexagon_smp2p_in: slave-kernel {
353			qcom,entry-name = "slave-kernel";
354
355			interrupt-controller;
356			#interrupt-cells = <2>;
357		};
358	};
359
360	smp2p-wcnss {
361		compatible = "qcom,smp2p";
362		qcom,smem = <451>, <431>;
363
364		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
365
366		qcom,ipc = <&apcs 8 18>;
367
368		qcom,local-pid = <0>;
369		qcom,remote-pid = <4>;
370
371		wcnss_smp2p_out: master-kernel {
372			qcom,entry-name = "master-kernel";
373
374			#qcom,smem-state-cells = <1>;
375		};
376
377		wcnss_smp2p_in: slave-kernel {
378			qcom,entry-name = "slave-kernel";
379
380			interrupt-controller;
381			#interrupt-cells = <2>;
382		};
383	};
384
385	smsm {
386		compatible = "qcom,smsm";
387
388		#address-cells = <1>;
389		#size-cells = <0>;
390
391		qcom,ipc-1 = <&apcs 8 13>;
392		qcom,ipc-3 = <&apcs 8 19>;
393
394		apps_smsm: apps@0 {
395			reg = <0>;
396
397			#qcom,smem-state-cells = <1>;
398		};
399
400		hexagon_smsm: hexagon@1 {
401			reg = <1>;
402			interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
403
404			interrupt-controller;
405			#interrupt-cells = <2>;
406		};
407
408		wcnss_smsm: wcnss@6 {
409			reg = <6>;
410			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
411
412			interrupt-controller;
413			#interrupt-cells = <2>;
414		};
415	};
416
417	soc: soc {
418		#address-cells = <1>;
419		#size-cells = <1>;
420		ranges = <0 0 0 0xffffffff>;
421		compatible = "simple-bus";
422
423		rng@22000 {
424			compatible = "qcom,prng";
425			reg = <0x00022000 0x200>;
426			clocks = <&gcc GCC_PRNG_AHB_CLK>;
427			clock-names = "core";
428		};
429
430		restart@4ab000 {
431			compatible = "qcom,pshold";
432			reg = <0x004ab000 0x4>;
433		};
434
435		qfprom: qfprom@5c000 {
436			compatible = "qcom,qfprom";
437			reg = <0x0005c000 0x1000>;
438			#address-cells = <1>;
439			#size-cells = <1>;
440			tsens_caldata: caldata@d0 {
441				reg = <0xd0 0x8>;
442			};
443			tsens_calsel: calsel@ec {
444				reg = <0xec 0x4>;
445			};
446		};
447
448		rpm_msg_ram: sram@60000 {
449			compatible = "qcom,rpm-msg-ram";
450			reg = <0x00060000 0x8000>;
451		};
452
453		bimc: interconnect@400000 {
454			compatible = "qcom,msm8916-bimc";
455			reg = <0x00400000 0x62000>;
456			#interconnect-cells = <1>;
457			clock-names = "bus", "bus_a";
458			clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
459				 <&rpmcc RPM_SMD_BIMC_A_CLK>;
460		};
461
462		tsens: thermal-sensor@4a9000 {
463			compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
464			reg = <0x004a9000 0x1000>, /* TM */
465			      <0x004a8000 0x1000>; /* SROT */
466			nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
467			nvmem-cell-names = "calib", "calib_sel";
468			#qcom,sensors = <5>;
469			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
470			interrupt-names = "uplow";
471			#thermal-sensor-cells = <1>;
472		};
473
474		pcnoc: interconnect@500000 {
475			compatible = "qcom,msm8916-pcnoc";
476			reg = <0x00500000 0x11000>;
477			#interconnect-cells = <1>;
478			clock-names = "bus", "bus_a";
479			clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
480				 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
481		};
482
483		snoc: interconnect@580000 {
484			compatible = "qcom,msm8916-snoc";
485			reg = <0x00580000 0x14000>;
486			#interconnect-cells = <1>;
487			clock-names = "bus", "bus_a";
488			clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
489				 <&rpmcc RPM_SMD_SNOC_A_CLK>;
490		};
491
492		stm: stm@802000 {
493			compatible = "arm,coresight-stm", "arm,primecell";
494			reg = <0x00802000 0x1000>,
495			      <0x09280000 0x180000>;
496			reg-names = "stm-base", "stm-stimulus-base";
497
498			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
499			clock-names = "apb_pclk", "atclk";
500
501			status = "disabled";
502
503			out-ports {
504				port {
505					stm_out: endpoint {
506						remote-endpoint = <&funnel0_in7>;
507					};
508				};
509			};
510		};
511
512		/* System CTIs */
513		/* CTI 0 - TMC connections */
514		cti0: cti@810000 {
515			compatible = "arm,coresight-cti", "arm,primecell";
516			reg = <0x00810000 0x1000>;
517
518			clocks = <&rpmcc RPM_QDSS_CLK>;
519			clock-names = "apb_pclk";
520
521			status = "disabled";
522		};
523
524		/* CTI 1 - TPIU connections */
525		cti1: cti@811000 {
526			compatible = "arm,coresight-cti", "arm,primecell";
527			reg = <0x00811000 0x1000>;
528
529			clocks = <&rpmcc RPM_QDSS_CLK>;
530			clock-names = "apb_pclk";
531
532			status = "disabled";
533		};
534
535		/* CTIs 2-11 - no information - not instantiated */
536
537		tpiu: tpiu@820000 {
538			compatible = "arm,coresight-tpiu", "arm,primecell";
539			reg = <0x00820000 0x1000>;
540
541			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
542			clock-names = "apb_pclk", "atclk";
543
544			status = "disabled";
545
546			in-ports {
547				port {
548					tpiu_in: endpoint {
549						remote-endpoint = <&replicator_out1>;
550					};
551				};
552			};
553		};
554
555		funnel0: funnel@821000 {
556			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
557			reg = <0x00821000 0x1000>;
558
559			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
560			clock-names = "apb_pclk", "atclk";
561
562			status = "disabled";
563
564			in-ports {
565				#address-cells = <1>;
566				#size-cells = <0>;
567
568				/*
569				 * Not described input ports:
570				 * 0 - connected to Resource and Power Manger CPU ETM
571				 * 1 - not-connected
572				 * 2 - connected to Modem CPU ETM
573				 * 3 - not-connected
574				 * 5 - not-connected
575				 * 6 - connected trought funnel to Wireless CPU ETM
576				 * 7 - connected to STM component
577				 */
578
579				port@4 {
580					reg = <4>;
581					funnel0_in4: endpoint {
582						remote-endpoint = <&funnel1_out>;
583					};
584				};
585
586				port@7 {
587					reg = <7>;
588					funnel0_in7: endpoint {
589						remote-endpoint = <&stm_out>;
590					};
591				};
592			};
593
594			out-ports {
595				port {
596					funnel0_out: endpoint {
597						remote-endpoint = <&etf_in>;
598					};
599				};
600			};
601		};
602
603		replicator: replicator@824000 {
604			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
605			reg = <0x00824000 0x1000>;
606
607			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
608			clock-names = "apb_pclk", "atclk";
609
610			status = "disabled";
611
612			out-ports {
613				#address-cells = <1>;
614				#size-cells = <0>;
615
616				port@0 {
617					reg = <0>;
618					replicator_out0: endpoint {
619						remote-endpoint = <&etr_in>;
620					};
621				};
622				port@1 {
623					reg = <1>;
624					replicator_out1: endpoint {
625						remote-endpoint = <&tpiu_in>;
626					};
627				};
628			};
629
630			in-ports {
631				port {
632					replicator_in: endpoint {
633						remote-endpoint = <&etf_out>;
634					};
635				};
636			};
637		};
638
639		etf: etf@825000 {
640			compatible = "arm,coresight-tmc", "arm,primecell";
641			reg = <0x00825000 0x1000>;
642
643			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
644			clock-names = "apb_pclk", "atclk";
645
646			status = "disabled";
647
648			in-ports {
649				port {
650					etf_in: endpoint {
651						remote-endpoint = <&funnel0_out>;
652					};
653				};
654			};
655
656			out-ports {
657				port {
658					etf_out: endpoint {
659						remote-endpoint = <&replicator_in>;
660					};
661				};
662			};
663		};
664
665		etr: etr@826000 {
666			compatible = "arm,coresight-tmc", "arm,primecell";
667			reg = <0x00826000 0x1000>;
668
669			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
670			clock-names = "apb_pclk", "atclk";
671
672			status = "disabled";
673
674			in-ports {
675				port {
676					etr_in: endpoint {
677						remote-endpoint = <&replicator_out0>;
678					};
679				};
680			};
681		};
682
683		funnel1: funnel@841000 {	/* APSS funnel only 4 inputs are used */
684			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
685			reg = <0x00841000 0x1000>;
686
687			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
688			clock-names = "apb_pclk", "atclk";
689
690			status = "disabled";
691
692			in-ports {
693				#address-cells = <1>;
694				#size-cells = <0>;
695
696				port@0 {
697					reg = <0>;
698					funnel1_in0: endpoint {
699						remote-endpoint = <&etm0_out>;
700					};
701				};
702				port@1 {
703					reg = <1>;
704					funnel1_in1: endpoint {
705						remote-endpoint = <&etm1_out>;
706					};
707				};
708				port@2 {
709					reg = <2>;
710					funnel1_in2: endpoint {
711						remote-endpoint = <&etm2_out>;
712					};
713				};
714				port@3 {
715					reg = <3>;
716					funnel1_in3: endpoint {
717						remote-endpoint = <&etm3_out>;
718					};
719				};
720			};
721
722			out-ports {
723				port {
724					funnel1_out: endpoint {
725						remote-endpoint = <&funnel0_in4>;
726					};
727				};
728			};
729		};
730
731		debug0: debug@850000 {
732			compatible = "arm,coresight-cpu-debug", "arm,primecell";
733			reg = <0x00850000 0x1000>;
734			clocks = <&rpmcc RPM_QDSS_CLK>;
735			clock-names = "apb_pclk";
736			cpu = <&CPU0>;
737			status = "disabled";
738		};
739
740		debug1: debug@852000 {
741			compatible = "arm,coresight-cpu-debug", "arm,primecell";
742			reg = <0x00852000 0x1000>;
743			clocks = <&rpmcc RPM_QDSS_CLK>;
744			clock-names = "apb_pclk";
745			cpu = <&CPU1>;
746			status = "disabled";
747		};
748
749		debug2: debug@854000 {
750			compatible = "arm,coresight-cpu-debug", "arm,primecell";
751			reg = <0x00854000 0x1000>;
752			clocks = <&rpmcc RPM_QDSS_CLK>;
753			clock-names = "apb_pclk";
754			cpu = <&CPU2>;
755			status = "disabled";
756		};
757
758		debug3: debug@856000 {
759			compatible = "arm,coresight-cpu-debug", "arm,primecell";
760			reg = <0x00856000 0x1000>;
761			clocks = <&rpmcc RPM_QDSS_CLK>;
762			clock-names = "apb_pclk";
763			cpu = <&CPU3>;
764			status = "disabled";
765		};
766
767		/* Core CTIs; CTIs 12-15 */
768		/* CTI - CPU-0 */
769		cti12: cti@858000 {
770			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
771				     "arm,primecell";
772			reg = <0x00858000 0x1000>;
773
774			clocks = <&rpmcc RPM_QDSS_CLK>;
775			clock-names = "apb_pclk";
776
777			cpu = <&CPU0>;
778			arm,cs-dev-assoc = <&etm0>;
779
780			status = "disabled";
781		};
782
783		/* CTI - CPU-1 */
784		cti13: cti@859000 {
785			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
786				     "arm,primecell";
787			reg = <0x00859000 0x1000>;
788
789			clocks = <&rpmcc RPM_QDSS_CLK>;
790			clock-names = "apb_pclk";
791
792			cpu = <&CPU1>;
793			arm,cs-dev-assoc = <&etm1>;
794
795			status = "disabled";
796		};
797
798		/* CTI - CPU-2 */
799		cti14: cti@85a000 {
800			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
801				     "arm,primecell";
802			reg = <0x0085a000 0x1000>;
803
804			clocks = <&rpmcc RPM_QDSS_CLK>;
805			clock-names = "apb_pclk";
806
807			cpu = <&CPU2>;
808			arm,cs-dev-assoc = <&etm2>;
809
810			status = "disabled";
811		};
812
813		/* CTI - CPU-3 */
814		cti15: cti@85b000 {
815			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
816				     "arm,primecell";
817			reg = <0x0085b000 0x1000>;
818
819			clocks = <&rpmcc RPM_QDSS_CLK>;
820			clock-names = "apb_pclk";
821
822			cpu = <&CPU3>;
823			arm,cs-dev-assoc = <&etm3>;
824
825			status = "disabled";
826		};
827
828		etm0: etm@85c000 {
829			compatible = "arm,coresight-etm4x", "arm,primecell";
830			reg = <0x0085c000 0x1000>;
831
832			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
833			clock-names = "apb_pclk", "atclk";
834			arm,coresight-loses-context-with-cpu;
835
836			cpu = <&CPU0>;
837
838			status = "disabled";
839
840			out-ports {
841				port {
842					etm0_out: endpoint {
843						remote-endpoint = <&funnel1_in0>;
844					};
845				};
846			};
847		};
848
849		etm1: etm@85d000 {
850			compatible = "arm,coresight-etm4x", "arm,primecell";
851			reg = <0x0085d000 0x1000>;
852
853			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
854			clock-names = "apb_pclk", "atclk";
855			arm,coresight-loses-context-with-cpu;
856
857			cpu = <&CPU1>;
858
859			status = "disabled";
860
861			out-ports {
862				port {
863					etm1_out: endpoint {
864						remote-endpoint = <&funnel1_in1>;
865					};
866				};
867			};
868		};
869
870		etm2: etm@85e000 {
871			compatible = "arm,coresight-etm4x", "arm,primecell";
872			reg = <0x0085e000 0x1000>;
873
874			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
875			clock-names = "apb_pclk", "atclk";
876			arm,coresight-loses-context-with-cpu;
877
878			cpu = <&CPU2>;
879
880			status = "disabled";
881
882			out-ports {
883				port {
884					etm2_out: endpoint {
885						remote-endpoint = <&funnel1_in2>;
886					};
887				};
888			};
889		};
890
891		etm3: etm@85f000 {
892			compatible = "arm,coresight-etm4x", "arm,primecell";
893			reg = <0x0085f000 0x1000>;
894
895			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
896			clock-names = "apb_pclk", "atclk";
897			arm,coresight-loses-context-with-cpu;
898
899			cpu = <&CPU3>;
900
901			status = "disabled";
902
903			out-ports {
904				port {
905					etm3_out: endpoint {
906						remote-endpoint = <&funnel1_in3>;
907					};
908				};
909			};
910		};
911
912		msmgpio: pinctrl@1000000 {
913			compatible = "qcom,msm8916-pinctrl";
914			reg = <0x01000000 0x300000>;
915			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
916			gpio-controller;
917			gpio-ranges = <&msmgpio 0 0 122>;
918			#gpio-cells = <2>;
919			interrupt-controller;
920			#interrupt-cells = <2>;
921		};
922
923		gcc: clock-controller@1800000 {
924			compatible = "qcom,gcc-msm8916";
925			#clock-cells = <1>;
926			#reset-cells = <1>;
927			#power-domain-cells = <1>;
928			reg = <0x01800000 0x80000>;
929		};
930
931		tcsr_mutex: hwlock@1905000 {
932			compatible = "qcom,tcsr-mutex";
933			reg = <0x01905000 0x20000>;
934			#hwlock-cells = <1>;
935		};
936
937		tcsr: syscon@1937000 {
938			compatible = "qcom,tcsr-msm8916", "syscon";
939			reg = <0x01937000 0x30000>;
940		};
941
942		mdss: mdss@1a00000 {
943			status = "disabled";
944			compatible = "qcom,mdss";
945			reg = <0x01a00000 0x1000>,
946			      <0x01ac8000 0x3000>;
947			reg-names = "mdss_phys", "vbif_phys";
948
949			power-domains = <&gcc MDSS_GDSC>;
950
951			clocks = <&gcc GCC_MDSS_AHB_CLK>,
952				 <&gcc GCC_MDSS_AXI_CLK>,
953				 <&gcc GCC_MDSS_VSYNC_CLK>;
954			clock-names = "iface",
955				      "bus",
956				      "vsync";
957
958			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
959
960			interrupt-controller;
961			#interrupt-cells = <1>;
962
963			#address-cells = <1>;
964			#size-cells = <1>;
965			ranges;
966
967			mdp: mdp@1a01000 {
968				compatible = "qcom,mdp5";
969				reg = <0x01a01000 0x89000>;
970				reg-names = "mdp_phys";
971
972				interrupt-parent = <&mdss>;
973				interrupts = <0>;
974
975				clocks = <&gcc GCC_MDSS_AHB_CLK>,
976					 <&gcc GCC_MDSS_AXI_CLK>,
977					 <&gcc GCC_MDSS_MDP_CLK>,
978					 <&gcc GCC_MDSS_VSYNC_CLK>;
979				clock-names = "iface",
980					      "bus",
981					      "core",
982					      "vsync";
983
984				iommus = <&apps_iommu 4>;
985
986				ports {
987					#address-cells = <1>;
988					#size-cells = <0>;
989
990					port@0 {
991						reg = <0>;
992						mdp5_intf1_out: endpoint {
993							remote-endpoint = <&dsi0_in>;
994						};
995					};
996				};
997			};
998
999			dsi0: dsi@1a98000 {
1000				compatible = "qcom,mdss-dsi-ctrl";
1001				reg = <0x01a98000 0x25c>;
1002				reg-names = "dsi_ctrl";
1003
1004				interrupt-parent = <&mdss>;
1005				interrupts = <4>;
1006
1007				assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1008						  <&gcc PCLK0_CLK_SRC>;
1009				assigned-clock-parents = <&dsi_phy0 0>,
1010							 <&dsi_phy0 1>;
1011
1012				clocks = <&gcc GCC_MDSS_MDP_CLK>,
1013					 <&gcc GCC_MDSS_AHB_CLK>,
1014					 <&gcc GCC_MDSS_AXI_CLK>,
1015					 <&gcc GCC_MDSS_BYTE0_CLK>,
1016					 <&gcc GCC_MDSS_PCLK0_CLK>,
1017					 <&gcc GCC_MDSS_ESC0_CLK>;
1018				clock-names = "mdp_core",
1019					      "iface",
1020					      "bus",
1021					      "byte",
1022					      "pixel",
1023					      "core";
1024				phys = <&dsi_phy0>;
1025				phy-names = "dsi-phy";
1026
1027				#address-cells = <1>;
1028				#size-cells = <0>;
1029
1030				ports {
1031					#address-cells = <1>;
1032					#size-cells = <0>;
1033
1034					port@0 {
1035						reg = <0>;
1036						dsi0_in: endpoint {
1037							remote-endpoint = <&mdp5_intf1_out>;
1038						};
1039					};
1040
1041					port@1 {
1042						reg = <1>;
1043						dsi0_out: endpoint {
1044						};
1045					};
1046				};
1047			};
1048
1049			dsi_phy0: dsi-phy@1a98300 {
1050				compatible = "qcom,dsi-phy-28nm-lp";
1051				reg = <0x01a98300 0xd4>,
1052				      <0x01a98500 0x280>,
1053				      <0x01a98780 0x30>;
1054				reg-names = "dsi_pll",
1055					    "dsi_phy",
1056					    "dsi_phy_regulator";
1057
1058				#clock-cells = <1>;
1059				#phy-cells = <0>;
1060
1061				clocks = <&gcc GCC_MDSS_AHB_CLK>,
1062					 <&xo_board>;
1063				clock-names = "iface", "ref";
1064			};
1065		};
1066
1067		camss: camss@1b0ac00 {
1068			compatible = "qcom,msm8916-camss";
1069			reg = <0x01b0ac00 0x200>,
1070				<0x01b00030 0x4>,
1071				<0x01b0b000 0x200>,
1072				<0x01b00038 0x4>,
1073				<0x01b08000 0x100>,
1074				<0x01b08400 0x100>,
1075				<0x01b0a000 0x500>,
1076				<0x01b00020 0x10>,
1077				<0x01b10000 0x1000>;
1078			reg-names = "csiphy0",
1079				"csiphy0_clk_mux",
1080				"csiphy1",
1081				"csiphy1_clk_mux",
1082				"csid0",
1083				"csid1",
1084				"ispif",
1085				"csi_clk_mux",
1086				"vfe0";
1087			interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1088				<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1089				<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1090				<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1091				<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1092				<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1093			interrupt-names = "csiphy0",
1094				"csiphy1",
1095				"csid0",
1096				"csid1",
1097				"ispif",
1098				"vfe0";
1099			power-domains = <&gcc VFE_GDSC>;
1100			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1101				<&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1102				<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1103				<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1104				<&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1105				<&gcc GCC_CAMSS_CSI0_CLK>,
1106				<&gcc GCC_CAMSS_CSI0PHY_CLK>,
1107				<&gcc GCC_CAMSS_CSI0PIX_CLK>,
1108				<&gcc GCC_CAMSS_CSI0RDI_CLK>,
1109				<&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1110				<&gcc GCC_CAMSS_CSI1_CLK>,
1111				<&gcc GCC_CAMSS_CSI1PHY_CLK>,
1112				<&gcc GCC_CAMSS_CSI1PIX_CLK>,
1113				<&gcc GCC_CAMSS_CSI1RDI_CLK>,
1114				<&gcc GCC_CAMSS_AHB_CLK>,
1115				<&gcc GCC_CAMSS_VFE0_CLK>,
1116				<&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1117				<&gcc GCC_CAMSS_VFE_AHB_CLK>,
1118				<&gcc GCC_CAMSS_VFE_AXI_CLK>;
1119			clock-names = "top_ahb",
1120				"ispif_ahb",
1121				"csiphy0_timer",
1122				"csiphy1_timer",
1123				"csi0_ahb",
1124				"csi0",
1125				"csi0_phy",
1126				"csi0_pix",
1127				"csi0_rdi",
1128				"csi1_ahb",
1129				"csi1",
1130				"csi1_phy",
1131				"csi1_pix",
1132				"csi1_rdi",
1133				"ahb",
1134				"vfe0",
1135				"csi_vfe0",
1136				"vfe_ahb",
1137				"vfe_axi";
1138			iommus = <&apps_iommu 3>;
1139			status = "disabled";
1140			ports {
1141				#address-cells = <1>;
1142				#size-cells = <0>;
1143			};
1144		};
1145
1146		cci: cci@1b0c000 {
1147			compatible = "qcom,msm8916-cci";
1148			#address-cells = <1>;
1149			#size-cells = <0>;
1150			reg = <0x01b0c000 0x1000>;
1151			interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1152			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1153				<&gcc GCC_CAMSS_CCI_AHB_CLK>,
1154				<&gcc GCC_CAMSS_CCI_CLK>,
1155				<&gcc GCC_CAMSS_AHB_CLK>;
1156			clock-names = "camss_top_ahb", "cci_ahb",
1157					  "cci", "camss_ahb";
1158			assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1159					  <&gcc GCC_CAMSS_CCI_CLK>;
1160			assigned-clock-rates = <80000000>, <19200000>;
1161			pinctrl-names = "default";
1162			pinctrl-0 = <&cci0_default>;
1163			status = "disabled";
1164
1165			cci_i2c0: i2c-bus@0 {
1166				reg = <0>;
1167				clock-frequency = <400000>;
1168				#address-cells = <1>;
1169				#size-cells = <0>;
1170			};
1171		};
1172
1173		gpu@1c00000 {
1174			compatible = "qcom,adreno-306.0", "qcom,adreno";
1175			reg = <0x01c00000 0x20000>;
1176			reg-names = "kgsl_3d0_reg_memory";
1177			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1178			interrupt-names = "kgsl_3d0_irq";
1179			clock-names =
1180			    "core",
1181			    "iface",
1182			    "mem",
1183			    "mem_iface",
1184			    "alt_mem_iface",
1185			    "gfx3d";
1186			clocks =
1187			    <&gcc GCC_OXILI_GFX3D_CLK>,
1188			    <&gcc GCC_OXILI_AHB_CLK>,
1189			    <&gcc GCC_OXILI_GMEM_CLK>,
1190			    <&gcc GCC_BIMC_GFX_CLK>,
1191			    <&gcc GCC_BIMC_GPU_CLK>,
1192			    <&gcc GFX3D_CLK_SRC>;
1193			power-domains = <&gcc OXILI_GDSC>;
1194			operating-points-v2 = <&gpu_opp_table>;
1195			iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1196
1197			gpu_opp_table: opp-table {
1198				compatible = "operating-points-v2";
1199
1200				opp-400000000 {
1201					opp-hz = /bits/ 64 <400000000>;
1202				};
1203				opp-19200000 {
1204					opp-hz = /bits/ 64 <19200000>;
1205				};
1206			};
1207		};
1208
1209		venus: video-codec@1d00000 {
1210			compatible = "qcom,msm8916-venus";
1211			reg = <0x01d00000 0xff000>;
1212			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1213			power-domains = <&gcc VENUS_GDSC>;
1214			clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1215				 <&gcc GCC_VENUS0_AHB_CLK>,
1216				 <&gcc GCC_VENUS0_AXI_CLK>;
1217			clock-names = "core", "iface", "bus";
1218			iommus = <&apps_iommu 5>;
1219			memory-region = <&venus_mem>;
1220			status = "okay";
1221
1222			video-decoder {
1223				compatible = "venus-decoder";
1224			};
1225
1226			video-encoder {
1227				compatible = "venus-encoder";
1228			};
1229		};
1230
1231		apps_iommu: iommu@1ef0000 {
1232			#address-cells = <1>;
1233			#size-cells = <1>;
1234			#iommu-cells = <1>;
1235			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1236			ranges = <0 0x01e20000 0x20000>;
1237			reg = <0x01ef0000 0x3000>;
1238			clocks = <&gcc GCC_SMMU_CFG_CLK>,
1239				 <&gcc GCC_APSS_TCU_CLK>;
1240			clock-names = "iface", "bus";
1241			qcom,iommu-secure-id = <17>;
1242
1243			// vfe:
1244			iommu-ctx@3000 {
1245				compatible = "qcom,msm-iommu-v1-sec";
1246				reg = <0x3000 0x1000>;
1247				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1248			};
1249
1250			// mdp_0:
1251			iommu-ctx@4000 {
1252				compatible = "qcom,msm-iommu-v1-ns";
1253				reg = <0x4000 0x1000>;
1254				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1255			};
1256
1257			// venus_ns:
1258			iommu-ctx@5000 {
1259				compatible = "qcom,msm-iommu-v1-sec";
1260				reg = <0x5000 0x1000>;
1261				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1262			};
1263		};
1264
1265		gpu_iommu: iommu@1f08000 {
1266			#address-cells = <1>;
1267			#size-cells = <1>;
1268			#iommu-cells = <1>;
1269			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1270			ranges = <0 0x01f08000 0x10000>;
1271			clocks = <&gcc GCC_SMMU_CFG_CLK>,
1272				 <&gcc GCC_GFX_TCU_CLK>;
1273			clock-names = "iface", "bus";
1274			qcom,iommu-secure-id = <18>;
1275
1276			// gfx3d_user:
1277			iommu-ctx@1000 {
1278				compatible = "qcom,msm-iommu-v1-ns";
1279				reg = <0x1000 0x1000>;
1280				interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1281			};
1282
1283			// gfx3d_priv:
1284			iommu-ctx@2000 {
1285				compatible = "qcom,msm-iommu-v1-ns";
1286				reg = <0x2000 0x1000>;
1287				interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1288			};
1289		};
1290
1291		spmi_bus: spmi@200f000 {
1292			compatible = "qcom,spmi-pmic-arb";
1293			reg = <0x0200f000 0x001000>,
1294			      <0x02400000 0x400000>,
1295			      <0x02c00000 0x400000>,
1296			      <0x03800000 0x200000>,
1297			      <0x0200a000 0x002100>;
1298			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1299			interrupt-names = "periph_irq";
1300			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1301			qcom,ee = <0>;
1302			qcom,channel = <0>;
1303			#address-cells = <2>;
1304			#size-cells = <0>;
1305			interrupt-controller;
1306			#interrupt-cells = <4>;
1307		};
1308
1309		mpss: remoteproc@4080000 {
1310			compatible = "qcom,msm8916-mss-pil";
1311			reg = <0x04080000 0x100>,
1312			      <0x04020000 0x040>;
1313
1314			reg-names = "qdsp6", "rmb";
1315
1316			interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1317					      <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1318					      <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1319					      <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1320					      <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1321			interrupt-names = "wdog", "fatal", "ready",
1322					  "handover", "stop-ack";
1323
1324			power-domains = <&rpmpd MSM8916_VDDCX>,
1325					<&rpmpd MSM8916_VDDMX>;
1326			power-domain-names = "cx", "mx";
1327
1328			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1329				 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1330				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1331				 <&xo_board>;
1332			clock-names = "iface", "bus", "mem", "xo";
1333
1334			qcom,smem-states = <&hexagon_smp2p_out 0>;
1335			qcom,smem-state-names = "stop";
1336
1337			resets = <&scm 0>;
1338			reset-names = "mss_restart";
1339
1340			qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1341
1342			status = "disabled";
1343
1344			mba {
1345				memory-region = <&mba_mem>;
1346			};
1347
1348			mpss {
1349				memory-region = <&mpss_mem>;
1350			};
1351
1352			smd-edge {
1353				interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1354
1355				qcom,smd-edge = <0>;
1356				qcom,ipc = <&apcs 8 12>;
1357				qcom,remote-pid = <1>;
1358
1359				label = "hexagon";
1360
1361				fastrpc {
1362					compatible = "qcom,fastrpc";
1363					qcom,smd-channels = "fastrpcsmd-apps-dsp";
1364					label = "adsp";
1365
1366					#address-cells = <1>;
1367					#size-cells = <0>;
1368
1369					cb@1 {
1370						compatible = "qcom,fastrpc-compute-cb";
1371						reg = <1>;
1372					};
1373				};
1374			};
1375		};
1376
1377		sound: sound@7702000 {
1378			status = "disabled";
1379			compatible = "qcom,apq8016-sbc-sndcard";
1380			reg = <0x07702000 0x4>, <0x07702004 0x4>;
1381			reg-names = "mic-iomux", "spkr-iomux";
1382		};
1383
1384		lpass: audio-controller@7708000 {
1385			status = "disabled";
1386			compatible = "qcom,lpass-cpu-apq8016";
1387
1388			/*
1389			 * Note: Unlike the name would suggest, the SEC_I2S_CLK
1390			 * is actually only used by Tertiary MI2S while
1391			 * Primary/Secondary MI2S both use the PRI_I2S_CLK.
1392			 */
1393			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1394				 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
1395				 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
1396				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1397				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1398				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1399				 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
1400
1401			clock-names = "ahbix-clk",
1402					"pcnoc-mport-clk",
1403					"pcnoc-sway-clk",
1404					"mi2s-bit-clk0",
1405					"mi2s-bit-clk1",
1406					"mi2s-bit-clk2",
1407					"mi2s-bit-clk3";
1408			#sound-dai-cells = <1>;
1409
1410			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1411			interrupt-names = "lpass-irq-lpaif";
1412			reg = <0x07708000 0x10000>;
1413			reg-names = "lpass-lpaif";
1414
1415			#address-cells = <1>;
1416			#size-cells = <0>;
1417		};
1418
1419		lpass_codec: audio-codec@771c000 {
1420			compatible = "qcom,msm8916-wcd-digital-codec";
1421			reg = <0x0771c000 0x400>;
1422			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1423				 <&gcc GCC_CODEC_DIGCODEC_CLK>;
1424			clock-names = "ahbix-clk", "mclk";
1425			#sound-dai-cells = <1>;
1426		};
1427
1428		sdhc_1: sdhci@7824000 {
1429			compatible = "qcom,sdhci-msm-v4";
1430			reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1431			reg-names = "hc_mem", "core_mem";
1432
1433			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1434				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1435			interrupt-names = "hc_irq", "pwr_irq";
1436			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
1437				 <&gcc GCC_SDCC1_AHB_CLK>,
1438				 <&xo_board>;
1439			clock-names = "core", "iface", "xo";
1440			mmc-ddr-1_8v;
1441			bus-width = <8>;
1442			non-removable;
1443			status = "disabled";
1444		};
1445
1446		sdhc_2: sdhci@7864000 {
1447			compatible = "qcom,sdhci-msm-v4";
1448			reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1449			reg-names = "hc_mem", "core_mem";
1450
1451			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1452				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1453			interrupt-names = "hc_irq", "pwr_irq";
1454			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
1455				 <&gcc GCC_SDCC2_AHB_CLK>,
1456				 <&xo_board>;
1457			clock-names = "core", "iface", "xo";
1458			bus-width = <4>;
1459			status = "disabled";
1460		};
1461
1462		blsp_dma: dma-controller@7884000 {
1463			compatible = "qcom,bam-v1.7.0";
1464			reg = <0x07884000 0x23000>;
1465			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1466			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1467			clock-names = "bam_clk";
1468			#dma-cells = <1>;
1469			qcom,ee = <0>;
1470			status = "disabled";
1471		};
1472
1473		blsp1_uart1: serial@78af000 {
1474			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1475			reg = <0x078af000 0x200>;
1476			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1477			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1478			clock-names = "core", "iface";
1479			dmas = <&blsp_dma 1>, <&blsp_dma 0>;
1480			dma-names = "rx", "tx";
1481			pinctrl-names = "default", "sleep";
1482			pinctrl-0 = <&blsp1_uart1_default>;
1483			pinctrl-1 = <&blsp1_uart1_sleep>;
1484			status = "disabled";
1485		};
1486
1487		blsp1_uart2: serial@78b0000 {
1488			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1489			reg = <0x078b0000 0x200>;
1490			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1491			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1492			clock-names = "core", "iface";
1493			dmas = <&blsp_dma 3>, <&blsp_dma 2>;
1494			dma-names = "rx", "tx";
1495			pinctrl-names = "default", "sleep";
1496			pinctrl-0 = <&blsp1_uart2_default>;
1497			pinctrl-1 = <&blsp1_uart2_sleep>;
1498			status = "disabled";
1499		};
1500
1501		blsp_i2c1: i2c@78b5000 {
1502			compatible = "qcom,i2c-qup-v2.2.1";
1503			reg = <0x078b5000 0x500>;
1504			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1505			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1506				 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
1507			clock-names = "iface", "core";
1508			pinctrl-names = "default", "sleep";
1509			pinctrl-0 = <&i2c1_default>;
1510			pinctrl-1 = <&i2c1_sleep>;
1511			#address-cells = <1>;
1512			#size-cells = <0>;
1513			status = "disabled";
1514		};
1515
1516		blsp_spi1: spi@78b5000 {
1517			compatible = "qcom,spi-qup-v2.2.1";
1518			reg = <0x078b5000 0x500>;
1519			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1520			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1521				 <&gcc GCC_BLSP1_AHB_CLK>;
1522			clock-names = "core", "iface";
1523			dmas = <&blsp_dma 5>, <&blsp_dma 4>;
1524			dma-names = "rx", "tx";
1525			pinctrl-names = "default", "sleep";
1526			pinctrl-0 = <&spi1_default>;
1527			pinctrl-1 = <&spi1_sleep>;
1528			#address-cells = <1>;
1529			#size-cells = <0>;
1530			status = "disabled";
1531		};
1532
1533		blsp_i2c2: i2c@78b6000 {
1534			compatible = "qcom,i2c-qup-v2.2.1";
1535			reg = <0x078b6000 0x500>;
1536			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1537			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1538				 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
1539			clock-names = "iface", "core";
1540			pinctrl-names = "default", "sleep";
1541			pinctrl-0 = <&i2c2_default>;
1542			pinctrl-1 = <&i2c2_sleep>;
1543			#address-cells = <1>;
1544			#size-cells = <0>;
1545			status = "disabled";
1546		};
1547
1548		blsp_spi2: spi@78b6000 {
1549			compatible = "qcom,spi-qup-v2.2.1";
1550			reg = <0x078b6000 0x500>;
1551			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1552			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1553				 <&gcc GCC_BLSP1_AHB_CLK>;
1554			clock-names = "core", "iface";
1555			dmas = <&blsp_dma 7>, <&blsp_dma 6>;
1556			dma-names = "rx", "tx";
1557			pinctrl-names = "default", "sleep";
1558			pinctrl-0 = <&spi2_default>;
1559			pinctrl-1 = <&spi2_sleep>;
1560			#address-cells = <1>;
1561			#size-cells = <0>;
1562			status = "disabled";
1563		};
1564
1565		blsp_i2c3: i2c@78b7000 {
1566			compatible = "qcom,i2c-qup-v2.2.1";
1567			reg = <0x078b7000 0x500>;
1568			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1569			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1570				 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
1571			clock-names = "iface", "core";
1572			pinctrl-names = "default", "sleep";
1573			pinctrl-0 = <&i2c3_default>;
1574			pinctrl-1 = <&i2c3_sleep>;
1575			#address-cells = <1>;
1576			#size-cells = <0>;
1577			status = "disabled";
1578		};
1579
1580		blsp_spi3: spi@78b7000 {
1581			compatible = "qcom,spi-qup-v2.2.1";
1582			reg = <0x078b7000 0x500>;
1583			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1584			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1585				 <&gcc GCC_BLSP1_AHB_CLK>;
1586			clock-names = "core", "iface";
1587			dmas = <&blsp_dma 9>, <&blsp_dma 8>;
1588			dma-names = "rx", "tx";
1589			pinctrl-names = "default", "sleep";
1590			pinctrl-0 = <&spi3_default>;
1591			pinctrl-1 = <&spi3_sleep>;
1592			#address-cells = <1>;
1593			#size-cells = <0>;
1594			status = "disabled";
1595		};
1596
1597		blsp_i2c4: i2c@78b8000 {
1598			compatible = "qcom,i2c-qup-v2.2.1";
1599			reg = <0x078b8000 0x500>;
1600			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1601			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1602				 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
1603			clock-names = "iface", "core";
1604			pinctrl-names = "default", "sleep";
1605			pinctrl-0 = <&i2c4_default>;
1606			pinctrl-1 = <&i2c4_sleep>;
1607			#address-cells = <1>;
1608			#size-cells = <0>;
1609			status = "disabled";
1610		};
1611
1612		blsp_spi4: spi@78b8000 {
1613			compatible = "qcom,spi-qup-v2.2.1";
1614			reg = <0x078b8000 0x500>;
1615			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1616			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1617				 <&gcc GCC_BLSP1_AHB_CLK>;
1618			clock-names = "core", "iface";
1619			dmas = <&blsp_dma 11>, <&blsp_dma 10>;
1620			dma-names = "rx", "tx";
1621			pinctrl-names = "default", "sleep";
1622			pinctrl-0 = <&spi4_default>;
1623			pinctrl-1 = <&spi4_sleep>;
1624			#address-cells = <1>;
1625			#size-cells = <0>;
1626			status = "disabled";
1627		};
1628
1629		blsp_i2c5: i2c@78b9000 {
1630			compatible = "qcom,i2c-qup-v2.2.1";
1631			reg = <0x078b9000 0x500>;
1632			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1633			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1634				 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
1635			clock-names = "iface", "core";
1636			pinctrl-names = "default", "sleep";
1637			pinctrl-0 = <&i2c5_default>;
1638			pinctrl-1 = <&i2c5_sleep>;
1639			#address-cells = <1>;
1640			#size-cells = <0>;
1641			status = "disabled";
1642		};
1643
1644		blsp_spi5: spi@78b9000 {
1645			compatible = "qcom,spi-qup-v2.2.1";
1646			reg = <0x078b9000 0x500>;
1647			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1648			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
1649				 <&gcc GCC_BLSP1_AHB_CLK>;
1650			clock-names = "core", "iface";
1651			dmas = <&blsp_dma 13>, <&blsp_dma 12>;
1652			dma-names = "rx", "tx";
1653			pinctrl-names = "default", "sleep";
1654			pinctrl-0 = <&spi5_default>;
1655			pinctrl-1 = <&spi5_sleep>;
1656			#address-cells = <1>;
1657			#size-cells = <0>;
1658			status = "disabled";
1659		};
1660
1661		blsp_i2c6: i2c@78ba000 {
1662			compatible = "qcom,i2c-qup-v2.2.1";
1663			reg = <0x078ba000 0x500>;
1664			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1665			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1666				 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
1667			clock-names = "iface", "core";
1668			pinctrl-names = "default", "sleep";
1669			pinctrl-0 = <&i2c6_default>;
1670			pinctrl-1 = <&i2c6_sleep>;
1671			#address-cells = <1>;
1672			#size-cells = <0>;
1673			status = "disabled";
1674		};
1675
1676		blsp_spi6: spi@78ba000 {
1677			compatible = "qcom,spi-qup-v2.2.1";
1678			reg = <0x078ba000 0x500>;
1679			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1680			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
1681				 <&gcc GCC_BLSP1_AHB_CLK>;
1682			clock-names = "core", "iface";
1683			dmas = <&blsp_dma 15>, <&blsp_dma 14>;
1684			dma-names = "rx", "tx";
1685			pinctrl-names = "default", "sleep";
1686			pinctrl-0 = <&spi6_default>;
1687			pinctrl-1 = <&spi6_sleep>;
1688			#address-cells = <1>;
1689			#size-cells = <0>;
1690			status = "disabled";
1691		};
1692
1693		usb: usb@78d9000 {
1694			compatible = "qcom,ci-hdrc";
1695			reg = <0x078d9000 0x200>,
1696			      <0x078d9200 0x200>;
1697			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1698				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1699			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1700				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
1701			clock-names = "iface", "core";
1702			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1703			assigned-clock-rates = <80000000>;
1704			resets = <&gcc GCC_USB_HS_BCR>;
1705			reset-names = "core";
1706			phy_type = "ulpi";
1707			dr_mode = "otg";
1708			hnp-disable;
1709			srp-disable;
1710			adp-disable;
1711			ahb-burst-config = <0>;
1712			phy-names = "usb-phy";
1713			phys = <&usb_hs_phy>;
1714			status = "disabled";
1715			#reset-cells = <1>;
1716
1717			ulpi {
1718				usb_hs_phy: phy {
1719					compatible = "qcom,usb-hs-phy-msm8916",
1720						     "qcom,usb-hs-phy";
1721					#phy-cells = <0>;
1722					clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
1723					clock-names = "ref", "sleep";
1724					resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
1725					reset-names = "phy", "por";
1726					qcom,init-seq = /bits/ 8 <0x0 0x44
1727						0x1 0x6b 0x2 0x24 0x3 0x13>;
1728				};
1729			};
1730		};
1731
1732		pronto: remoteproc@a21b000 {
1733			compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1734			reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1735			reg-names = "ccu", "dxe", "pmu";
1736
1737			memory-region = <&wcnss_mem>;
1738
1739			interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1740					      <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1741					      <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1742					      <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1743					      <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1744			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1745
1746			power-domains = <&rpmpd MSM8916_VDDCX>,
1747					<&rpmpd MSM8916_VDDMX>;
1748			power-domain-names = "cx", "mx";
1749
1750			qcom,smem-states = <&wcnss_smp2p_out 0>;
1751			qcom,smem-state-names = "stop";
1752
1753			pinctrl-names = "default";
1754			pinctrl-0 = <&wcnss_pin_a>;
1755
1756			status = "disabled";
1757
1758			iris {
1759				compatible = "qcom,wcn3620";
1760
1761				clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1762				clock-names = "xo";
1763			};
1764
1765			smd-edge {
1766				interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
1767
1768				qcom,ipc = <&apcs 8 17>;
1769				qcom,smd-edge = <6>;
1770				qcom,remote-pid = <4>;
1771
1772				label = "pronto";
1773
1774				wcnss_ctrl: wcnss {
1775					compatible = "qcom,wcnss";
1776					qcom,smd-channels = "WCNSS_CTRL";
1777
1778					qcom,mmio = <&pronto>;
1779
1780					bt {
1781						compatible = "qcom,wcnss-bt";
1782					};
1783
1784					wifi {
1785						compatible = "qcom,wcnss-wlan";
1786
1787						interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1788							     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1789						interrupt-names = "tx", "rx";
1790
1791						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1792						qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1793					};
1794				};
1795			};
1796		};
1797
1798		intc: interrupt-controller@b000000 {
1799			compatible = "qcom,msm-qgic2";
1800			interrupt-controller;
1801			#interrupt-cells = <3>;
1802			reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
1803			      <0x0b001000 0x1000>, <0x0b004000 0x2000>;
1804			interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1805		};
1806
1807		apcs: mailbox@b011000 {
1808			compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
1809			reg = <0x0b011000 0x1000>;
1810			#mbox-cells = <1>;
1811			clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
1812			clock-names = "pll", "aux";
1813			#clock-cells = <0>;
1814		};
1815
1816		a53pll: clock@b016000 {
1817			compatible = "qcom,msm8916-a53pll";
1818			reg = <0x0b016000 0x40>;
1819			#clock-cells = <0>;
1820		};
1821
1822		timer@b020000 {
1823			#address-cells = <1>;
1824			#size-cells = <1>;
1825			ranges;
1826			compatible = "arm,armv7-timer-mem";
1827			reg = <0x0b020000 0x1000>;
1828			clock-frequency = <19200000>;
1829
1830			frame@b021000 {
1831				frame-number = <0>;
1832				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1833					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1834				reg = <0x0b021000 0x1000>,
1835				      <0x0b022000 0x1000>;
1836			};
1837
1838			frame@b023000 {
1839				frame-number = <1>;
1840				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1841				reg = <0x0b023000 0x1000>;
1842				status = "disabled";
1843			};
1844
1845			frame@b024000 {
1846				frame-number = <2>;
1847				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1848				reg = <0x0b024000 0x1000>;
1849				status = "disabled";
1850			};
1851
1852			frame@b025000 {
1853				frame-number = <3>;
1854				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1855				reg = <0x0b025000 0x1000>;
1856				status = "disabled";
1857			};
1858
1859			frame@b026000 {
1860				frame-number = <4>;
1861				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1862				reg = <0x0b026000 0x1000>;
1863				status = "disabled";
1864			};
1865
1866			frame@b027000 {
1867				frame-number = <5>;
1868				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1869				reg = <0x0b027000 0x1000>;
1870				status = "disabled";
1871			};
1872
1873			frame@b028000 {
1874				frame-number = <6>;
1875				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1876				reg = <0x0b028000 0x1000>;
1877				status = "disabled";
1878			};
1879		};
1880	};
1881
1882	thermal-zones {
1883		cpu0-1-thermal {
1884			polling-delay-passive = <250>;
1885			polling-delay = <1000>;
1886
1887			thermal-sensors = <&tsens 5>;
1888
1889			trips {
1890				cpu0_1_alert0: trip-point0 {
1891					temperature = <75000>;
1892					hysteresis = <2000>;
1893					type = "passive";
1894				};
1895				cpu0_1_crit: cpu_crit {
1896					temperature = <110000>;
1897					hysteresis = <2000>;
1898					type = "critical";
1899				};
1900			};
1901
1902			cooling-maps {
1903				map0 {
1904					trip = <&cpu0_1_alert0>;
1905					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1906							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1907							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1908							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1909				};
1910			};
1911		};
1912
1913		cpu2-3-thermal {
1914			polling-delay-passive = <250>;
1915			polling-delay = <1000>;
1916
1917			thermal-sensors = <&tsens 4>;
1918
1919			trips {
1920				cpu2_3_alert0: trip-point0 {
1921					temperature = <75000>;
1922					hysteresis = <2000>;
1923					type = "passive";
1924				};
1925				cpu2_3_crit: cpu_crit {
1926					temperature = <110000>;
1927					hysteresis = <2000>;
1928					type = "critical";
1929				};
1930			};
1931
1932			cooling-maps {
1933				map0 {
1934					trip = <&cpu2_3_alert0>;
1935					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1936							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1937							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1938							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1939				};
1940			};
1941		};
1942
1943		gpu-thermal {
1944			polling-delay-passive = <250>;
1945			polling-delay = <1000>;
1946
1947			thermal-sensors = <&tsens 2>;
1948
1949			trips {
1950				gpu_alert0: trip-point0 {
1951					temperature = <75000>;
1952					hysteresis = <2000>;
1953					type = "passive";
1954				};
1955				gpu_crit: gpu_crit {
1956					temperature = <95000>;
1957					hysteresis = <2000>;
1958					type = "critical";
1959				};
1960			};
1961		};
1962
1963		camera-thermal {
1964			polling-delay-passive = <250>;
1965			polling-delay = <1000>;
1966
1967			thermal-sensors = <&tsens 1>;
1968
1969			trips {
1970				cam_alert0: trip-point0 {
1971					temperature = <75000>;
1972					hysteresis = <2000>;
1973					type = "hot";
1974				};
1975			};
1976		};
1977
1978		modem-thermal {
1979			polling-delay-passive = <250>;
1980			polling-delay = <1000>;
1981
1982			thermal-sensors = <&tsens 0>;
1983
1984			trips {
1985				modem_alert0: trip-point0 {
1986					temperature = <85000>;
1987					hysteresis = <2000>;
1988					type = "hot";
1989				};
1990			};
1991		};
1992
1993	};
1994
1995	timer {
1996		compatible = "arm,armv8-timer";
1997		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1998			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1999			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2000			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2001	};
2002};
2003
2004#include "msm8916-pins.dtsi"
2005