1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sm8250.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/power/qcom-aoss-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,apr.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/sound/qcom,q6afe.h> 21#include <dt-bindings/thermal/thermal.h> 22#include <dt-bindings/clock/qcom,videocc-sm8250.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 i2c16 = &i2c16; 48 i2c17 = &i2c17; 49 i2c18 = &i2c18; 50 i2c19 = &i2c19; 51 spi0 = &spi0; 52 spi1 = &spi1; 53 spi2 = &spi2; 54 spi3 = &spi3; 55 spi4 = &spi4; 56 spi5 = &spi5; 57 spi6 = &spi6; 58 spi7 = &spi7; 59 spi8 = &spi8; 60 spi9 = &spi9; 61 spi10 = &spi10; 62 spi11 = &spi11; 63 spi12 = &spi12; 64 spi13 = &spi13; 65 spi14 = &spi14; 66 spi15 = &spi15; 67 spi16 = &spi16; 68 spi17 = &spi17; 69 spi18 = &spi18; 70 spi19 = &spi19; 71 }; 72 73 chosen { }; 74 75 clocks { 76 xo_board: xo-board { 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <38400000>; 80 clock-output-names = "xo_board"; 81 }; 82 83 sleep_clk: sleep-clk { 84 compatible = "fixed-clock"; 85 clock-frequency = <32768>; 86 #clock-cells = <0>; 87 }; 88 }; 89 90 cpus { 91 #address-cells = <2>; 92 #size-cells = <0>; 93 94 CPU0: cpu@0 { 95 device_type = "cpu"; 96 compatible = "qcom,kryo485"; 97 reg = <0x0 0x0>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <448>; 100 dynamic-power-coefficient = <105>; 101 next-level-cache = <&L2_0>; 102 qcom,freq-domain = <&cpufreq_hw 0>; 103 #cooling-cells = <2>; 104 L2_0: l2-cache { 105 compatible = "cache"; 106 next-level-cache = <&L3_0>; 107 L3_0: l3-cache { 108 compatible = "cache"; 109 }; 110 }; 111 }; 112 113 CPU1: cpu@100 { 114 device_type = "cpu"; 115 compatible = "qcom,kryo485"; 116 reg = <0x0 0x100>; 117 enable-method = "psci"; 118 capacity-dmips-mhz = <448>; 119 dynamic-power-coefficient = <105>; 120 next-level-cache = <&L2_100>; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 #cooling-cells = <2>; 123 L2_100: l2-cache { 124 compatible = "cache"; 125 next-level-cache = <&L3_0>; 126 }; 127 }; 128 129 CPU2: cpu@200 { 130 device_type = "cpu"; 131 compatible = "qcom,kryo485"; 132 reg = <0x0 0x200>; 133 enable-method = "psci"; 134 capacity-dmips-mhz = <448>; 135 dynamic-power-coefficient = <105>; 136 next-level-cache = <&L2_200>; 137 qcom,freq-domain = <&cpufreq_hw 0>; 138 #cooling-cells = <2>; 139 L2_200: l2-cache { 140 compatible = "cache"; 141 next-level-cache = <&L3_0>; 142 }; 143 }; 144 145 CPU3: cpu@300 { 146 device_type = "cpu"; 147 compatible = "qcom,kryo485"; 148 reg = <0x0 0x300>; 149 enable-method = "psci"; 150 capacity-dmips-mhz = <448>; 151 dynamic-power-coefficient = <105>; 152 next-level-cache = <&L2_300>; 153 qcom,freq-domain = <&cpufreq_hw 0>; 154 #cooling-cells = <2>; 155 L2_300: l2-cache { 156 compatible = "cache"; 157 next-level-cache = <&L3_0>; 158 }; 159 }; 160 161 CPU4: cpu@400 { 162 device_type = "cpu"; 163 compatible = "qcom,kryo485"; 164 reg = <0x0 0x400>; 165 enable-method = "psci"; 166 capacity-dmips-mhz = <1024>; 167 dynamic-power-coefficient = <379>; 168 next-level-cache = <&L2_400>; 169 qcom,freq-domain = <&cpufreq_hw 1>; 170 #cooling-cells = <2>; 171 L2_400: l2-cache { 172 compatible = "cache"; 173 next-level-cache = <&L3_0>; 174 }; 175 }; 176 177 CPU5: cpu@500 { 178 device_type = "cpu"; 179 compatible = "qcom,kryo485"; 180 reg = <0x0 0x500>; 181 enable-method = "psci"; 182 capacity-dmips-mhz = <1024>; 183 dynamic-power-coefficient = <379>; 184 next-level-cache = <&L2_500>; 185 qcom,freq-domain = <&cpufreq_hw 1>; 186 #cooling-cells = <2>; 187 L2_500: l2-cache { 188 compatible = "cache"; 189 next-level-cache = <&L3_0>; 190 }; 191 192 }; 193 194 CPU6: cpu@600 { 195 device_type = "cpu"; 196 compatible = "qcom,kryo485"; 197 reg = <0x0 0x600>; 198 enable-method = "psci"; 199 capacity-dmips-mhz = <1024>; 200 dynamic-power-coefficient = <379>; 201 next-level-cache = <&L2_600>; 202 qcom,freq-domain = <&cpufreq_hw 1>; 203 #cooling-cells = <2>; 204 L2_600: l2-cache { 205 compatible = "cache"; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 CPU7: cpu@700 { 211 device_type = "cpu"; 212 compatible = "qcom,kryo485"; 213 reg = <0x0 0x700>; 214 enable-method = "psci"; 215 capacity-dmips-mhz = <1024>; 216 dynamic-power-coefficient = <444>; 217 next-level-cache = <&L2_700>; 218 qcom,freq-domain = <&cpufreq_hw 2>; 219 #cooling-cells = <2>; 220 L2_700: l2-cache { 221 compatible = "cache"; 222 next-level-cache = <&L3_0>; 223 }; 224 }; 225 226 cpu-map { 227 cluster0 { 228 core0 { 229 cpu = <&CPU0>; 230 }; 231 232 core1 { 233 cpu = <&CPU1>; 234 }; 235 236 core2 { 237 cpu = <&CPU2>; 238 }; 239 240 core3 { 241 cpu = <&CPU3>; 242 }; 243 244 core4 { 245 cpu = <&CPU4>; 246 }; 247 248 core5 { 249 cpu = <&CPU5>; 250 }; 251 252 core6 { 253 cpu = <&CPU6>; 254 }; 255 256 core7 { 257 cpu = <&CPU7>; 258 }; 259 }; 260 }; 261 }; 262 263 firmware { 264 scm: scm { 265 compatible = "qcom,scm"; 266 #reset-cells = <1>; 267 }; 268 }; 269 270 memory@80000000 { 271 device_type = "memory"; 272 /* We expect the bootloader to fill in the size */ 273 reg = <0x0 0x80000000 0x0 0x0>; 274 }; 275 276 mmcx_reg: mmcx-reg { 277 compatible = "regulator-fixed-domain"; 278 power-domains = <&rpmhpd SM8250_MMCX>; 279 required-opps = <&rpmhpd_opp_low_svs>; 280 regulator-name = "MMCX"; 281 }; 282 283 pmu { 284 compatible = "arm,armv8-pmuv3"; 285 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 286 }; 287 288 psci { 289 compatible = "arm,psci-1.0"; 290 method = "smc"; 291 }; 292 293 reserved-memory { 294 #address-cells = <2>; 295 #size-cells = <2>; 296 ranges; 297 298 hyp_mem: memory@80000000 { 299 reg = <0x0 0x80000000 0x0 0x600000>; 300 no-map; 301 }; 302 303 xbl_aop_mem: memory@80700000 { 304 reg = <0x0 0x80700000 0x0 0x160000>; 305 no-map; 306 }; 307 308 cmd_db: memory@80860000 { 309 compatible = "qcom,cmd-db"; 310 reg = <0x0 0x80860000 0x0 0x20000>; 311 no-map; 312 }; 313 314 smem_mem: memory@80900000 { 315 reg = <0x0 0x80900000 0x0 0x200000>; 316 no-map; 317 }; 318 319 removed_mem: memory@80b00000 { 320 reg = <0x0 0x80b00000 0x0 0x5300000>; 321 no-map; 322 }; 323 324 camera_mem: memory@86200000 { 325 reg = <0x0 0x86200000 0x0 0x500000>; 326 no-map; 327 }; 328 329 wlan_mem: memory@86700000 { 330 reg = <0x0 0x86700000 0x0 0x100000>; 331 no-map; 332 }; 333 334 ipa_fw_mem: memory@86800000 { 335 reg = <0x0 0x86800000 0x0 0x10000>; 336 no-map; 337 }; 338 339 ipa_gsi_mem: memory@86810000 { 340 reg = <0x0 0x86810000 0x0 0xa000>; 341 no-map; 342 }; 343 344 gpu_mem: memory@8681a000 { 345 reg = <0x0 0x8681a000 0x0 0x2000>; 346 no-map; 347 }; 348 349 npu_mem: memory@86900000 { 350 reg = <0x0 0x86900000 0x0 0x500000>; 351 no-map; 352 }; 353 354 video_mem: memory@86e00000 { 355 reg = <0x0 0x86e00000 0x0 0x500000>; 356 no-map; 357 }; 358 359 cvp_mem: memory@87300000 { 360 reg = <0x0 0x87300000 0x0 0x500000>; 361 no-map; 362 }; 363 364 cdsp_mem: memory@87800000 { 365 reg = <0x0 0x87800000 0x0 0x1400000>; 366 no-map; 367 }; 368 369 slpi_mem: memory@88c00000 { 370 reg = <0x0 0x88c00000 0x0 0x1500000>; 371 no-map; 372 }; 373 374 adsp_mem: memory@8a100000 { 375 reg = <0x0 0x8a100000 0x0 0x1d00000>; 376 no-map; 377 }; 378 379 spss_mem: memory@8be00000 { 380 reg = <0x0 0x8be00000 0x0 0x100000>; 381 no-map; 382 }; 383 384 cdsp_secure_heap: memory@8bf00000 { 385 reg = <0x0 0x8bf00000 0x0 0x4600000>; 386 no-map; 387 }; 388 }; 389 390 smem { 391 compatible = "qcom,smem"; 392 memory-region = <&smem_mem>; 393 hwlocks = <&tcsr_mutex 3>; 394 }; 395 396 smp2p-adsp { 397 compatible = "qcom,smp2p"; 398 qcom,smem = <443>, <429>; 399 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 400 IPCC_MPROC_SIGNAL_SMP2P 401 IRQ_TYPE_EDGE_RISING>; 402 mboxes = <&ipcc IPCC_CLIENT_LPASS 403 IPCC_MPROC_SIGNAL_SMP2P>; 404 405 qcom,local-pid = <0>; 406 qcom,remote-pid = <2>; 407 408 smp2p_adsp_out: master-kernel { 409 qcom,entry-name = "master-kernel"; 410 #qcom,smem-state-cells = <1>; 411 }; 412 413 smp2p_adsp_in: slave-kernel { 414 qcom,entry-name = "slave-kernel"; 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 }; 418 }; 419 420 smp2p-cdsp { 421 compatible = "qcom,smp2p"; 422 qcom,smem = <94>, <432>; 423 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 424 IPCC_MPROC_SIGNAL_SMP2P 425 IRQ_TYPE_EDGE_RISING>; 426 mboxes = <&ipcc IPCC_CLIENT_CDSP 427 IPCC_MPROC_SIGNAL_SMP2P>; 428 429 qcom,local-pid = <0>; 430 qcom,remote-pid = <5>; 431 432 smp2p_cdsp_out: master-kernel { 433 qcom,entry-name = "master-kernel"; 434 #qcom,smem-state-cells = <1>; 435 }; 436 437 smp2p_cdsp_in: slave-kernel { 438 qcom,entry-name = "slave-kernel"; 439 interrupt-controller; 440 #interrupt-cells = <2>; 441 }; 442 }; 443 444 smp2p-slpi { 445 compatible = "qcom,smp2p"; 446 qcom,smem = <481>, <430>; 447 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 448 IPCC_MPROC_SIGNAL_SMP2P 449 IRQ_TYPE_EDGE_RISING>; 450 mboxes = <&ipcc IPCC_CLIENT_SLPI 451 IPCC_MPROC_SIGNAL_SMP2P>; 452 453 qcom,local-pid = <0>; 454 qcom,remote-pid = <3>; 455 456 smp2p_slpi_out: master-kernel { 457 qcom,entry-name = "master-kernel"; 458 #qcom,smem-state-cells = <1>; 459 }; 460 461 smp2p_slpi_in: slave-kernel { 462 qcom,entry-name = "slave-kernel"; 463 interrupt-controller; 464 #interrupt-cells = <2>; 465 }; 466 }; 467 468 soc: soc@0 { 469 #address-cells = <2>; 470 #size-cells = <2>; 471 ranges = <0 0 0 0 0x10 0>; 472 dma-ranges = <0 0 0 0 0x10 0>; 473 compatible = "simple-bus"; 474 475 gcc: clock-controller@100000 { 476 compatible = "qcom,gcc-sm8250"; 477 reg = <0x0 0x00100000 0x0 0x1f0000>; 478 #clock-cells = <1>; 479 #reset-cells = <1>; 480 #power-domain-cells = <1>; 481 clock-names = "bi_tcxo", 482 "bi_tcxo_ao", 483 "sleep_clk"; 484 clocks = <&rpmhcc RPMH_CXO_CLK>, 485 <&rpmhcc RPMH_CXO_CLK_A>, 486 <&sleep_clk>; 487 }; 488 489 ipcc: mailbox@408000 { 490 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 491 reg = <0 0x00408000 0 0x1000>; 492 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 493 interrupt-controller; 494 #interrupt-cells = <3>; 495 #mbox-cells = <2>; 496 }; 497 498 rng: rng@793000 { 499 compatible = "qcom,prng-ee"; 500 reg = <0 0x00793000 0 0x1000>; 501 clocks = <&gcc GCC_PRNG_AHB_CLK>; 502 clock-names = "core"; 503 }; 504 505 qup_opp_table: qup-opp-table { 506 compatible = "operating-points-v2"; 507 508 opp-50000000 { 509 opp-hz = /bits/ 64 <50000000>; 510 required-opps = <&rpmhpd_opp_min_svs>; 511 }; 512 513 opp-75000000 { 514 opp-hz = /bits/ 64 <75000000>; 515 required-opps = <&rpmhpd_opp_low_svs>; 516 }; 517 518 opp-120000000 { 519 opp-hz = /bits/ 64 <120000000>; 520 required-opps = <&rpmhpd_opp_svs>; 521 }; 522 }; 523 524 gpi_dma2: dma-controller@800000 { 525 compatible = "qcom,sm8250-gpi-dma"; 526 reg = <0 0x00800000 0 0x70000>; 527 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 537 dma-channels = <10>; 538 dma-channel-mask = <0x3f>; 539 iommus = <&apps_smmu 0x76 0x0>; 540 #dma-cells = <3>; 541 status = "disabled"; 542 }; 543 544 qupv3_id_2: geniqup@8c0000 { 545 compatible = "qcom,geni-se-qup"; 546 reg = <0x0 0x008c0000 0x0 0x6000>; 547 clock-names = "m-ahb", "s-ahb"; 548 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 549 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 550 #address-cells = <2>; 551 #size-cells = <2>; 552 iommus = <&apps_smmu 0x63 0x0>; 553 ranges; 554 status = "disabled"; 555 556 i2c14: i2c@880000 { 557 compatible = "qcom,geni-i2c"; 558 reg = <0 0x00880000 0 0x4000>; 559 clock-names = "se"; 560 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&qup_i2c14_default>; 563 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 564 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 565 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 566 dma-names = "tx", "rx"; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 status = "disabled"; 570 }; 571 572 spi14: spi@880000 { 573 compatible = "qcom,geni-spi"; 574 reg = <0 0x00880000 0 0x4000>; 575 clock-names = "se"; 576 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 577 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 578 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 579 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 580 dma-names = "tx", "rx"; 581 power-domains = <&rpmhpd SM8250_CX>; 582 operating-points-v2 = <&qup_opp_table>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 status = "disabled"; 586 }; 587 588 i2c15: i2c@884000 { 589 compatible = "qcom,geni-i2c"; 590 reg = <0 0x00884000 0 0x4000>; 591 clock-names = "se"; 592 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 593 pinctrl-names = "default"; 594 pinctrl-0 = <&qup_i2c15_default>; 595 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 596 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 597 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 598 dma-names = "tx", "rx"; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 status = "disabled"; 602 }; 603 604 spi15: spi@884000 { 605 compatible = "qcom,geni-spi"; 606 reg = <0 0x00884000 0 0x4000>; 607 clock-names = "se"; 608 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 609 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 610 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 611 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 612 dma-names = "tx", "rx"; 613 power-domains = <&rpmhpd SM8250_CX>; 614 operating-points-v2 = <&qup_opp_table>; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 status = "disabled"; 618 }; 619 620 i2c16: i2c@888000 { 621 compatible = "qcom,geni-i2c"; 622 reg = <0 0x00888000 0 0x4000>; 623 clock-names = "se"; 624 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 625 pinctrl-names = "default"; 626 pinctrl-0 = <&qup_i2c16_default>; 627 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 628 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 629 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 630 dma-names = "tx", "rx"; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 status = "disabled"; 634 }; 635 636 spi16: spi@888000 { 637 compatible = "qcom,geni-spi"; 638 reg = <0 0x00888000 0 0x4000>; 639 clock-names = "se"; 640 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 641 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 642 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 643 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 644 dma-names = "tx", "rx"; 645 power-domains = <&rpmhpd SM8250_CX>; 646 operating-points-v2 = <&qup_opp_table>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 status = "disabled"; 650 }; 651 652 i2c17: i2c@88c000 { 653 compatible = "qcom,geni-i2c"; 654 reg = <0 0x0088c000 0 0x4000>; 655 clock-names = "se"; 656 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 657 pinctrl-names = "default"; 658 pinctrl-0 = <&qup_i2c17_default>; 659 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 660 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 661 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 662 dma-names = "tx", "rx"; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 status = "disabled"; 666 }; 667 668 spi17: spi@88c000 { 669 compatible = "qcom,geni-spi"; 670 reg = <0 0x0088c000 0 0x4000>; 671 clock-names = "se"; 672 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 673 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 674 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 675 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 676 dma-names = "tx", "rx"; 677 power-domains = <&rpmhpd SM8250_CX>; 678 operating-points-v2 = <&qup_opp_table>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 status = "disabled"; 682 }; 683 684 uart17: serial@88c000 { 685 compatible = "qcom,geni-uart"; 686 reg = <0 0x0088c000 0 0x4000>; 687 clock-names = "se"; 688 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 689 pinctrl-names = "default"; 690 pinctrl-0 = <&qup_uart17_default>; 691 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 692 power-domains = <&rpmhpd SM8250_CX>; 693 operating-points-v2 = <&qup_opp_table>; 694 status = "disabled"; 695 }; 696 697 i2c18: i2c@890000 { 698 compatible = "qcom,geni-i2c"; 699 reg = <0 0x00890000 0 0x4000>; 700 clock-names = "se"; 701 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 702 pinctrl-names = "default"; 703 pinctrl-0 = <&qup_i2c18_default>; 704 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 705 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 706 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 707 dma-names = "tx", "rx"; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 status = "disabled"; 711 }; 712 713 spi18: spi@890000 { 714 compatible = "qcom,geni-spi"; 715 reg = <0 0x00890000 0 0x4000>; 716 clock-names = "se"; 717 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 718 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 719 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 720 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 721 dma-names = "tx", "rx"; 722 power-domains = <&rpmhpd SM8250_CX>; 723 operating-points-v2 = <&qup_opp_table>; 724 #address-cells = <1>; 725 #size-cells = <0>; 726 status = "disabled"; 727 }; 728 729 uart18: serial@890000 { 730 compatible = "qcom,geni-uart"; 731 reg = <0 0x00890000 0 0x4000>; 732 clock-names = "se"; 733 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 734 pinctrl-names = "default"; 735 pinctrl-0 = <&qup_uart18_default>; 736 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 737 power-domains = <&rpmhpd SM8250_CX>; 738 operating-points-v2 = <&qup_opp_table>; 739 status = "disabled"; 740 }; 741 742 i2c19: i2c@894000 { 743 compatible = "qcom,geni-i2c"; 744 reg = <0 0x00894000 0 0x4000>; 745 clock-names = "se"; 746 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 747 pinctrl-names = "default"; 748 pinctrl-0 = <&qup_i2c19_default>; 749 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 750 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 751 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 752 dma-names = "tx", "rx"; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 status = "disabled"; 756 }; 757 758 spi19: spi@894000 { 759 compatible = "qcom,geni-spi"; 760 reg = <0 0x00894000 0 0x4000>; 761 clock-names = "se"; 762 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 763 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 764 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 765 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 766 dma-names = "tx", "rx"; 767 power-domains = <&rpmhpd SM8250_CX>; 768 operating-points-v2 = <&qup_opp_table>; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 status = "disabled"; 772 }; 773 }; 774 775 gpi_dma0: dma-controller@900000 { 776 compatible = "qcom,sm8250-gpi-dma"; 777 reg = <0 0x00900000 0 0x70000>; 778 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 791 dma-channels = <15>; 792 dma-channel-mask = <0x7ff>; 793 iommus = <&apps_smmu 0x5b6 0x0>; 794 #dma-cells = <3>; 795 status = "disabled"; 796 }; 797 798 qupv3_id_0: geniqup@9c0000 { 799 compatible = "qcom,geni-se-qup"; 800 reg = <0x0 0x009c0000 0x0 0x6000>; 801 clock-names = "m-ahb", "s-ahb"; 802 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 803 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 804 #address-cells = <2>; 805 #size-cells = <2>; 806 iommus = <&apps_smmu 0x5a3 0x0>; 807 ranges; 808 status = "disabled"; 809 810 i2c0: i2c@980000 { 811 compatible = "qcom,geni-i2c"; 812 reg = <0 0x00980000 0 0x4000>; 813 clock-names = "se"; 814 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 815 pinctrl-names = "default"; 816 pinctrl-0 = <&qup_i2c0_default>; 817 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 818 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 819 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 820 dma-names = "tx", "rx"; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 status = "disabled"; 824 }; 825 826 spi0: spi@980000 { 827 compatible = "qcom,geni-spi"; 828 reg = <0 0x00980000 0 0x4000>; 829 clock-names = "se"; 830 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 831 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 832 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 833 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 834 dma-names = "tx", "rx"; 835 power-domains = <&rpmhpd SM8250_CX>; 836 operating-points-v2 = <&qup_opp_table>; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 status = "disabled"; 840 }; 841 842 i2c1: i2c@984000 { 843 compatible = "qcom,geni-i2c"; 844 reg = <0 0x00984000 0 0x4000>; 845 clock-names = "se"; 846 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 847 pinctrl-names = "default"; 848 pinctrl-0 = <&qup_i2c1_default>; 849 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 850 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 851 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 852 dma-names = "tx", "rx"; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 status = "disabled"; 856 }; 857 858 spi1: spi@984000 { 859 compatible = "qcom,geni-spi"; 860 reg = <0 0x00984000 0 0x4000>; 861 clock-names = "se"; 862 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 863 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 864 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 865 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 866 dma-names = "tx", "rx"; 867 power-domains = <&rpmhpd SM8250_CX>; 868 operating-points-v2 = <&qup_opp_table>; 869 #address-cells = <1>; 870 #size-cells = <0>; 871 status = "disabled"; 872 }; 873 874 i2c2: i2c@988000 { 875 compatible = "qcom,geni-i2c"; 876 reg = <0 0x00988000 0 0x4000>; 877 clock-names = "se"; 878 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 879 pinctrl-names = "default"; 880 pinctrl-0 = <&qup_i2c2_default>; 881 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 882 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 883 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 884 dma-names = "tx", "rx"; 885 #address-cells = <1>; 886 #size-cells = <0>; 887 status = "disabled"; 888 }; 889 890 spi2: spi@988000 { 891 compatible = "qcom,geni-spi"; 892 reg = <0 0x00988000 0 0x4000>; 893 clock-names = "se"; 894 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 895 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 896 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 897 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 898 dma-names = "tx", "rx"; 899 power-domains = <&rpmhpd SM8250_CX>; 900 operating-points-v2 = <&qup_opp_table>; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 status = "disabled"; 904 }; 905 906 uart2: serial@988000 { 907 compatible = "qcom,geni-debug-uart"; 908 reg = <0 0x00988000 0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 911 pinctrl-names = "default"; 912 pinctrl-0 = <&qup_uart2_default>; 913 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 914 power-domains = <&rpmhpd SM8250_CX>; 915 operating-points-v2 = <&qup_opp_table>; 916 status = "disabled"; 917 }; 918 919 i2c3: i2c@98c000 { 920 compatible = "qcom,geni-i2c"; 921 reg = <0 0x0098c000 0 0x4000>; 922 clock-names = "se"; 923 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 924 pinctrl-names = "default"; 925 pinctrl-0 = <&qup_i2c3_default>; 926 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 927 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 928 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 929 dma-names = "tx", "rx"; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 status = "disabled"; 933 }; 934 935 spi3: spi@98c000 { 936 compatible = "qcom,geni-spi"; 937 reg = <0 0x0098c000 0 0x4000>; 938 clock-names = "se"; 939 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 940 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 941 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 942 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 943 dma-names = "tx", "rx"; 944 power-domains = <&rpmhpd SM8250_CX>; 945 operating-points-v2 = <&qup_opp_table>; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 status = "disabled"; 949 }; 950 951 i2c4: i2c@990000 { 952 compatible = "qcom,geni-i2c"; 953 reg = <0 0x00990000 0 0x4000>; 954 clock-names = "se"; 955 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 956 pinctrl-names = "default"; 957 pinctrl-0 = <&qup_i2c4_default>; 958 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 959 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 960 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 961 dma-names = "tx", "rx"; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 status = "disabled"; 965 }; 966 967 spi4: spi@990000 { 968 compatible = "qcom,geni-spi"; 969 reg = <0 0x00990000 0 0x4000>; 970 clock-names = "se"; 971 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 972 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 973 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 974 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 975 dma-names = "tx", "rx"; 976 power-domains = <&rpmhpd SM8250_CX>; 977 operating-points-v2 = <&qup_opp_table>; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 status = "disabled"; 981 }; 982 983 i2c5: i2c@994000 { 984 compatible = "qcom,geni-i2c"; 985 reg = <0 0x00994000 0 0x4000>; 986 clock-names = "se"; 987 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 988 pinctrl-names = "default"; 989 pinctrl-0 = <&qup_i2c5_default>; 990 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 991 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 992 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 993 dma-names = "tx", "rx"; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 status = "disabled"; 997 }; 998 999 spi5: spi@994000 { 1000 compatible = "qcom,geni-spi"; 1001 reg = <0 0x00994000 0 0x4000>; 1002 clock-names = "se"; 1003 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1004 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1005 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1006 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1007 dma-names = "tx", "rx"; 1008 power-domains = <&rpmhpd SM8250_CX>; 1009 operating-points-v2 = <&qup_opp_table>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 status = "disabled"; 1013 }; 1014 1015 i2c6: i2c@998000 { 1016 compatible = "qcom,geni-i2c"; 1017 reg = <0 0x00998000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_i2c6_default>; 1022 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1023 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1024 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1025 dma-names = "tx", "rx"; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 status = "disabled"; 1029 }; 1030 1031 spi6: spi@998000 { 1032 compatible = "qcom,geni-spi"; 1033 reg = <0 0x00998000 0 0x4000>; 1034 clock-names = "se"; 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1036 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1037 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1038 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1039 dma-names = "tx", "rx"; 1040 power-domains = <&rpmhpd SM8250_CX>; 1041 operating-points-v2 = <&qup_opp_table>; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 status = "disabled"; 1045 }; 1046 1047 uart6: serial@998000 { 1048 compatible = "qcom,geni-uart"; 1049 reg = <0 0x00998000 0 0x4000>; 1050 clock-names = "se"; 1051 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1052 pinctrl-names = "default"; 1053 pinctrl-0 = <&qup_uart6_default>; 1054 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1055 power-domains = <&rpmhpd SM8250_CX>; 1056 operating-points-v2 = <&qup_opp_table>; 1057 status = "disabled"; 1058 }; 1059 1060 i2c7: i2c@99c000 { 1061 compatible = "qcom,geni-i2c"; 1062 reg = <0 0x0099c000 0 0x4000>; 1063 clock-names = "se"; 1064 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1065 pinctrl-names = "default"; 1066 pinctrl-0 = <&qup_i2c7_default>; 1067 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1068 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1069 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1070 dma-names = "tx", "rx"; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 status = "disabled"; 1074 }; 1075 1076 spi7: spi@99c000 { 1077 compatible = "qcom,geni-spi"; 1078 reg = <0 0x0099c000 0 0x4000>; 1079 clock-names = "se"; 1080 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1081 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1082 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1083 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1084 dma-names = "tx", "rx"; 1085 power-domains = <&rpmhpd SM8250_CX>; 1086 operating-points-v2 = <&qup_opp_table>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 status = "disabled"; 1090 }; 1091 }; 1092 1093 gpi_dma1: dma-controller@a00000 { 1094 compatible = "qcom,sm8250-gpi-dma"; 1095 reg = <0 0x00a00000 0 0x70000>; 1096 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1106 dma-channels = <10>; 1107 dma-channel-mask = <0x3f>; 1108 iommus = <&apps_smmu 0x56 0x0>; 1109 #dma-cells = <3>; 1110 status = "disabled"; 1111 }; 1112 1113 qupv3_id_1: geniqup@ac0000 { 1114 compatible = "qcom,geni-se-qup"; 1115 reg = <0x0 0x00ac0000 0x0 0x6000>; 1116 clock-names = "m-ahb", "s-ahb"; 1117 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1118 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1119 #address-cells = <2>; 1120 #size-cells = <2>; 1121 iommus = <&apps_smmu 0x43 0x0>; 1122 ranges; 1123 status = "disabled"; 1124 1125 i2c8: i2c@a80000 { 1126 compatible = "qcom,geni-i2c"; 1127 reg = <0 0x00a80000 0 0x4000>; 1128 clock-names = "se"; 1129 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1130 pinctrl-names = "default"; 1131 pinctrl-0 = <&qup_i2c8_default>; 1132 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1133 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1134 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1135 dma-names = "tx", "rx"; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 status = "disabled"; 1139 }; 1140 1141 spi8: spi@a80000 { 1142 compatible = "qcom,geni-spi"; 1143 reg = <0 0x00a80000 0 0x4000>; 1144 clock-names = "se"; 1145 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1146 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1147 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1148 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1149 dma-names = "tx", "rx"; 1150 power-domains = <&rpmhpd SM8250_CX>; 1151 operating-points-v2 = <&qup_opp_table>; 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 status = "disabled"; 1155 }; 1156 1157 i2c9: i2c@a84000 { 1158 compatible = "qcom,geni-i2c"; 1159 reg = <0 0x00a84000 0 0x4000>; 1160 clock-names = "se"; 1161 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&qup_i2c9_default>; 1164 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1165 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1166 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1167 dma-names = "tx", "rx"; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 status = "disabled"; 1171 }; 1172 1173 spi9: spi@a84000 { 1174 compatible = "qcom,geni-spi"; 1175 reg = <0 0x00a84000 0 0x4000>; 1176 clock-names = "se"; 1177 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1178 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1179 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1180 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1181 dma-names = "tx", "rx"; 1182 power-domains = <&rpmhpd SM8250_CX>; 1183 operating-points-v2 = <&qup_opp_table>; 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 status = "disabled"; 1187 }; 1188 1189 i2c10: i2c@a88000 { 1190 compatible = "qcom,geni-i2c"; 1191 reg = <0 0x00a88000 0 0x4000>; 1192 clock-names = "se"; 1193 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1194 pinctrl-names = "default"; 1195 pinctrl-0 = <&qup_i2c10_default>; 1196 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1197 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1198 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1199 dma-names = "tx", "rx"; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 status = "disabled"; 1203 }; 1204 1205 spi10: spi@a88000 { 1206 compatible = "qcom,geni-spi"; 1207 reg = <0 0x00a88000 0 0x4000>; 1208 clock-names = "se"; 1209 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1210 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1211 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1212 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1213 dma-names = "tx", "rx"; 1214 power-domains = <&rpmhpd SM8250_CX>; 1215 operating-points-v2 = <&qup_opp_table>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 status = "disabled"; 1219 }; 1220 1221 i2c11: i2c@a8c000 { 1222 compatible = "qcom,geni-i2c"; 1223 reg = <0 0x00a8c000 0 0x4000>; 1224 clock-names = "se"; 1225 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1226 pinctrl-names = "default"; 1227 pinctrl-0 = <&qup_i2c11_default>; 1228 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1229 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1230 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1231 dma-names = "tx", "rx"; 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 status = "disabled"; 1235 }; 1236 1237 spi11: spi@a8c000 { 1238 compatible = "qcom,geni-spi"; 1239 reg = <0 0x00a8c000 0 0x4000>; 1240 clock-names = "se"; 1241 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1242 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1243 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1244 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1245 dma-names = "tx", "rx"; 1246 power-domains = <&rpmhpd SM8250_CX>; 1247 operating-points-v2 = <&qup_opp_table>; 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 status = "disabled"; 1251 }; 1252 1253 i2c12: i2c@a90000 { 1254 compatible = "qcom,geni-i2c"; 1255 reg = <0 0x00a90000 0 0x4000>; 1256 clock-names = "se"; 1257 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1258 pinctrl-names = "default"; 1259 pinctrl-0 = <&qup_i2c12_default>; 1260 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1261 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1262 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1263 dma-names = "tx", "rx"; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 status = "disabled"; 1267 }; 1268 1269 spi12: spi@a90000 { 1270 compatible = "qcom,geni-spi"; 1271 reg = <0 0x00a90000 0 0x4000>; 1272 clock-names = "se"; 1273 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1274 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1275 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1276 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1277 dma-names = "tx", "rx"; 1278 power-domains = <&rpmhpd SM8250_CX>; 1279 operating-points-v2 = <&qup_opp_table>; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 status = "disabled"; 1283 }; 1284 1285 uart12: serial@a90000 { 1286 compatible = "qcom,geni-debug-uart"; 1287 reg = <0x0 0x00a90000 0x0 0x4000>; 1288 clock-names = "se"; 1289 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&qup_uart12_default>; 1292 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1293 power-domains = <&rpmhpd SM8250_CX>; 1294 operating-points-v2 = <&qup_opp_table>; 1295 status = "disabled"; 1296 }; 1297 1298 i2c13: i2c@a94000 { 1299 compatible = "qcom,geni-i2c"; 1300 reg = <0 0x00a94000 0 0x4000>; 1301 clock-names = "se"; 1302 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&qup_i2c13_default>; 1305 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1306 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1307 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1308 dma-names = "tx", "rx"; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 status = "disabled"; 1312 }; 1313 1314 spi13: spi@a94000 { 1315 compatible = "qcom,geni-spi"; 1316 reg = <0 0x00a94000 0 0x4000>; 1317 clock-names = "se"; 1318 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1319 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1320 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1321 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1322 dma-names = "tx", "rx"; 1323 power-domains = <&rpmhpd SM8250_CX>; 1324 operating-points-v2 = <&qup_opp_table>; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 status = "disabled"; 1328 }; 1329 }; 1330 1331 config_noc: interconnect@1500000 { 1332 compatible = "qcom,sm8250-config-noc"; 1333 reg = <0 0x01500000 0 0xa580>; 1334 #interconnect-cells = <1>; 1335 qcom,bcm-voters = <&apps_bcm_voter>; 1336 }; 1337 1338 system_noc: interconnect@1620000 { 1339 compatible = "qcom,sm8250-system-noc"; 1340 reg = <0 0x01620000 0 0x1c200>; 1341 #interconnect-cells = <1>; 1342 qcom,bcm-voters = <&apps_bcm_voter>; 1343 }; 1344 1345 mc_virt: interconnect@163d000 { 1346 compatible = "qcom,sm8250-mc-virt"; 1347 reg = <0 0x0163d000 0 0x1000>; 1348 #interconnect-cells = <1>; 1349 qcom,bcm-voters = <&apps_bcm_voter>; 1350 }; 1351 1352 aggre1_noc: interconnect@16e0000 { 1353 compatible = "qcom,sm8250-aggre1-noc"; 1354 reg = <0 0x016e0000 0 0x1f180>; 1355 #interconnect-cells = <1>; 1356 qcom,bcm-voters = <&apps_bcm_voter>; 1357 }; 1358 1359 aggre2_noc: interconnect@1700000 { 1360 compatible = "qcom,sm8250-aggre2-noc"; 1361 reg = <0 0x01700000 0 0x33000>; 1362 #interconnect-cells = <1>; 1363 qcom,bcm-voters = <&apps_bcm_voter>; 1364 }; 1365 1366 compute_noc: interconnect@1733000 { 1367 compatible = "qcom,sm8250-compute-noc"; 1368 reg = <0 0x01733000 0 0xa180>; 1369 #interconnect-cells = <1>; 1370 qcom,bcm-voters = <&apps_bcm_voter>; 1371 }; 1372 1373 mmss_noc: interconnect@1740000 { 1374 compatible = "qcom,sm8250-mmss-noc"; 1375 reg = <0 0x01740000 0 0x1f080>; 1376 #interconnect-cells = <1>; 1377 qcom,bcm-voters = <&apps_bcm_voter>; 1378 }; 1379 1380 pcie0: pci@1c00000 { 1381 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1382 reg = <0 0x01c00000 0 0x3000>, 1383 <0 0x60000000 0 0xf1d>, 1384 <0 0x60000f20 0 0xa8>, 1385 <0 0x60001000 0 0x1000>, 1386 <0 0x60100000 0 0x100000>; 1387 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1388 device_type = "pci"; 1389 linux,pci-domain = <0>; 1390 bus-range = <0x00 0xff>; 1391 num-lanes = <1>; 1392 1393 #address-cells = <3>; 1394 #size-cells = <2>; 1395 1396 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1397 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1398 1399 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1400 interrupt-names = "msi"; 1401 #interrupt-cells = <1>; 1402 interrupt-map-mask = <0 0 0 0x7>; 1403 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1404 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1405 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1406 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1407 1408 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1409 <&gcc GCC_PCIE_0_AUX_CLK>, 1410 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1411 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1412 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1413 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1414 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1415 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1416 clock-names = "pipe", 1417 "aux", 1418 "cfg", 1419 "bus_master", 1420 "bus_slave", 1421 "slave_q2a", 1422 "tbu", 1423 "ddrss_sf_tbu"; 1424 1425 iommus = <&apps_smmu 0x1c00 0x7f>; 1426 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1427 <0x100 &apps_smmu 0x1c01 0x1>; 1428 1429 resets = <&gcc GCC_PCIE_0_BCR>; 1430 reset-names = "pci"; 1431 1432 power-domains = <&gcc PCIE_0_GDSC>; 1433 1434 phys = <&pcie0_lane>; 1435 phy-names = "pciephy"; 1436 1437 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 1438 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 1439 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&pcie0_default_state>; 1442 dma-coherent; 1443 1444 status = "disabled"; 1445 }; 1446 1447 pcie0_phy: phy@1c06000 { 1448 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1449 reg = <0 0x01c06000 0 0x1c0>; 1450 #address-cells = <2>; 1451 #size-cells = <2>; 1452 ranges; 1453 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1454 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1455 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1456 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1457 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1458 1459 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1460 reset-names = "phy"; 1461 1462 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1463 assigned-clock-rates = <100000000>; 1464 1465 status = "disabled"; 1466 1467 pcie0_lane: phy@1c06200 { 1468 reg = <0 0x1c06200 0 0x170>, /* tx */ 1469 <0 0x1c06400 0 0x200>, /* rx */ 1470 <0 0x1c06800 0 0x1f0>, /* pcs */ 1471 <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1472 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1473 clock-names = "pipe0"; 1474 1475 #phy-cells = <0>; 1476 1477 #clock-cells = <0>; 1478 clock-output-names = "pcie_0_pipe_clk"; 1479 }; 1480 }; 1481 1482 pcie1: pci@1c08000 { 1483 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1484 reg = <0 0x01c08000 0 0x3000>, 1485 <0 0x40000000 0 0xf1d>, 1486 <0 0x40000f20 0 0xa8>, 1487 <0 0x40001000 0 0x1000>, 1488 <0 0x40100000 0 0x100000>; 1489 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1490 device_type = "pci"; 1491 linux,pci-domain = <1>; 1492 bus-range = <0x00 0xff>; 1493 num-lanes = <2>; 1494 1495 #address-cells = <3>; 1496 #size-cells = <2>; 1497 1498 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1499 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1500 1501 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1502 interrupt-names = "msi"; 1503 #interrupt-cells = <1>; 1504 interrupt-map-mask = <0 0 0 0x7>; 1505 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1506 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1507 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1508 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1509 1510 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1511 <&gcc GCC_PCIE_1_AUX_CLK>, 1512 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1513 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1514 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1515 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1516 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1517 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1518 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1519 clock-names = "pipe", 1520 "aux", 1521 "cfg", 1522 "bus_master", 1523 "bus_slave", 1524 "slave_q2a", 1525 "ref", 1526 "tbu", 1527 "ddrss_sf_tbu"; 1528 1529 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1530 assigned-clock-rates = <19200000>; 1531 1532 iommus = <&apps_smmu 0x1c80 0x7f>; 1533 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1534 <0x100 &apps_smmu 0x1c81 0x1>; 1535 1536 resets = <&gcc GCC_PCIE_1_BCR>; 1537 reset-names = "pci"; 1538 1539 power-domains = <&gcc PCIE_1_GDSC>; 1540 1541 phys = <&pcie1_lane>; 1542 phy-names = "pciephy"; 1543 1544 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 1545 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 1546 1547 pinctrl-names = "default"; 1548 pinctrl-0 = <&pcie1_default_state>; 1549 dma-coherent; 1550 1551 status = "disabled"; 1552 }; 1553 1554 pcie1_phy: phy@1c0e000 { 1555 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 1556 reg = <0 0x01c0e000 0 0x1c0>; 1557 #address-cells = <2>; 1558 #size-cells = <2>; 1559 ranges; 1560 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1561 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1562 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1563 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1564 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1565 1566 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1567 reset-names = "phy"; 1568 1569 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1570 assigned-clock-rates = <100000000>; 1571 1572 status = "disabled"; 1573 1574 pcie1_lane: phy@1c0e200 { 1575 reg = <0 0x1c0e200 0 0x170>, /* tx0 */ 1576 <0 0x1c0e400 0 0x200>, /* rx0 */ 1577 <0 0x1c0ea00 0 0x1f0>, /* pcs */ 1578 <0 0x1c0e600 0 0x170>, /* tx1 */ 1579 <0 0x1c0e800 0 0x200>, /* rx1 */ 1580 <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1581 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1582 clock-names = "pipe0"; 1583 1584 #phy-cells = <0>; 1585 1586 #clock-cells = <0>; 1587 clock-output-names = "pcie_1_pipe_clk"; 1588 }; 1589 }; 1590 1591 pcie2: pci@1c10000 { 1592 compatible = "qcom,pcie-sm8250", "snps,dw-pcie"; 1593 reg = <0 0x01c10000 0 0x3000>, 1594 <0 0x64000000 0 0xf1d>, 1595 <0 0x64000f20 0 0xa8>, 1596 <0 0x64001000 0 0x1000>, 1597 <0 0x64100000 0 0x100000>; 1598 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1599 device_type = "pci"; 1600 linux,pci-domain = <2>; 1601 bus-range = <0x00 0xff>; 1602 num-lanes = <2>; 1603 1604 #address-cells = <3>; 1605 #size-cells = <2>; 1606 1607 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, 1608 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 1609 1610 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1611 interrupt-names = "msi"; 1612 #interrupt-cells = <1>; 1613 interrupt-map-mask = <0 0 0 0x7>; 1614 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1615 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1616 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1617 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1618 1619 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 1620 <&gcc GCC_PCIE_2_AUX_CLK>, 1621 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1622 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 1623 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 1624 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 1625 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1626 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1627 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1628 clock-names = "pipe", 1629 "aux", 1630 "cfg", 1631 "bus_master", 1632 "bus_slave", 1633 "slave_q2a", 1634 "ref", 1635 "tbu", 1636 "ddrss_sf_tbu"; 1637 1638 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 1639 assigned-clock-rates = <19200000>; 1640 1641 iommus = <&apps_smmu 0x1d00 0x7f>; 1642 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 1643 <0x100 &apps_smmu 0x1d01 0x1>; 1644 1645 resets = <&gcc GCC_PCIE_2_BCR>; 1646 reset-names = "pci"; 1647 1648 power-domains = <&gcc PCIE_2_GDSC>; 1649 1650 phys = <&pcie2_lane>; 1651 phy-names = "pciephy"; 1652 1653 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 1654 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 1655 1656 pinctrl-names = "default"; 1657 pinctrl-0 = <&pcie2_default_state>; 1658 dma-coherent; 1659 1660 status = "disabled"; 1661 }; 1662 1663 pcie2_phy: phy@1c16000 { 1664 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 1665 reg = <0 0x1c16000 0 0x1c0>; 1666 #address-cells = <2>; 1667 #size-cells = <2>; 1668 ranges; 1669 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1670 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 1671 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 1672 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1673 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1674 1675 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 1676 reset-names = "phy"; 1677 1678 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 1679 assigned-clock-rates = <100000000>; 1680 1681 status = "disabled"; 1682 1683 pcie2_lane: phy@1c16200 { 1684 reg = <0 0x1c16200 0 0x170>, /* tx0 */ 1685 <0 0x1c16400 0 0x200>, /* rx0 */ 1686 <0 0x1c16a00 0 0x1f0>, /* pcs */ 1687 <0 0x1c16600 0 0x170>, /* tx1 */ 1688 <0 0x1c16800 0 0x200>, /* rx1 */ 1689 <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 1690 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 1691 clock-names = "pipe0"; 1692 1693 #phy-cells = <0>; 1694 1695 #clock-cells = <0>; 1696 clock-output-names = "pcie_2_pipe_clk"; 1697 }; 1698 }; 1699 1700 ufs_mem_hc: ufshc@1d84000 { 1701 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 1702 "jedec,ufs-2.0"; 1703 reg = <0 0x01d84000 0 0x3000>; 1704 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1705 phys = <&ufs_mem_phy_lanes>; 1706 phy-names = "ufsphy"; 1707 lanes-per-direction = <2>; 1708 #reset-cells = <1>; 1709 resets = <&gcc GCC_UFS_PHY_BCR>; 1710 reset-names = "rst"; 1711 1712 power-domains = <&gcc UFS_PHY_GDSC>; 1713 1714 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 1715 1716 clock-names = 1717 "core_clk", 1718 "bus_aggr_clk", 1719 "iface_clk", 1720 "core_clk_unipro", 1721 "ref_clk", 1722 "tx_lane0_sync_clk", 1723 "rx_lane0_sync_clk", 1724 "rx_lane1_sync_clk"; 1725 clocks = 1726 <&gcc GCC_UFS_PHY_AXI_CLK>, 1727 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1728 <&gcc GCC_UFS_PHY_AHB_CLK>, 1729 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1730 <&rpmhcc RPMH_CXO_CLK>, 1731 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1732 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1733 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1734 freq-table-hz = 1735 <37500000 300000000>, 1736 <0 0>, 1737 <0 0>, 1738 <37500000 300000000>, 1739 <0 0>, 1740 <0 0>, 1741 <0 0>, 1742 <0 0>; 1743 1744 status = "disabled"; 1745 }; 1746 1747 ufs_mem_phy: phy@1d87000 { 1748 compatible = "qcom,sm8250-qmp-ufs-phy"; 1749 reg = <0 0x01d87000 0 0x1c0>; 1750 #address-cells = <2>; 1751 #size-cells = <2>; 1752 ranges; 1753 clock-names = "ref", 1754 "ref_aux"; 1755 clocks = <&rpmhcc RPMH_CXO_CLK>, 1756 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1757 1758 resets = <&ufs_mem_hc 0>; 1759 reset-names = "ufsphy"; 1760 status = "disabled"; 1761 1762 ufs_mem_phy_lanes: phy@1d87400 { 1763 reg = <0 0x01d87400 0 0x16c>, 1764 <0 0x01d87600 0 0x200>, 1765 <0 0x01d87c00 0 0x200>, 1766 <0 0x01d87800 0 0x16c>, 1767 <0 0x01d87a00 0 0x200>; 1768 #phy-cells = <0>; 1769 }; 1770 }; 1771 1772 ipa_virt: interconnect@1e00000 { 1773 compatible = "qcom,sm8250-ipa-virt"; 1774 reg = <0 0x01e00000 0 0x1000>; 1775 #interconnect-cells = <1>; 1776 qcom,bcm-voters = <&apps_bcm_voter>; 1777 }; 1778 1779 tcsr_mutex: hwlock@1f40000 { 1780 compatible = "qcom,tcsr-mutex"; 1781 reg = <0x0 0x01f40000 0x0 0x40000>; 1782 #hwlock-cells = <1>; 1783 }; 1784 1785 wsamacro: codec@3240000 { 1786 compatible = "qcom,sm8250-lpass-wsa-macro"; 1787 reg = <0 0x03240000 0 0x1000>; 1788 clocks = <&audiocc 1>, 1789 <&audiocc 0>, 1790 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1791 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1792 <&aoncc 0>, 1793 <&vamacro>; 1794 1795 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 1796 1797 #clock-cells = <0>; 1798 clock-frequency = <9600000>; 1799 clock-output-names = "mclk"; 1800 #sound-dai-cells = <1>; 1801 1802 pinctrl-names = "default"; 1803 pinctrl-0 = <&wsa_swr_active>; 1804 }; 1805 1806 swr0: soundwire-controller@3250000 { 1807 reg = <0 0x03250000 0 0x2000>; 1808 compatible = "qcom,soundwire-v1.5.1"; 1809 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1810 clocks = <&wsamacro>; 1811 clock-names = "iface"; 1812 1813 qcom,din-ports = <2>; 1814 qcom,dout-ports = <6>; 1815 1816 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 1817 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 1818 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 1819 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 1820 1821 #sound-dai-cells = <1>; 1822 #address-cells = <2>; 1823 #size-cells = <0>; 1824 }; 1825 1826 audiocc: clock-controller@3300000 { 1827 compatible = "qcom,sm8250-lpass-audiocc"; 1828 reg = <0 0x03300000 0 0x30000>; 1829 #clock-cells = <1>; 1830 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1831 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1832 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1833 clock-names = "core", "audio", "bus"; 1834 }; 1835 1836 vamacro: codec@3370000 { 1837 compatible = "qcom,sm8250-lpass-va-macro"; 1838 reg = <0 0x03370000 0 0x1000>; 1839 clocks = <&aoncc 0>, 1840 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1841 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1842 1843 clock-names = "mclk", "macro", "dcodec"; 1844 1845 #clock-cells = <0>; 1846 clock-frequency = <9600000>; 1847 clock-output-names = "fsgen"; 1848 #sound-dai-cells = <1>; 1849 }; 1850 1851 aoncc: clock-controller@3380000 { 1852 compatible = "qcom,sm8250-lpass-aoncc"; 1853 reg = <0 0x03380000 0 0x40000>; 1854 #clock-cells = <1>; 1855 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1856 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1857 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1858 clock-names = "core", "audio", "bus"; 1859 }; 1860 1861 lpass_tlmm: pinctrl@33c0000{ 1862 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 1863 reg = <0 0x033c0000 0x0 0x20000>, 1864 <0 0x03550000 0x0 0x10000>; 1865 gpio-controller; 1866 #gpio-cells = <2>; 1867 gpio-ranges = <&lpass_tlmm 0 0 14>; 1868 1869 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1870 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1871 clock-names = "core", "audio"; 1872 1873 wsa_swr_active: wsa-swr-active-pins { 1874 clk { 1875 pins = "gpio10"; 1876 function = "wsa_swr_clk"; 1877 drive-strength = <2>; 1878 slew-rate = <1>; 1879 bias-disable; 1880 }; 1881 1882 data { 1883 pins = "gpio11"; 1884 function = "wsa_swr_data"; 1885 drive-strength = <2>; 1886 slew-rate = <1>; 1887 bias-bus-hold; 1888 1889 }; 1890 }; 1891 1892 wsa_swr_sleep: wsa-swr-sleep-pins { 1893 clk { 1894 pins = "gpio10"; 1895 function = "wsa_swr_clk"; 1896 drive-strength = <2>; 1897 input-enable; 1898 bias-pull-down; 1899 }; 1900 1901 data { 1902 pins = "gpio11"; 1903 function = "wsa_swr_data"; 1904 drive-strength = <2>; 1905 input-enable; 1906 bias-pull-down; 1907 1908 }; 1909 }; 1910 1911 dmic01_active: dmic01-active-pins { 1912 clk { 1913 pins = "gpio6"; 1914 function = "dmic1_clk"; 1915 drive-strength = <8>; 1916 output-high; 1917 }; 1918 data { 1919 pins = "gpio7"; 1920 function = "dmic1_data"; 1921 drive-strength = <8>; 1922 input-enable; 1923 }; 1924 }; 1925 1926 dmic01_sleep: dmic01-sleep-pins { 1927 clk { 1928 pins = "gpio6"; 1929 function = "dmic1_clk"; 1930 drive-strength = <2>; 1931 bias-disable; 1932 output-low; 1933 }; 1934 1935 data { 1936 pins = "gpio7"; 1937 function = "dmic1_data"; 1938 drive-strength = <2>; 1939 bias-pull-down; 1940 input-enable; 1941 }; 1942 }; 1943 }; 1944 1945 gpu: gpu@3d00000 { 1946 compatible = "qcom,adreno-650.2", 1947 "qcom,adreno"; 1948 #stream-id-cells = <16>; 1949 1950 reg = <0 0x03d00000 0 0x40000>; 1951 reg-names = "kgsl_3d0_reg_memory"; 1952 1953 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1954 1955 iommus = <&adreno_smmu 0 0x401>; 1956 1957 operating-points-v2 = <&gpu_opp_table>; 1958 1959 qcom,gmu = <&gmu>; 1960 1961 status = "disabled"; 1962 1963 zap-shader { 1964 memory-region = <&gpu_mem>; 1965 }; 1966 1967 /* note: downstream checks gpu binning for 670 Mhz */ 1968 gpu_opp_table: opp-table { 1969 compatible = "operating-points-v2"; 1970 1971 opp-670000000 { 1972 opp-hz = /bits/ 64 <670000000>; 1973 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1974 }; 1975 1976 opp-587000000 { 1977 opp-hz = /bits/ 64 <587000000>; 1978 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1979 }; 1980 1981 opp-525000000 { 1982 opp-hz = /bits/ 64 <525000000>; 1983 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1984 }; 1985 1986 opp-490000000 { 1987 opp-hz = /bits/ 64 <490000000>; 1988 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1989 }; 1990 1991 opp-441600000 { 1992 opp-hz = /bits/ 64 <441600000>; 1993 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1994 }; 1995 1996 opp-400000000 { 1997 opp-hz = /bits/ 64 <400000000>; 1998 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1999 }; 2000 2001 opp-305000000 { 2002 opp-hz = /bits/ 64 <305000000>; 2003 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2004 }; 2005 }; 2006 }; 2007 2008 gmu: gmu@3d6a000 { 2009 compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2010 2011 reg = <0 0x03d6a000 0 0x30000>, 2012 <0 0x3de0000 0 0x10000>, 2013 <0 0xb290000 0 0x10000>, 2014 <0 0xb490000 0 0x10000>; 2015 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 2016 2017 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2018 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2019 interrupt-names = "hfi", "gmu"; 2020 2021 clocks = <&gpucc GPU_CC_AHB_CLK>, 2022 <&gpucc GPU_CC_CX_GMU_CLK>, 2023 <&gpucc GPU_CC_CXO_CLK>, 2024 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2025 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2026 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2027 2028 power-domains = <&gpucc GPU_CX_GDSC>, 2029 <&gpucc GPU_GX_GDSC>; 2030 power-domain-names = "cx", "gx"; 2031 2032 iommus = <&adreno_smmu 5 0x400>; 2033 2034 operating-points-v2 = <&gmu_opp_table>; 2035 2036 status = "disabled"; 2037 2038 gmu_opp_table: opp-table { 2039 compatible = "operating-points-v2"; 2040 2041 opp-200000000 { 2042 opp-hz = /bits/ 64 <200000000>; 2043 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2044 }; 2045 }; 2046 }; 2047 2048 gpucc: clock-controller@3d90000 { 2049 compatible = "qcom,sm8250-gpucc"; 2050 reg = <0 0x03d90000 0 0x9000>; 2051 clocks = <&rpmhcc RPMH_CXO_CLK>, 2052 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2053 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2054 clock-names = "bi_tcxo", 2055 "gcc_gpu_gpll0_clk_src", 2056 "gcc_gpu_gpll0_div_clk_src"; 2057 #clock-cells = <1>; 2058 #reset-cells = <1>; 2059 #power-domain-cells = <1>; 2060 }; 2061 2062 adreno_smmu: iommu@3da0000 { 2063 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 2064 reg = <0 0x03da0000 0 0x10000>; 2065 #iommu-cells = <2>; 2066 #global-interrupts = <2>; 2067 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2068 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2069 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2070 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2071 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2072 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2073 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2074 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2075 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2076 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 2077 clocks = <&gpucc GPU_CC_AHB_CLK>, 2078 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2079 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2080 clock-names = "ahb", "bus", "iface"; 2081 2082 power-domains = <&gpucc GPU_CX_GDSC>; 2083 }; 2084 2085 slpi: remoteproc@5c00000 { 2086 compatible = "qcom,sm8250-slpi-pas"; 2087 reg = <0 0x05c00000 0 0x4000>; 2088 2089 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2090 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2091 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2092 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2093 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2094 interrupt-names = "wdog", "fatal", "ready", 2095 "handover", "stop-ack"; 2096 2097 clocks = <&rpmhcc RPMH_CXO_CLK>; 2098 clock-names = "xo"; 2099 2100 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, 2101 <&rpmhpd SM8250_LCX>, 2102 <&rpmhpd SM8250_LMX>; 2103 power-domain-names = "load_state", "lcx", "lmx"; 2104 2105 memory-region = <&slpi_mem>; 2106 2107 qcom,smem-states = <&smp2p_slpi_out 0>; 2108 qcom,smem-state-names = "stop"; 2109 2110 status = "disabled"; 2111 2112 glink-edge { 2113 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2114 IPCC_MPROC_SIGNAL_GLINK_QMP 2115 IRQ_TYPE_EDGE_RISING>; 2116 mboxes = <&ipcc IPCC_CLIENT_SLPI 2117 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2118 2119 label = "slpi"; 2120 qcom,remote-pid = <3>; 2121 2122 fastrpc { 2123 compatible = "qcom,fastrpc"; 2124 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2125 label = "sdsp"; 2126 #address-cells = <1>; 2127 #size-cells = <0>; 2128 2129 compute-cb@1 { 2130 compatible = "qcom,fastrpc-compute-cb"; 2131 reg = <1>; 2132 iommus = <&apps_smmu 0x0541 0x0>; 2133 }; 2134 2135 compute-cb@2 { 2136 compatible = "qcom,fastrpc-compute-cb"; 2137 reg = <2>; 2138 iommus = <&apps_smmu 0x0542 0x0>; 2139 }; 2140 2141 compute-cb@3 { 2142 compatible = "qcom,fastrpc-compute-cb"; 2143 reg = <3>; 2144 iommus = <&apps_smmu 0x0543 0x0>; 2145 /* note: shared-cb = <4> in downstream */ 2146 }; 2147 }; 2148 }; 2149 }; 2150 2151 cdsp: remoteproc@8300000 { 2152 compatible = "qcom,sm8250-cdsp-pas"; 2153 reg = <0 0x08300000 0 0x10000>; 2154 2155 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 2156 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2157 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2158 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2159 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2160 interrupt-names = "wdog", "fatal", "ready", 2161 "handover", "stop-ack"; 2162 2163 clocks = <&rpmhcc RPMH_CXO_CLK>; 2164 clock-names = "xo"; 2165 2166 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, 2167 <&rpmhpd SM8250_CX>; 2168 power-domain-names = "load_state", "cx"; 2169 2170 memory-region = <&cdsp_mem>; 2171 2172 qcom,smem-states = <&smp2p_cdsp_out 0>; 2173 qcom,smem-state-names = "stop"; 2174 2175 status = "disabled"; 2176 2177 glink-edge { 2178 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2179 IPCC_MPROC_SIGNAL_GLINK_QMP 2180 IRQ_TYPE_EDGE_RISING>; 2181 mboxes = <&ipcc IPCC_CLIENT_CDSP 2182 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2183 2184 label = "cdsp"; 2185 qcom,remote-pid = <5>; 2186 2187 fastrpc { 2188 compatible = "qcom,fastrpc"; 2189 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2190 label = "cdsp"; 2191 #address-cells = <1>; 2192 #size-cells = <0>; 2193 2194 compute-cb@1 { 2195 compatible = "qcom,fastrpc-compute-cb"; 2196 reg = <1>; 2197 iommus = <&apps_smmu 0x1001 0x0460>; 2198 }; 2199 2200 compute-cb@2 { 2201 compatible = "qcom,fastrpc-compute-cb"; 2202 reg = <2>; 2203 iommus = <&apps_smmu 0x1002 0x0460>; 2204 }; 2205 2206 compute-cb@3 { 2207 compatible = "qcom,fastrpc-compute-cb"; 2208 reg = <3>; 2209 iommus = <&apps_smmu 0x1003 0x0460>; 2210 }; 2211 2212 compute-cb@4 { 2213 compatible = "qcom,fastrpc-compute-cb"; 2214 reg = <4>; 2215 iommus = <&apps_smmu 0x1004 0x0460>; 2216 }; 2217 2218 compute-cb@5 { 2219 compatible = "qcom,fastrpc-compute-cb"; 2220 reg = <5>; 2221 iommus = <&apps_smmu 0x1005 0x0460>; 2222 }; 2223 2224 compute-cb@6 { 2225 compatible = "qcom,fastrpc-compute-cb"; 2226 reg = <6>; 2227 iommus = <&apps_smmu 0x1006 0x0460>; 2228 }; 2229 2230 compute-cb@7 { 2231 compatible = "qcom,fastrpc-compute-cb"; 2232 reg = <7>; 2233 iommus = <&apps_smmu 0x1007 0x0460>; 2234 }; 2235 2236 compute-cb@8 { 2237 compatible = "qcom,fastrpc-compute-cb"; 2238 reg = <8>; 2239 iommus = <&apps_smmu 0x1008 0x0460>; 2240 }; 2241 2242 /* note: secure cb9 in downstream */ 2243 }; 2244 }; 2245 }; 2246 2247 sound: sound { 2248 }; 2249 2250 usb_1_hsphy: phy@88e3000 { 2251 compatible = "qcom,sm8250-usb-hs-phy", 2252 "qcom,usb-snps-hs-7nm-phy"; 2253 reg = <0 0x088e3000 0 0x400>; 2254 status = "disabled"; 2255 #phy-cells = <0>; 2256 2257 clocks = <&rpmhcc RPMH_CXO_CLK>; 2258 clock-names = "ref"; 2259 2260 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2261 }; 2262 2263 usb_2_hsphy: phy@88e4000 { 2264 compatible = "qcom,sm8250-usb-hs-phy", 2265 "qcom,usb-snps-hs-7nm-phy"; 2266 reg = <0 0x088e4000 0 0x400>; 2267 status = "disabled"; 2268 #phy-cells = <0>; 2269 2270 clocks = <&rpmhcc RPMH_CXO_CLK>; 2271 clock-names = "ref"; 2272 2273 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2274 }; 2275 2276 usb_1_qmpphy: phy@88e9000 { 2277 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 2278 reg = <0 0x088e9000 0 0x200>, 2279 <0 0x088e8000 0 0x40>, 2280 <0 0x088ea000 0 0x200>; 2281 status = "disabled"; 2282 #address-cells = <2>; 2283 #size-cells = <2>; 2284 ranges; 2285 2286 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2287 <&rpmhcc RPMH_CXO_CLK>, 2288 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2289 clock-names = "aux", "ref_clk_src", "com_aux"; 2290 2291 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2292 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2293 reset-names = "phy", "common"; 2294 2295 usb_1_ssphy: usb3-phy@88e9200 { 2296 reg = <0 0x088e9200 0 0x200>, 2297 <0 0x088e9400 0 0x200>, 2298 <0 0x088e9c00 0 0x400>, 2299 <0 0x088e9600 0 0x200>, 2300 <0 0x088e9800 0 0x200>, 2301 <0 0x088e9a00 0 0x100>; 2302 #clock-cells = <0>; 2303 #phy-cells = <0>; 2304 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2305 clock-names = "pipe0"; 2306 clock-output-names = "usb3_phy_pipe_clk_src"; 2307 }; 2308 2309 dp_phy: dp-phy@88ea200 { 2310 reg = <0 0x088ea200 0 0x200>, 2311 <0 0x088ea400 0 0x200>, 2312 <0 0x088eaa00 0 0x200>, 2313 <0 0x088ea600 0 0x200>, 2314 <0 0x088ea800 0 0x200>; 2315 #phy-cells = <0>; 2316 #clock-cells = <1>; 2317 }; 2318 }; 2319 2320 usb_2_qmpphy: phy@88eb000 { 2321 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 2322 reg = <0 0x088eb000 0 0x200>; 2323 status = "disabled"; 2324 #address-cells = <2>; 2325 #size-cells = <2>; 2326 ranges; 2327 2328 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2329 <&rpmhcc RPMH_CXO_CLK>, 2330 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2331 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2332 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2333 2334 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2335 <&gcc GCC_USB3_PHY_SEC_BCR>; 2336 reset-names = "phy", "common"; 2337 2338 usb_2_ssphy: phy@88eb200 { 2339 reg = <0 0x088eb200 0 0x200>, 2340 <0 0x088eb400 0 0x200>, 2341 <0 0x088eb800 0 0x800>; 2342 #clock-cells = <0>; 2343 #phy-cells = <0>; 2344 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2345 clock-names = "pipe0"; 2346 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2347 }; 2348 }; 2349 2350 sdhc_2: sdhci@8804000 { 2351 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 2352 reg = <0 0x08804000 0 0x1000>; 2353 2354 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2355 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2356 interrupt-names = "hc_irq", "pwr_irq"; 2357 2358 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2359 <&gcc GCC_SDCC2_APPS_CLK>, 2360 <&rpmhcc RPMH_CXO_CLK>; 2361 clock-names = "iface", "core", "xo"; 2362 iommus = <&apps_smmu 0x4a0 0x0>; 2363 qcom,dll-config = <0x0007642c>; 2364 qcom,ddr-config = <0x80040868>; 2365 power-domains = <&rpmhpd SM8250_CX>; 2366 operating-points-v2 = <&sdhc2_opp_table>; 2367 2368 status = "disabled"; 2369 2370 sdhc2_opp_table: sdhc2-opp-table { 2371 compatible = "operating-points-v2"; 2372 2373 opp-19200000 { 2374 opp-hz = /bits/ 64 <19200000>; 2375 required-opps = <&rpmhpd_opp_min_svs>; 2376 }; 2377 2378 opp-50000000 { 2379 opp-hz = /bits/ 64 <50000000>; 2380 required-opps = <&rpmhpd_opp_low_svs>; 2381 }; 2382 2383 opp-100000000 { 2384 opp-hz = /bits/ 64 <100000000>; 2385 required-opps = <&rpmhpd_opp_svs>; 2386 }; 2387 2388 opp-202000000 { 2389 opp-hz = /bits/ 64 <202000000>; 2390 required-opps = <&rpmhpd_opp_svs_l1>; 2391 }; 2392 }; 2393 }; 2394 2395 dc_noc: interconnect@90c0000 { 2396 compatible = "qcom,sm8250-dc-noc"; 2397 reg = <0 0x090c0000 0 0x4200>; 2398 #interconnect-cells = <1>; 2399 qcom,bcm-voters = <&apps_bcm_voter>; 2400 }; 2401 2402 gem_noc: interconnect@9100000 { 2403 compatible = "qcom,sm8250-gem-noc"; 2404 reg = <0 0x09100000 0 0xb4000>; 2405 #interconnect-cells = <1>; 2406 qcom,bcm-voters = <&apps_bcm_voter>; 2407 }; 2408 2409 npu_noc: interconnect@9990000 { 2410 compatible = "qcom,sm8250-npu-noc"; 2411 reg = <0 0x09990000 0 0x1600>; 2412 #interconnect-cells = <1>; 2413 qcom,bcm-voters = <&apps_bcm_voter>; 2414 }; 2415 2416 usb_1: usb@a6f8800 { 2417 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 2418 reg = <0 0x0a6f8800 0 0x400>; 2419 status = "disabled"; 2420 #address-cells = <2>; 2421 #size-cells = <2>; 2422 ranges; 2423 dma-ranges; 2424 2425 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2426 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2427 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2428 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2429 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2430 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2431 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2432 "sleep", "xo"; 2433 2434 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2435 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2436 assigned-clock-rates = <19200000>, <200000000>; 2437 2438 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2439 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2440 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2441 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2442 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2443 "dm_hs_phy_irq", "ss_phy_irq"; 2444 2445 power-domains = <&gcc USB30_PRIM_GDSC>; 2446 2447 resets = <&gcc GCC_USB30_PRIM_BCR>; 2448 2449 usb_1_dwc3: usb@a600000 { 2450 compatible = "snps,dwc3"; 2451 reg = <0 0x0a600000 0 0xcd00>; 2452 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2453 iommus = <&apps_smmu 0x0 0x0>; 2454 snps,dis_u2_susphy_quirk; 2455 snps,dis_enblslpm_quirk; 2456 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2457 phy-names = "usb2-phy", "usb3-phy"; 2458 }; 2459 }; 2460 2461 system-cache-controller@9200000 { 2462 compatible = "qcom,sm8250-llcc"; 2463 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 2464 reg-names = "llcc_base", "llcc_broadcast_base"; 2465 }; 2466 2467 usb_2: usb@a8f8800 { 2468 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 2469 reg = <0 0x0a8f8800 0 0x400>; 2470 status = "disabled"; 2471 #address-cells = <2>; 2472 #size-cells = <2>; 2473 ranges; 2474 dma-ranges; 2475 2476 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2477 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2478 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2479 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2480 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2481 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2482 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2483 "sleep", "xo"; 2484 2485 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2486 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2487 assigned-clock-rates = <19200000>, <200000000>; 2488 2489 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2490 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 2491 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2492 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 2493 interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", 2494 "dm_hs_phy_irq", "ss_phy_irq"; 2495 2496 power-domains = <&gcc USB30_SEC_GDSC>; 2497 2498 resets = <&gcc GCC_USB30_SEC_BCR>; 2499 2500 usb_2_dwc3: usb@a800000 { 2501 compatible = "snps,dwc3"; 2502 reg = <0 0x0a800000 0 0xcd00>; 2503 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2504 iommus = <&apps_smmu 0x20 0>; 2505 snps,dis_u2_susphy_quirk; 2506 snps,dis_enblslpm_quirk; 2507 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2508 phy-names = "usb2-phy", "usb3-phy"; 2509 }; 2510 }; 2511 2512 venus: video-codec@aa00000 { 2513 compatible = "qcom,sm8250-venus"; 2514 reg = <0 0x0aa00000 0 0x100000>; 2515 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2516 power-domains = <&videocc MVS0C_GDSC>, 2517 <&videocc MVS0_GDSC>, 2518 <&rpmhpd SM8250_MX>; 2519 power-domain-names = "venus", "vcodec0", "mx"; 2520 operating-points-v2 = <&venus_opp_table>; 2521 2522 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 2523 <&videocc VIDEO_CC_MVS0C_CLK>, 2524 <&videocc VIDEO_CC_MVS0_CLK>; 2525 clock-names = "iface", "core", "vcodec0_core"; 2526 2527 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 2528 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 2529 interconnect-names = "cpu-cfg", "video-mem"; 2530 2531 iommus = <&apps_smmu 0x2100 0x0400>; 2532 memory-region = <&video_mem>; 2533 2534 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 2535 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 2536 reset-names = "bus", "core"; 2537 2538 status = "disabled"; 2539 2540 video-decoder { 2541 compatible = "venus-decoder"; 2542 }; 2543 2544 video-encoder { 2545 compatible = "venus-encoder"; 2546 }; 2547 2548 venus_opp_table: venus-opp-table { 2549 compatible = "operating-points-v2"; 2550 2551 opp-720000000 { 2552 opp-hz = /bits/ 64 <720000000>; 2553 required-opps = <&rpmhpd_opp_low_svs>; 2554 }; 2555 2556 opp-1014000000 { 2557 opp-hz = /bits/ 64 <1014000000>; 2558 required-opps = <&rpmhpd_opp_svs>; 2559 }; 2560 2561 opp-1098000000 { 2562 opp-hz = /bits/ 64 <1098000000>; 2563 required-opps = <&rpmhpd_opp_svs_l1>; 2564 }; 2565 2566 opp-1332000000 { 2567 opp-hz = /bits/ 64 <1332000000>; 2568 required-opps = <&rpmhpd_opp_nom>; 2569 }; 2570 }; 2571 }; 2572 2573 videocc: clock-controller@abf0000 { 2574 compatible = "qcom,sm8250-videocc"; 2575 reg = <0 0x0abf0000 0 0x10000>; 2576 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 2577 <&rpmhcc RPMH_CXO_CLK>, 2578 <&rpmhcc RPMH_CXO_CLK_A>; 2579 mmcx-supply = <&mmcx_reg>; 2580 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 2581 #clock-cells = <1>; 2582 #reset-cells = <1>; 2583 #power-domain-cells = <1>; 2584 }; 2585 2586 mdss: mdss@ae00000 { 2587 compatible = "qcom,sm8250-mdss"; 2588 reg = <0 0x0ae00000 0 0x1000>; 2589 reg-names = "mdss"; 2590 2591 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 2592 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 2593 interconnect-names = "mdp0-mem", "mdp1-mem"; 2594 2595 power-domains = <&dispcc MDSS_GDSC>; 2596 2597 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2598 <&gcc GCC_DISP_HF_AXI_CLK>, 2599 <&gcc GCC_DISP_SF_AXI_CLK>, 2600 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2601 clock-names = "iface", "bus", "nrt_bus", "core"; 2602 2603 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2604 assigned-clock-rates = <460000000>; 2605 2606 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2607 interrupt-controller; 2608 #interrupt-cells = <1>; 2609 2610 iommus = <&apps_smmu 0x820 0x402>; 2611 2612 status = "disabled"; 2613 2614 #address-cells = <2>; 2615 #size-cells = <2>; 2616 ranges; 2617 2618 mdss_mdp: mdp@ae01000 { 2619 compatible = "qcom,sm8250-dpu"; 2620 reg = <0 0x0ae01000 0 0x8f000>, 2621 <0 0x0aeb0000 0 0x2008>; 2622 reg-names = "mdp", "vbif"; 2623 2624 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2625 <&gcc GCC_DISP_HF_AXI_CLK>, 2626 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2627 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2628 clock-names = "iface", "bus", "core", "vsync"; 2629 2630 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2631 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2632 assigned-clock-rates = <460000000>, 2633 <19200000>; 2634 2635 operating-points-v2 = <&mdp_opp_table>; 2636 power-domains = <&rpmhpd SM8250_MMCX>; 2637 2638 interrupt-parent = <&mdss>; 2639 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2640 2641 ports { 2642 #address-cells = <1>; 2643 #size-cells = <0>; 2644 2645 port@0 { 2646 reg = <0>; 2647 dpu_intf1_out: endpoint { 2648 remote-endpoint = <&dsi0_in>; 2649 }; 2650 }; 2651 2652 port@1 { 2653 reg = <1>; 2654 dpu_intf2_out: endpoint { 2655 remote-endpoint = <&dsi1_in>; 2656 }; 2657 }; 2658 }; 2659 2660 mdp_opp_table: mdp-opp-table { 2661 compatible = "operating-points-v2"; 2662 2663 opp-200000000 { 2664 opp-hz = /bits/ 64 <200000000>; 2665 required-opps = <&rpmhpd_opp_low_svs>; 2666 }; 2667 2668 opp-300000000 { 2669 opp-hz = /bits/ 64 <300000000>; 2670 required-opps = <&rpmhpd_opp_svs>; 2671 }; 2672 2673 opp-345000000 { 2674 opp-hz = /bits/ 64 <345000000>; 2675 required-opps = <&rpmhpd_opp_svs_l1>; 2676 }; 2677 2678 opp-460000000 { 2679 opp-hz = /bits/ 64 <460000000>; 2680 required-opps = <&rpmhpd_opp_nom>; 2681 }; 2682 }; 2683 }; 2684 2685 dsi0: dsi@ae94000 { 2686 compatible = "qcom,mdss-dsi-ctrl"; 2687 reg = <0 0x0ae94000 0 0x400>; 2688 reg-names = "dsi_ctrl"; 2689 2690 interrupt-parent = <&mdss>; 2691 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2692 2693 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2694 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2695 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2696 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2697 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2698 <&gcc GCC_DISP_HF_AXI_CLK>; 2699 clock-names = "byte", 2700 "byte_intf", 2701 "pixel", 2702 "core", 2703 "iface", 2704 "bus"; 2705 2706 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2707 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 2708 2709 operating-points-v2 = <&dsi_opp_table>; 2710 power-domains = <&rpmhpd SM8250_MMCX>; 2711 2712 phys = <&dsi0_phy>; 2713 phy-names = "dsi"; 2714 2715 status = "disabled"; 2716 2717 #address-cells = <1>; 2718 #size-cells = <0>; 2719 2720 ports { 2721 #address-cells = <1>; 2722 #size-cells = <0>; 2723 2724 port@0 { 2725 reg = <0>; 2726 dsi0_in: endpoint { 2727 remote-endpoint = <&dpu_intf1_out>; 2728 }; 2729 }; 2730 2731 port@1 { 2732 reg = <1>; 2733 dsi0_out: endpoint { 2734 }; 2735 }; 2736 }; 2737 }; 2738 2739 dsi0_phy: dsi-phy@ae94400 { 2740 compatible = "qcom,dsi-phy-7nm"; 2741 reg = <0 0x0ae94400 0 0x200>, 2742 <0 0x0ae94600 0 0x280>, 2743 <0 0x0ae94900 0 0x260>; 2744 reg-names = "dsi_phy", 2745 "dsi_phy_lane", 2746 "dsi_pll"; 2747 2748 #clock-cells = <1>; 2749 #phy-cells = <0>; 2750 2751 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2752 <&rpmhcc RPMH_CXO_CLK>; 2753 clock-names = "iface", "ref"; 2754 2755 status = "disabled"; 2756 }; 2757 2758 dsi1: dsi@ae96000 { 2759 compatible = "qcom,mdss-dsi-ctrl"; 2760 reg = <0 0x0ae96000 0 0x400>; 2761 reg-names = "dsi_ctrl"; 2762 2763 interrupt-parent = <&mdss>; 2764 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 2765 2766 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2767 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2768 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2769 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2770 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2771 <&gcc GCC_DISP_HF_AXI_CLK>; 2772 clock-names = "byte", 2773 "byte_intf", 2774 "pixel", 2775 "core", 2776 "iface", 2777 "bus"; 2778 2779 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2780 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 2781 2782 operating-points-v2 = <&dsi_opp_table>; 2783 power-domains = <&rpmhpd SM8250_MMCX>; 2784 2785 phys = <&dsi1_phy>; 2786 phy-names = "dsi"; 2787 2788 status = "disabled"; 2789 2790 #address-cells = <1>; 2791 #size-cells = <0>; 2792 2793 ports { 2794 #address-cells = <1>; 2795 #size-cells = <0>; 2796 2797 port@0 { 2798 reg = <0>; 2799 dsi1_in: endpoint { 2800 remote-endpoint = <&dpu_intf2_out>; 2801 }; 2802 }; 2803 2804 port@1 { 2805 reg = <1>; 2806 dsi1_out: endpoint { 2807 }; 2808 }; 2809 }; 2810 }; 2811 2812 dsi1_phy: dsi-phy@ae96400 { 2813 compatible = "qcom,dsi-phy-7nm"; 2814 reg = <0 0x0ae96400 0 0x200>, 2815 <0 0x0ae96600 0 0x280>, 2816 <0 0x0ae96900 0 0x260>; 2817 reg-names = "dsi_phy", 2818 "dsi_phy_lane", 2819 "dsi_pll"; 2820 2821 #clock-cells = <1>; 2822 #phy-cells = <0>; 2823 2824 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2825 <&rpmhcc RPMH_CXO_CLK>; 2826 clock-names = "iface", "ref"; 2827 2828 status = "disabled"; 2829 2830 dsi_opp_table: dsi-opp-table { 2831 compatible = "operating-points-v2"; 2832 2833 opp-187500000 { 2834 opp-hz = /bits/ 64 <187500000>; 2835 required-opps = <&rpmhpd_opp_low_svs>; 2836 }; 2837 2838 opp-300000000 { 2839 opp-hz = /bits/ 64 <300000000>; 2840 required-opps = <&rpmhpd_opp_svs>; 2841 }; 2842 2843 opp-358000000 { 2844 opp-hz = /bits/ 64 <358000000>; 2845 required-opps = <&rpmhpd_opp_svs_l1>; 2846 }; 2847 }; 2848 }; 2849 }; 2850 2851 dispcc: clock-controller@af00000 { 2852 compatible = "qcom,sm8250-dispcc"; 2853 reg = <0 0x0af00000 0 0x10000>; 2854 mmcx-supply = <&mmcx_reg>; 2855 clocks = <&rpmhcc RPMH_CXO_CLK>, 2856 <&dsi0_phy 0>, 2857 <&dsi0_phy 1>, 2858 <&dsi1_phy 0>, 2859 <&dsi1_phy 1>, 2860 <&dp_phy 0>, 2861 <&dp_phy 1>; 2862 clock-names = "bi_tcxo", 2863 "dsi0_phy_pll_out_byteclk", 2864 "dsi0_phy_pll_out_dsiclk", 2865 "dsi1_phy_pll_out_byteclk", 2866 "dsi1_phy_pll_out_dsiclk", 2867 "dp_phy_pll_link_clk", 2868 "dp_phy_pll_vco_div_clk"; 2869 #clock-cells = <1>; 2870 #reset-cells = <1>; 2871 #power-domain-cells = <1>; 2872 }; 2873 2874 pdc: interrupt-controller@b220000 { 2875 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 2876 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2877 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2878 <125 63 1>, <126 716 12>; 2879 #interrupt-cells = <2>; 2880 interrupt-parent = <&intc>; 2881 interrupt-controller; 2882 }; 2883 2884 tsens0: thermal-sensor@c263000 { 2885 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2886 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2887 <0 0x0c222000 0 0x1ff>; /* SROT */ 2888 #qcom,sensors = <16>; 2889 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2890 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2891 interrupt-names = "uplow", "critical"; 2892 #thermal-sensor-cells = <1>; 2893 }; 2894 2895 tsens1: thermal-sensor@c265000 { 2896 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 2897 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2898 <0 0x0c223000 0 0x1ff>; /* SROT */ 2899 #qcom,sensors = <9>; 2900 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2901 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2902 interrupt-names = "uplow", "critical"; 2903 #thermal-sensor-cells = <1>; 2904 }; 2905 2906 aoss_qmp: power-controller@c300000 { 2907 compatible = "qcom,sm8250-aoss-qmp"; 2908 reg = <0 0x0c300000 0 0x100000>; 2909 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2910 IPCC_MPROC_SIGNAL_GLINK_QMP 2911 IRQ_TYPE_EDGE_RISING>; 2912 mboxes = <&ipcc IPCC_CLIENT_AOP 2913 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2914 2915 #clock-cells = <0>; 2916 #power-domain-cells = <1>; 2917 }; 2918 2919 spmi_bus: spmi@c440000 { 2920 compatible = "qcom,spmi-pmic-arb"; 2921 reg = <0x0 0x0c440000 0x0 0x0001100>, 2922 <0x0 0x0c600000 0x0 0x2000000>, 2923 <0x0 0x0e600000 0x0 0x0100000>, 2924 <0x0 0x0e700000 0x0 0x00a0000>, 2925 <0x0 0x0c40a000 0x0 0x0026000>; 2926 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2927 interrupt-names = "periph_irq"; 2928 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2929 qcom,ee = <0>; 2930 qcom,channel = <0>; 2931 #address-cells = <2>; 2932 #size-cells = <0>; 2933 interrupt-controller; 2934 #interrupt-cells = <4>; 2935 }; 2936 2937 tlmm: pinctrl@f100000 { 2938 compatible = "qcom,sm8250-pinctrl"; 2939 reg = <0 0x0f100000 0 0x300000>, 2940 <0 0x0f500000 0 0x300000>, 2941 <0 0x0f900000 0 0x300000>; 2942 reg-names = "west", "south", "north"; 2943 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2944 gpio-controller; 2945 #gpio-cells = <2>; 2946 interrupt-controller; 2947 #interrupt-cells = <2>; 2948 gpio-ranges = <&tlmm 0 0 181>; 2949 wakeup-parent = <&pdc>; 2950 2951 pri_mi2s_active: pri-mi2s-active { 2952 sclk { 2953 pins = "gpio138"; 2954 function = "mi2s0_sck"; 2955 drive-strength = <8>; 2956 bias-disable; 2957 }; 2958 2959 ws { 2960 pins = "gpio141"; 2961 function = "mi2s0_ws"; 2962 drive-strength = <8>; 2963 output-high; 2964 }; 2965 2966 data0 { 2967 pins = "gpio139"; 2968 function = "mi2s0_data0"; 2969 drive-strength = <8>; 2970 bias-disable; 2971 output-high; 2972 }; 2973 2974 data1 { 2975 pins = "gpio140"; 2976 function = "mi2s0_data1"; 2977 drive-strength = <8>; 2978 output-high; 2979 }; 2980 }; 2981 2982 qup_i2c0_default: qup-i2c0-default { 2983 mux { 2984 pins = "gpio28", "gpio29"; 2985 function = "qup0"; 2986 }; 2987 2988 config { 2989 pins = "gpio28", "gpio29"; 2990 drive-strength = <2>; 2991 bias-disable; 2992 }; 2993 }; 2994 2995 qup_i2c1_default: qup-i2c1-default { 2996 pinmux { 2997 pins = "gpio4", "gpio5"; 2998 function = "qup1"; 2999 }; 3000 3001 config { 3002 pins = "gpio4", "gpio5"; 3003 drive-strength = <2>; 3004 bias-disable; 3005 }; 3006 }; 3007 3008 qup_i2c2_default: qup-i2c2-default { 3009 mux { 3010 pins = "gpio115", "gpio116"; 3011 function = "qup2"; 3012 }; 3013 3014 config { 3015 pins = "gpio115", "gpio116"; 3016 drive-strength = <2>; 3017 bias-disable; 3018 }; 3019 }; 3020 3021 qup_i2c3_default: qup-i2c3-default { 3022 mux { 3023 pins = "gpio119", "gpio120"; 3024 function = "qup3"; 3025 }; 3026 3027 config { 3028 pins = "gpio119", "gpio120"; 3029 drive-strength = <2>; 3030 bias-disable; 3031 }; 3032 }; 3033 3034 qup_i2c4_default: qup-i2c4-default { 3035 mux { 3036 pins = "gpio8", "gpio9"; 3037 function = "qup4"; 3038 }; 3039 3040 config { 3041 pins = "gpio8", "gpio9"; 3042 drive-strength = <2>; 3043 bias-disable; 3044 }; 3045 }; 3046 3047 qup_i2c5_default: qup-i2c5-default { 3048 mux { 3049 pins = "gpio12", "gpio13"; 3050 function = "qup5"; 3051 }; 3052 3053 config { 3054 pins = "gpio12", "gpio13"; 3055 drive-strength = <2>; 3056 bias-disable; 3057 }; 3058 }; 3059 3060 qup_i2c6_default: qup-i2c6-default { 3061 mux { 3062 pins = "gpio16", "gpio17"; 3063 function = "qup6"; 3064 }; 3065 3066 config { 3067 pins = "gpio16", "gpio17"; 3068 drive-strength = <2>; 3069 bias-disable; 3070 }; 3071 }; 3072 3073 qup_i2c7_default: qup-i2c7-default { 3074 mux { 3075 pins = "gpio20", "gpio21"; 3076 function = "qup7"; 3077 }; 3078 3079 config { 3080 pins = "gpio20", "gpio21"; 3081 drive-strength = <2>; 3082 bias-disable; 3083 }; 3084 }; 3085 3086 qup_i2c8_default: qup-i2c8-default { 3087 mux { 3088 pins = "gpio24", "gpio25"; 3089 function = "qup8"; 3090 }; 3091 3092 config { 3093 pins = "gpio24", "gpio25"; 3094 drive-strength = <2>; 3095 bias-disable; 3096 }; 3097 }; 3098 3099 qup_i2c9_default: qup-i2c9-default { 3100 mux { 3101 pins = "gpio125", "gpio126"; 3102 function = "qup9"; 3103 }; 3104 3105 config { 3106 pins = "gpio125", "gpio126"; 3107 drive-strength = <2>; 3108 bias-disable; 3109 }; 3110 }; 3111 3112 qup_i2c10_default: qup-i2c10-default { 3113 mux { 3114 pins = "gpio129", "gpio130"; 3115 function = "qup10"; 3116 }; 3117 3118 config { 3119 pins = "gpio129", "gpio130"; 3120 drive-strength = <2>; 3121 bias-disable; 3122 }; 3123 }; 3124 3125 qup_i2c11_default: qup-i2c11-default { 3126 mux { 3127 pins = "gpio60", "gpio61"; 3128 function = "qup11"; 3129 }; 3130 3131 config { 3132 pins = "gpio60", "gpio61"; 3133 drive-strength = <2>; 3134 bias-disable; 3135 }; 3136 }; 3137 3138 qup_i2c12_default: qup-i2c12-default { 3139 mux { 3140 pins = "gpio32", "gpio33"; 3141 function = "qup12"; 3142 }; 3143 3144 config { 3145 pins = "gpio32", "gpio33"; 3146 drive-strength = <2>; 3147 bias-disable; 3148 }; 3149 }; 3150 3151 qup_i2c13_default: qup-i2c13-default { 3152 mux { 3153 pins = "gpio36", "gpio37"; 3154 function = "qup13"; 3155 }; 3156 3157 config { 3158 pins = "gpio36", "gpio37"; 3159 drive-strength = <2>; 3160 bias-disable; 3161 }; 3162 }; 3163 3164 qup_i2c14_default: qup-i2c14-default { 3165 mux { 3166 pins = "gpio40", "gpio41"; 3167 function = "qup14"; 3168 }; 3169 3170 config { 3171 pins = "gpio40", "gpio41"; 3172 drive-strength = <2>; 3173 bias-disable; 3174 }; 3175 }; 3176 3177 qup_i2c15_default: qup-i2c15-default { 3178 mux { 3179 pins = "gpio44", "gpio45"; 3180 function = "qup15"; 3181 }; 3182 3183 config { 3184 pins = "gpio44", "gpio45"; 3185 drive-strength = <2>; 3186 bias-disable; 3187 }; 3188 }; 3189 3190 qup_i2c16_default: qup-i2c16-default { 3191 mux { 3192 pins = "gpio48", "gpio49"; 3193 function = "qup16"; 3194 }; 3195 3196 config { 3197 pins = "gpio48", "gpio49"; 3198 drive-strength = <2>; 3199 bias-disable; 3200 }; 3201 }; 3202 3203 qup_i2c17_default: qup-i2c17-default { 3204 mux { 3205 pins = "gpio52", "gpio53"; 3206 function = "qup17"; 3207 }; 3208 3209 config { 3210 pins = "gpio52", "gpio53"; 3211 drive-strength = <2>; 3212 bias-disable; 3213 }; 3214 }; 3215 3216 qup_i2c18_default: qup-i2c18-default { 3217 mux { 3218 pins = "gpio56", "gpio57"; 3219 function = "qup18"; 3220 }; 3221 3222 config { 3223 pins = "gpio56", "gpio57"; 3224 drive-strength = <2>; 3225 bias-disable; 3226 }; 3227 }; 3228 3229 qup_i2c19_default: qup-i2c19-default { 3230 mux { 3231 pins = "gpio0", "gpio1"; 3232 function = "qup19"; 3233 }; 3234 3235 config { 3236 pins = "gpio0", "gpio1"; 3237 drive-strength = <2>; 3238 bias-disable; 3239 }; 3240 }; 3241 3242 qup_spi0_cs: qup-spi0-cs { 3243 pins = "gpio31"; 3244 function = "qup0"; 3245 }; 3246 3247 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 3248 pins = "gpio31"; 3249 function = "gpio"; 3250 }; 3251 3252 qup_spi0_data_clk: qup-spi0-data-clk { 3253 pins = "gpio28", "gpio29", 3254 "gpio30"; 3255 function = "qup0"; 3256 }; 3257 3258 qup_spi1_cs: qup-spi1-cs { 3259 pins = "gpio7"; 3260 function = "qup1"; 3261 }; 3262 3263 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 3264 pins = "gpio7"; 3265 function = "gpio"; 3266 }; 3267 3268 qup_spi1_data_clk: qup-spi1-data-clk { 3269 pins = "gpio4", "gpio5", 3270 "gpio6"; 3271 function = "qup1"; 3272 }; 3273 3274 qup_spi2_cs: qup-spi2-cs { 3275 pins = "gpio118"; 3276 function = "qup2"; 3277 }; 3278 3279 qup_spi2_cs_gpio: qup-spi2-cs-gpio { 3280 pins = "gpio118"; 3281 function = "gpio"; 3282 }; 3283 3284 qup_spi2_data_clk: qup-spi2-data-clk { 3285 pins = "gpio115", "gpio116", 3286 "gpio117"; 3287 function = "qup2"; 3288 }; 3289 3290 qup_spi3_cs: qup-spi3-cs { 3291 pins = "gpio122"; 3292 function = "qup3"; 3293 }; 3294 3295 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 3296 pins = "gpio122"; 3297 function = "gpio"; 3298 }; 3299 3300 qup_spi3_data_clk: qup-spi3-data-clk { 3301 pins = "gpio119", "gpio120", 3302 "gpio121"; 3303 function = "qup3"; 3304 }; 3305 3306 qup_spi4_cs: qup-spi4-cs { 3307 pins = "gpio11"; 3308 function = "qup4"; 3309 }; 3310 3311 qup_spi4_cs_gpio: qup-spi4-cs-gpio { 3312 pins = "gpio11"; 3313 function = "gpio"; 3314 }; 3315 3316 qup_spi4_data_clk: qup-spi4-data-clk { 3317 pins = "gpio8", "gpio9", 3318 "gpio10"; 3319 function = "qup4"; 3320 }; 3321 3322 qup_spi5_cs: qup-spi5-cs { 3323 pins = "gpio15"; 3324 function = "qup5"; 3325 }; 3326 3327 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 3328 pins = "gpio15"; 3329 function = "gpio"; 3330 }; 3331 3332 qup_spi5_data_clk: qup-spi5-data-clk { 3333 pins = "gpio12", "gpio13", 3334 "gpio14"; 3335 function = "qup5"; 3336 }; 3337 3338 qup_spi6_cs: qup-spi6-cs { 3339 pins = "gpio19"; 3340 function = "qup6"; 3341 }; 3342 3343 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 3344 pins = "gpio19"; 3345 function = "gpio"; 3346 }; 3347 3348 qup_spi6_data_clk: qup-spi6-data-clk { 3349 pins = "gpio16", "gpio17", 3350 "gpio18"; 3351 function = "qup6"; 3352 }; 3353 3354 qup_spi7_cs: qup-spi7-cs { 3355 pins = "gpio23"; 3356 function = "qup7"; 3357 }; 3358 3359 qup_spi7_cs_gpio: qup-spi7-cs-gpio { 3360 pins = "gpio23"; 3361 function = "gpio"; 3362 }; 3363 3364 qup_spi7_data_clk: qup-spi7-data-clk { 3365 pins = "gpio20", "gpio21", 3366 "gpio22"; 3367 function = "qup7"; 3368 }; 3369 3370 qup_spi8_cs: qup-spi8-cs { 3371 pins = "gpio27"; 3372 function = "qup8"; 3373 }; 3374 3375 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 3376 pins = "gpio27"; 3377 function = "gpio"; 3378 }; 3379 3380 qup_spi8_data_clk: qup-spi8-data-clk { 3381 pins = "gpio24", "gpio25", 3382 "gpio26"; 3383 function = "qup8"; 3384 }; 3385 3386 qup_spi9_cs: qup-spi9-cs { 3387 pins = "gpio128"; 3388 function = "qup9"; 3389 }; 3390 3391 qup_spi9_cs_gpio: qup-spi9-cs-gpio { 3392 pins = "gpio128"; 3393 function = "gpio"; 3394 }; 3395 3396 qup_spi9_data_clk: qup-spi9-data-clk { 3397 pins = "gpio125", "gpio126", 3398 "gpio127"; 3399 function = "qup9"; 3400 }; 3401 3402 qup_spi10_cs: qup-spi10-cs { 3403 pins = "gpio132"; 3404 function = "qup10"; 3405 }; 3406 3407 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 3408 pins = "gpio132"; 3409 function = "gpio"; 3410 }; 3411 3412 qup_spi10_data_clk: qup-spi10-data-clk { 3413 pins = "gpio129", "gpio130", 3414 "gpio131"; 3415 function = "qup10"; 3416 }; 3417 3418 qup_spi11_cs: qup-spi11-cs { 3419 pins = "gpio63"; 3420 function = "qup11"; 3421 }; 3422 3423 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 3424 pins = "gpio63"; 3425 function = "gpio"; 3426 }; 3427 3428 qup_spi11_data_clk: qup-spi11-data-clk { 3429 pins = "gpio60", "gpio61", 3430 "gpio62"; 3431 function = "qup11"; 3432 }; 3433 3434 qup_spi12_cs: qup-spi12-cs { 3435 pins = "gpio35"; 3436 function = "qup12"; 3437 }; 3438 3439 qup_spi12_cs_gpio: qup-spi12-cs-gpio { 3440 pins = "gpio35"; 3441 function = "gpio"; 3442 }; 3443 3444 qup_spi12_data_clk: qup-spi12-data-clk { 3445 pins = "gpio32", "gpio33", 3446 "gpio34"; 3447 function = "qup12"; 3448 }; 3449 3450 qup_spi13_cs: qup-spi13-cs { 3451 pins = "gpio39"; 3452 function = "qup13"; 3453 }; 3454 3455 qup_spi13_cs_gpio: qup-spi13-cs-gpio { 3456 pins = "gpio39"; 3457 function = "gpio"; 3458 }; 3459 3460 qup_spi13_data_clk: qup-spi13-data-clk { 3461 pins = "gpio36", "gpio37", 3462 "gpio38"; 3463 function = "qup13"; 3464 }; 3465 3466 qup_spi14_cs: qup-spi14-cs { 3467 pins = "gpio43"; 3468 function = "qup14"; 3469 }; 3470 3471 qup_spi14_cs_gpio: qup-spi14-cs-gpio { 3472 pins = "gpio43"; 3473 function = "gpio"; 3474 }; 3475 3476 qup_spi14_data_clk: qup-spi14-data-clk { 3477 pins = "gpio40", "gpio41", 3478 "gpio42"; 3479 function = "qup14"; 3480 }; 3481 3482 qup_spi15_cs: qup-spi15-cs { 3483 pins = "gpio47"; 3484 function = "qup15"; 3485 }; 3486 3487 qup_spi15_cs_gpio: qup-spi15-cs-gpio { 3488 pins = "gpio47"; 3489 function = "gpio"; 3490 }; 3491 3492 qup_spi15_data_clk: qup-spi15-data-clk { 3493 pins = "gpio44", "gpio45", 3494 "gpio46"; 3495 function = "qup15"; 3496 }; 3497 3498 qup_spi16_cs: qup-spi16-cs { 3499 pins = "gpio51"; 3500 function = "qup16"; 3501 }; 3502 3503 qup_spi16_cs_gpio: qup-spi16-cs-gpio { 3504 pins = "gpio51"; 3505 function = "gpio"; 3506 }; 3507 3508 qup_spi16_data_clk: qup-spi16-data-clk { 3509 pins = "gpio48", "gpio49", 3510 "gpio50"; 3511 function = "qup16"; 3512 }; 3513 3514 qup_spi17_cs: qup-spi17-cs { 3515 pins = "gpio55"; 3516 function = "qup17"; 3517 }; 3518 3519 qup_spi17_cs_gpio: qup-spi17-cs-gpio { 3520 pins = "gpio55"; 3521 function = "gpio"; 3522 }; 3523 3524 qup_spi17_data_clk: qup-spi17-data-clk { 3525 pins = "gpio52", "gpio53", 3526 "gpio54"; 3527 function = "qup17"; 3528 }; 3529 3530 qup_spi18_cs: qup-spi18-cs { 3531 pins = "gpio59"; 3532 function = "qup18"; 3533 }; 3534 3535 qup_spi18_cs_gpio: qup-spi18-cs-gpio { 3536 pins = "gpio59"; 3537 function = "gpio"; 3538 }; 3539 3540 qup_spi18_data_clk: qup-spi18-data-clk { 3541 pins = "gpio56", "gpio57", 3542 "gpio58"; 3543 function = "qup18"; 3544 }; 3545 3546 qup_spi19_cs: qup-spi19-cs { 3547 pins = "gpio3"; 3548 function = "qup19"; 3549 }; 3550 3551 qup_spi19_cs_gpio: qup-spi19-cs-gpio { 3552 pins = "gpio3"; 3553 function = "gpio"; 3554 }; 3555 3556 qup_spi19_data_clk: qup-spi19-data-clk { 3557 pins = "gpio0", "gpio1", 3558 "gpio2"; 3559 function = "qup19"; 3560 }; 3561 3562 qup_uart2_default: qup-uart2-default { 3563 mux { 3564 pins = "gpio117", "gpio118"; 3565 function = "qup2"; 3566 }; 3567 }; 3568 3569 qup_uart6_default: qup-uart6-default { 3570 mux { 3571 pins = "gpio16", "gpio17", 3572 "gpio18", "gpio19"; 3573 function = "qup6"; 3574 }; 3575 }; 3576 3577 qup_uart12_default: qup-uart12-default { 3578 mux { 3579 pins = "gpio34", "gpio35"; 3580 function = "qup12"; 3581 }; 3582 }; 3583 3584 qup_uart17_default: qup-uart17-default { 3585 mux { 3586 pins = "gpio52", "gpio53", 3587 "gpio54", "gpio55"; 3588 function = "qup17"; 3589 }; 3590 }; 3591 3592 qup_uart18_default: qup-uart18-default { 3593 mux { 3594 pins = "gpio58", "gpio59"; 3595 function = "qup18"; 3596 }; 3597 }; 3598 3599 tert_mi2s_active: tert-mi2s-active { 3600 sck { 3601 pins = "gpio133"; 3602 function = "mi2s2_sck"; 3603 drive-strength = <8>; 3604 bias-disable; 3605 }; 3606 3607 data0 { 3608 pins = "gpio134"; 3609 function = "mi2s2_data0"; 3610 drive-strength = <8>; 3611 bias-disable; 3612 output-high; 3613 }; 3614 3615 ws { 3616 pins = "gpio135"; 3617 function = "mi2s2_ws"; 3618 drive-strength = <8>; 3619 output-high; 3620 }; 3621 }; 3622 3623 sdc2_sleep_state: sdc2-sleep { 3624 clk { 3625 pins = "sdc2_clk"; 3626 drive-strength = <2>; 3627 bias-disable; 3628 }; 3629 3630 cmd { 3631 pins = "sdc2_cmd"; 3632 drive-strength = <2>; 3633 bias-pull-up; 3634 }; 3635 3636 data { 3637 pins = "sdc2_data"; 3638 drive-strength = <2>; 3639 bias-pull-up; 3640 }; 3641 }; 3642 3643 pcie0_default_state: pcie0-default { 3644 perst { 3645 pins = "gpio79"; 3646 function = "gpio"; 3647 drive-strength = <2>; 3648 bias-pull-down; 3649 }; 3650 3651 clkreq { 3652 pins = "gpio80"; 3653 function = "pci_e0"; 3654 drive-strength = <2>; 3655 bias-pull-up; 3656 }; 3657 3658 wake { 3659 pins = "gpio81"; 3660 function = "gpio"; 3661 drive-strength = <2>; 3662 bias-pull-up; 3663 }; 3664 }; 3665 3666 pcie1_default_state: pcie1-default { 3667 perst { 3668 pins = "gpio82"; 3669 function = "gpio"; 3670 drive-strength = <2>; 3671 bias-pull-down; 3672 }; 3673 3674 clkreq { 3675 pins = "gpio83"; 3676 function = "pci_e1"; 3677 drive-strength = <2>; 3678 bias-pull-up; 3679 }; 3680 3681 wake { 3682 pins = "gpio84"; 3683 function = "gpio"; 3684 drive-strength = <2>; 3685 bias-pull-up; 3686 }; 3687 }; 3688 3689 pcie2_default_state: pcie2-default { 3690 perst { 3691 pins = "gpio85"; 3692 function = "gpio"; 3693 drive-strength = <2>; 3694 bias-pull-down; 3695 }; 3696 3697 clkreq { 3698 pins = "gpio86"; 3699 function = "pci_e2"; 3700 drive-strength = <2>; 3701 bias-pull-up; 3702 }; 3703 3704 wake { 3705 pins = "gpio87"; 3706 function = "gpio"; 3707 drive-strength = <2>; 3708 bias-pull-up; 3709 }; 3710 }; 3711 }; 3712 3713 apps_smmu: iommu@15000000 { 3714 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 3715 reg = <0 0x15000000 0 0x100000>; 3716 #iommu-cells = <2>; 3717 #global-interrupts = <2>; 3718 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3719 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3720 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3721 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3722 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3723 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3724 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3725 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3726 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3727 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3728 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3729 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3730 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3731 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3732 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3733 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3734 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3735 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3736 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3737 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3738 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3739 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3740 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3741 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3742 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3743 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3744 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3745 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3746 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3747 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3748 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3749 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3750 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3751 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3752 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3753 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3754 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3755 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3756 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3757 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3758 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3759 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3760 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3761 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3762 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3763 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3764 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3765 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3799 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3800 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3801 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3802 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3803 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3804 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3805 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3809 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3810 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3811 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3812 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3813 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3814 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3815 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3816 }; 3817 3818 adsp: remoteproc@17300000 { 3819 compatible = "qcom,sm8250-adsp-pas"; 3820 reg = <0 0x17300000 0 0x100>; 3821 3822 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3823 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3824 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3825 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3826 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3827 interrupt-names = "wdog", "fatal", "ready", 3828 "handover", "stop-ack"; 3829 3830 clocks = <&rpmhcc RPMH_CXO_CLK>; 3831 clock-names = "xo"; 3832 3833 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, 3834 <&rpmhpd SM8250_LCX>, 3835 <&rpmhpd SM8250_LMX>; 3836 power-domain-names = "load_state", "lcx", "lmx"; 3837 3838 memory-region = <&adsp_mem>; 3839 3840 qcom,smem-states = <&smp2p_adsp_out 0>; 3841 qcom,smem-state-names = "stop"; 3842 3843 status = "disabled"; 3844 3845 glink-edge { 3846 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3847 IPCC_MPROC_SIGNAL_GLINK_QMP 3848 IRQ_TYPE_EDGE_RISING>; 3849 mboxes = <&ipcc IPCC_CLIENT_LPASS 3850 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3851 3852 label = "lpass"; 3853 qcom,remote-pid = <2>; 3854 3855 apr { 3856 compatible = "qcom,apr-v2"; 3857 qcom,glink-channels = "apr_audio_svc"; 3858 qcom,apr-domain = <APR_DOMAIN_ADSP>; 3859 #address-cells = <1>; 3860 #size-cells = <0>; 3861 3862 apr-service@3 { 3863 reg = <APR_SVC_ADSP_CORE>; 3864 compatible = "qcom,q6core"; 3865 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3866 }; 3867 3868 q6afe: apr-service@4 { 3869 compatible = "qcom,q6afe"; 3870 reg = <APR_SVC_AFE>; 3871 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3872 q6afedai: dais { 3873 compatible = "qcom,q6afe-dais"; 3874 #address-cells = <1>; 3875 #size-cells = <0>; 3876 #sound-dai-cells = <1>; 3877 }; 3878 3879 q6afecc: cc { 3880 compatible = "qcom,q6afe-clocks"; 3881 #clock-cells = <2>; 3882 }; 3883 }; 3884 3885 q6asm: apr-service@7 { 3886 compatible = "qcom,q6asm"; 3887 reg = <APR_SVC_ASM>; 3888 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3889 q6asmdai: dais { 3890 compatible = "qcom,q6asm-dais"; 3891 #address-cells = <1>; 3892 #size-cells = <0>; 3893 #sound-dai-cells = <1>; 3894 iommus = <&apps_smmu 0x1801 0x0>; 3895 }; 3896 }; 3897 3898 q6adm: apr-service@8 { 3899 compatible = "qcom,q6adm"; 3900 reg = <APR_SVC_ADM>; 3901 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3902 q6routing: routing { 3903 compatible = "qcom,q6adm-routing"; 3904 #sound-dai-cells = <0>; 3905 }; 3906 }; 3907 }; 3908 3909 fastrpc { 3910 compatible = "qcom,fastrpc"; 3911 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3912 label = "adsp"; 3913 #address-cells = <1>; 3914 #size-cells = <0>; 3915 3916 compute-cb@3 { 3917 compatible = "qcom,fastrpc-compute-cb"; 3918 reg = <3>; 3919 iommus = <&apps_smmu 0x1803 0x0>; 3920 }; 3921 3922 compute-cb@4 { 3923 compatible = "qcom,fastrpc-compute-cb"; 3924 reg = <4>; 3925 iommus = <&apps_smmu 0x1804 0x0>; 3926 }; 3927 3928 compute-cb@5 { 3929 compatible = "qcom,fastrpc-compute-cb"; 3930 reg = <5>; 3931 iommus = <&apps_smmu 0x1805 0x0>; 3932 }; 3933 }; 3934 }; 3935 }; 3936 3937 intc: interrupt-controller@17a00000 { 3938 compatible = "arm,gic-v3"; 3939 #interrupt-cells = <3>; 3940 interrupt-controller; 3941 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3942 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3943 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3944 }; 3945 3946 watchdog@17c10000 { 3947 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 3948 reg = <0 0x17c10000 0 0x1000>; 3949 clocks = <&sleep_clk>; 3950 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 3951 }; 3952 3953 timer@17c20000 { 3954 #address-cells = <2>; 3955 #size-cells = <2>; 3956 ranges; 3957 compatible = "arm,armv7-timer-mem"; 3958 reg = <0x0 0x17c20000 0x0 0x1000>; 3959 clock-frequency = <19200000>; 3960 3961 frame@17c21000 { 3962 frame-number = <0>; 3963 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3964 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3965 reg = <0x0 0x17c21000 0x0 0x1000>, 3966 <0x0 0x17c22000 0x0 0x1000>; 3967 }; 3968 3969 frame@17c23000 { 3970 frame-number = <1>; 3971 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3972 reg = <0x0 0x17c23000 0x0 0x1000>; 3973 status = "disabled"; 3974 }; 3975 3976 frame@17c25000 { 3977 frame-number = <2>; 3978 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3979 reg = <0x0 0x17c25000 0x0 0x1000>; 3980 status = "disabled"; 3981 }; 3982 3983 frame@17c27000 { 3984 frame-number = <3>; 3985 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3986 reg = <0x0 0x17c27000 0x0 0x1000>; 3987 status = "disabled"; 3988 }; 3989 3990 frame@17c29000 { 3991 frame-number = <4>; 3992 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3993 reg = <0x0 0x17c29000 0x0 0x1000>; 3994 status = "disabled"; 3995 }; 3996 3997 frame@17c2b000 { 3998 frame-number = <5>; 3999 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4000 reg = <0x0 0x17c2b000 0x0 0x1000>; 4001 status = "disabled"; 4002 }; 4003 4004 frame@17c2d000 { 4005 frame-number = <6>; 4006 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4007 reg = <0x0 0x17c2d000 0x0 0x1000>; 4008 status = "disabled"; 4009 }; 4010 }; 4011 4012 apps_rsc: rsc@18200000 { 4013 label = "apps_rsc"; 4014 compatible = "qcom,rpmh-rsc"; 4015 reg = <0x0 0x18200000 0x0 0x10000>, 4016 <0x0 0x18210000 0x0 0x10000>, 4017 <0x0 0x18220000 0x0 0x10000>; 4018 reg-names = "drv-0", "drv-1", "drv-2"; 4019 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4020 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4021 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4022 qcom,tcs-offset = <0xd00>; 4023 qcom,drv-id = <2>; 4024 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 4025 <WAKE_TCS 3>, <CONTROL_TCS 1>; 4026 4027 rpmhcc: clock-controller { 4028 compatible = "qcom,sm8250-rpmh-clk"; 4029 #clock-cells = <1>; 4030 clock-names = "xo"; 4031 clocks = <&xo_board>; 4032 }; 4033 4034 rpmhpd: power-controller { 4035 compatible = "qcom,sm8250-rpmhpd"; 4036 #power-domain-cells = <1>; 4037 operating-points-v2 = <&rpmhpd_opp_table>; 4038 4039 rpmhpd_opp_table: opp-table { 4040 compatible = "operating-points-v2"; 4041 4042 rpmhpd_opp_ret: opp1 { 4043 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4044 }; 4045 4046 rpmhpd_opp_min_svs: opp2 { 4047 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4048 }; 4049 4050 rpmhpd_opp_low_svs: opp3 { 4051 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4052 }; 4053 4054 rpmhpd_opp_svs: opp4 { 4055 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4056 }; 4057 4058 rpmhpd_opp_svs_l1: opp5 { 4059 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4060 }; 4061 4062 rpmhpd_opp_nom: opp6 { 4063 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4064 }; 4065 4066 rpmhpd_opp_nom_l1: opp7 { 4067 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4068 }; 4069 4070 rpmhpd_opp_nom_l2: opp8 { 4071 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4072 }; 4073 4074 rpmhpd_opp_turbo: opp9 { 4075 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4076 }; 4077 4078 rpmhpd_opp_turbo_l1: opp10 { 4079 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4080 }; 4081 }; 4082 }; 4083 4084 apps_bcm_voter: bcm_voter { 4085 compatible = "qcom,bcm-voter"; 4086 }; 4087 }; 4088 4089 epss_l3: interconnect@18590000 { 4090 compatible = "qcom,sm8250-epss-l3"; 4091 reg = <0 0x18590000 0 0x1000>; 4092 4093 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4094 clock-names = "xo", "alternate"; 4095 4096 #interconnect-cells = <1>; 4097 }; 4098 4099 cpufreq_hw: cpufreq@18591000 { 4100 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 4101 reg = <0 0x18591000 0 0x1000>, 4102 <0 0x18592000 0 0x1000>, 4103 <0 0x18593000 0 0x1000>; 4104 reg-names = "freq-domain0", "freq-domain1", 4105 "freq-domain2"; 4106 4107 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4108 clock-names = "xo", "alternate"; 4109 4110 #freq-domain-cells = <1>; 4111 }; 4112 }; 4113 4114 timer { 4115 compatible = "arm,armv8-timer"; 4116 interrupts = <GIC_PPI 13 4117 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4118 <GIC_PPI 14 4119 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4120 <GIC_PPI 11 4121 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4122 <GIC_PPI 10 4123 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4124 }; 4125 4126 thermal-zones { 4127 cpu0-thermal { 4128 polling-delay-passive = <250>; 4129 polling-delay = <1000>; 4130 4131 thermal-sensors = <&tsens0 1>; 4132 4133 trips { 4134 cpu0_alert0: trip-point0 { 4135 temperature = <90000>; 4136 hysteresis = <2000>; 4137 type = "passive"; 4138 }; 4139 4140 cpu0_alert1: trip-point1 { 4141 temperature = <95000>; 4142 hysteresis = <2000>; 4143 type = "passive"; 4144 }; 4145 4146 cpu0_crit: cpu_crit { 4147 temperature = <110000>; 4148 hysteresis = <1000>; 4149 type = "critical"; 4150 }; 4151 }; 4152 4153 cooling-maps { 4154 map0 { 4155 trip = <&cpu0_alert0>; 4156 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4157 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4158 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4159 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4160 }; 4161 map1 { 4162 trip = <&cpu0_alert1>; 4163 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4164 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4165 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4166 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4167 }; 4168 }; 4169 }; 4170 4171 cpu1-thermal { 4172 polling-delay-passive = <250>; 4173 polling-delay = <1000>; 4174 4175 thermal-sensors = <&tsens0 2>; 4176 4177 trips { 4178 cpu1_alert0: trip-point0 { 4179 temperature = <90000>; 4180 hysteresis = <2000>; 4181 type = "passive"; 4182 }; 4183 4184 cpu1_alert1: trip-point1 { 4185 temperature = <95000>; 4186 hysteresis = <2000>; 4187 type = "passive"; 4188 }; 4189 4190 cpu1_crit: cpu_crit { 4191 temperature = <110000>; 4192 hysteresis = <1000>; 4193 type = "critical"; 4194 }; 4195 }; 4196 4197 cooling-maps { 4198 map0 { 4199 trip = <&cpu1_alert0>; 4200 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4201 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4202 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4203 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4204 }; 4205 map1 { 4206 trip = <&cpu1_alert1>; 4207 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4208 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4209 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4210 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4211 }; 4212 }; 4213 }; 4214 4215 cpu2-thermal { 4216 polling-delay-passive = <250>; 4217 polling-delay = <1000>; 4218 4219 thermal-sensors = <&tsens0 3>; 4220 4221 trips { 4222 cpu2_alert0: trip-point0 { 4223 temperature = <90000>; 4224 hysteresis = <2000>; 4225 type = "passive"; 4226 }; 4227 4228 cpu2_alert1: trip-point1 { 4229 temperature = <95000>; 4230 hysteresis = <2000>; 4231 type = "passive"; 4232 }; 4233 4234 cpu2_crit: cpu_crit { 4235 temperature = <110000>; 4236 hysteresis = <1000>; 4237 type = "critical"; 4238 }; 4239 }; 4240 4241 cooling-maps { 4242 map0 { 4243 trip = <&cpu2_alert0>; 4244 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4245 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4246 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4247 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4248 }; 4249 map1 { 4250 trip = <&cpu2_alert1>; 4251 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4252 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4253 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4254 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4255 }; 4256 }; 4257 }; 4258 4259 cpu3-thermal { 4260 polling-delay-passive = <250>; 4261 polling-delay = <1000>; 4262 4263 thermal-sensors = <&tsens0 4>; 4264 4265 trips { 4266 cpu3_alert0: trip-point0 { 4267 temperature = <90000>; 4268 hysteresis = <2000>; 4269 type = "passive"; 4270 }; 4271 4272 cpu3_alert1: trip-point1 { 4273 temperature = <95000>; 4274 hysteresis = <2000>; 4275 type = "passive"; 4276 }; 4277 4278 cpu3_crit: cpu_crit { 4279 temperature = <110000>; 4280 hysteresis = <1000>; 4281 type = "critical"; 4282 }; 4283 }; 4284 4285 cooling-maps { 4286 map0 { 4287 trip = <&cpu3_alert0>; 4288 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4289 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4290 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4291 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4292 }; 4293 map1 { 4294 trip = <&cpu3_alert1>; 4295 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4296 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4297 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4298 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4299 }; 4300 }; 4301 }; 4302 4303 cpu4-top-thermal { 4304 polling-delay-passive = <250>; 4305 polling-delay = <1000>; 4306 4307 thermal-sensors = <&tsens0 7>; 4308 4309 trips { 4310 cpu4_top_alert0: trip-point0 { 4311 temperature = <90000>; 4312 hysteresis = <2000>; 4313 type = "passive"; 4314 }; 4315 4316 cpu4_top_alert1: trip-point1 { 4317 temperature = <95000>; 4318 hysteresis = <2000>; 4319 type = "passive"; 4320 }; 4321 4322 cpu4_top_crit: cpu_crit { 4323 temperature = <110000>; 4324 hysteresis = <1000>; 4325 type = "critical"; 4326 }; 4327 }; 4328 4329 cooling-maps { 4330 map0 { 4331 trip = <&cpu4_top_alert0>; 4332 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4333 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4334 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4335 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4336 }; 4337 map1 { 4338 trip = <&cpu4_top_alert1>; 4339 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4340 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4341 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4342 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4343 }; 4344 }; 4345 }; 4346 4347 cpu5-top-thermal { 4348 polling-delay-passive = <250>; 4349 polling-delay = <1000>; 4350 4351 thermal-sensors = <&tsens0 8>; 4352 4353 trips { 4354 cpu5_top_alert0: trip-point0 { 4355 temperature = <90000>; 4356 hysteresis = <2000>; 4357 type = "passive"; 4358 }; 4359 4360 cpu5_top_alert1: trip-point1 { 4361 temperature = <95000>; 4362 hysteresis = <2000>; 4363 type = "passive"; 4364 }; 4365 4366 cpu5_top_crit: cpu_crit { 4367 temperature = <110000>; 4368 hysteresis = <1000>; 4369 type = "critical"; 4370 }; 4371 }; 4372 4373 cooling-maps { 4374 map0 { 4375 trip = <&cpu5_top_alert0>; 4376 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4377 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4378 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4379 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4380 }; 4381 map1 { 4382 trip = <&cpu5_top_alert1>; 4383 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4384 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4385 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4386 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4387 }; 4388 }; 4389 }; 4390 4391 cpu6-top-thermal { 4392 polling-delay-passive = <250>; 4393 polling-delay = <1000>; 4394 4395 thermal-sensors = <&tsens0 9>; 4396 4397 trips { 4398 cpu6_top_alert0: trip-point0 { 4399 temperature = <90000>; 4400 hysteresis = <2000>; 4401 type = "passive"; 4402 }; 4403 4404 cpu6_top_alert1: trip-point1 { 4405 temperature = <95000>; 4406 hysteresis = <2000>; 4407 type = "passive"; 4408 }; 4409 4410 cpu6_top_crit: cpu_crit { 4411 temperature = <110000>; 4412 hysteresis = <1000>; 4413 type = "critical"; 4414 }; 4415 }; 4416 4417 cooling-maps { 4418 map0 { 4419 trip = <&cpu6_top_alert0>; 4420 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4421 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4422 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4423 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4424 }; 4425 map1 { 4426 trip = <&cpu6_top_alert1>; 4427 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4428 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4429 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4430 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4431 }; 4432 }; 4433 }; 4434 4435 cpu7-top-thermal { 4436 polling-delay-passive = <250>; 4437 polling-delay = <1000>; 4438 4439 thermal-sensors = <&tsens0 10>; 4440 4441 trips { 4442 cpu7_top_alert0: trip-point0 { 4443 temperature = <90000>; 4444 hysteresis = <2000>; 4445 type = "passive"; 4446 }; 4447 4448 cpu7_top_alert1: trip-point1 { 4449 temperature = <95000>; 4450 hysteresis = <2000>; 4451 type = "passive"; 4452 }; 4453 4454 cpu7_top_crit: cpu_crit { 4455 temperature = <110000>; 4456 hysteresis = <1000>; 4457 type = "critical"; 4458 }; 4459 }; 4460 4461 cooling-maps { 4462 map0 { 4463 trip = <&cpu7_top_alert0>; 4464 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4465 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4466 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4467 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4468 }; 4469 map1 { 4470 trip = <&cpu7_top_alert1>; 4471 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4472 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4473 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4474 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4475 }; 4476 }; 4477 }; 4478 4479 cpu4-bottom-thermal { 4480 polling-delay-passive = <250>; 4481 polling-delay = <1000>; 4482 4483 thermal-sensors = <&tsens0 11>; 4484 4485 trips { 4486 cpu4_bottom_alert0: trip-point0 { 4487 temperature = <90000>; 4488 hysteresis = <2000>; 4489 type = "passive"; 4490 }; 4491 4492 cpu4_bottom_alert1: trip-point1 { 4493 temperature = <95000>; 4494 hysteresis = <2000>; 4495 type = "passive"; 4496 }; 4497 4498 cpu4_bottom_crit: cpu_crit { 4499 temperature = <110000>; 4500 hysteresis = <1000>; 4501 type = "critical"; 4502 }; 4503 }; 4504 4505 cooling-maps { 4506 map0 { 4507 trip = <&cpu4_bottom_alert0>; 4508 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4509 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4510 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4511 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4512 }; 4513 map1 { 4514 trip = <&cpu4_bottom_alert1>; 4515 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4516 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4517 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4518 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4519 }; 4520 }; 4521 }; 4522 4523 cpu5-bottom-thermal { 4524 polling-delay-passive = <250>; 4525 polling-delay = <1000>; 4526 4527 thermal-sensors = <&tsens0 12>; 4528 4529 trips { 4530 cpu5_bottom_alert0: trip-point0 { 4531 temperature = <90000>; 4532 hysteresis = <2000>; 4533 type = "passive"; 4534 }; 4535 4536 cpu5_bottom_alert1: trip-point1 { 4537 temperature = <95000>; 4538 hysteresis = <2000>; 4539 type = "passive"; 4540 }; 4541 4542 cpu5_bottom_crit: cpu_crit { 4543 temperature = <110000>; 4544 hysteresis = <1000>; 4545 type = "critical"; 4546 }; 4547 }; 4548 4549 cooling-maps { 4550 map0 { 4551 trip = <&cpu5_bottom_alert0>; 4552 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4553 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4554 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4555 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4556 }; 4557 map1 { 4558 trip = <&cpu5_bottom_alert1>; 4559 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4560 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4561 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4562 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4563 }; 4564 }; 4565 }; 4566 4567 cpu6-bottom-thermal { 4568 polling-delay-passive = <250>; 4569 polling-delay = <1000>; 4570 4571 thermal-sensors = <&tsens0 13>; 4572 4573 trips { 4574 cpu6_bottom_alert0: trip-point0 { 4575 temperature = <90000>; 4576 hysteresis = <2000>; 4577 type = "passive"; 4578 }; 4579 4580 cpu6_bottom_alert1: trip-point1 { 4581 temperature = <95000>; 4582 hysteresis = <2000>; 4583 type = "passive"; 4584 }; 4585 4586 cpu6_bottom_crit: cpu_crit { 4587 temperature = <110000>; 4588 hysteresis = <1000>; 4589 type = "critical"; 4590 }; 4591 }; 4592 4593 cooling-maps { 4594 map0 { 4595 trip = <&cpu6_bottom_alert0>; 4596 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4597 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4598 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4599 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4600 }; 4601 map1 { 4602 trip = <&cpu6_bottom_alert1>; 4603 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4604 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4605 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4606 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4607 }; 4608 }; 4609 }; 4610 4611 cpu7-bottom-thermal { 4612 polling-delay-passive = <250>; 4613 polling-delay = <1000>; 4614 4615 thermal-sensors = <&tsens0 14>; 4616 4617 trips { 4618 cpu7_bottom_alert0: trip-point0 { 4619 temperature = <90000>; 4620 hysteresis = <2000>; 4621 type = "passive"; 4622 }; 4623 4624 cpu7_bottom_alert1: trip-point1 { 4625 temperature = <95000>; 4626 hysteresis = <2000>; 4627 type = "passive"; 4628 }; 4629 4630 cpu7_bottom_crit: cpu_crit { 4631 temperature = <110000>; 4632 hysteresis = <1000>; 4633 type = "critical"; 4634 }; 4635 }; 4636 4637 cooling-maps { 4638 map0 { 4639 trip = <&cpu7_bottom_alert0>; 4640 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4641 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4642 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4643 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4644 }; 4645 map1 { 4646 trip = <&cpu7_bottom_alert1>; 4647 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4648 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4649 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4650 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4651 }; 4652 }; 4653 }; 4654 4655 aoss0-thermal { 4656 polling-delay-passive = <250>; 4657 polling-delay = <1000>; 4658 4659 thermal-sensors = <&tsens0 0>; 4660 4661 trips { 4662 aoss0_alert0: trip-point0 { 4663 temperature = <90000>; 4664 hysteresis = <2000>; 4665 type = "hot"; 4666 }; 4667 }; 4668 }; 4669 4670 cluster0-thermal { 4671 polling-delay-passive = <250>; 4672 polling-delay = <1000>; 4673 4674 thermal-sensors = <&tsens0 5>; 4675 4676 trips { 4677 cluster0_alert0: trip-point0 { 4678 temperature = <90000>; 4679 hysteresis = <2000>; 4680 type = "hot"; 4681 }; 4682 cluster0_crit: cluster0_crit { 4683 temperature = <110000>; 4684 hysteresis = <2000>; 4685 type = "critical"; 4686 }; 4687 }; 4688 }; 4689 4690 cluster1-thermal { 4691 polling-delay-passive = <250>; 4692 polling-delay = <1000>; 4693 4694 thermal-sensors = <&tsens0 6>; 4695 4696 trips { 4697 cluster1_alert0: trip-point0 { 4698 temperature = <90000>; 4699 hysteresis = <2000>; 4700 type = "hot"; 4701 }; 4702 cluster1_crit: cluster1_crit { 4703 temperature = <110000>; 4704 hysteresis = <2000>; 4705 type = "critical"; 4706 }; 4707 }; 4708 }; 4709 4710 gpu-thermal-top { 4711 polling-delay-passive = <250>; 4712 polling-delay = <1000>; 4713 4714 thermal-sensors = <&tsens0 15>; 4715 4716 trips { 4717 gpu1_alert0: trip-point0 { 4718 temperature = <90000>; 4719 hysteresis = <2000>; 4720 type = "hot"; 4721 }; 4722 }; 4723 }; 4724 4725 aoss1-thermal { 4726 polling-delay-passive = <250>; 4727 polling-delay = <1000>; 4728 4729 thermal-sensors = <&tsens1 0>; 4730 4731 trips { 4732 aoss1_alert0: trip-point0 { 4733 temperature = <90000>; 4734 hysteresis = <2000>; 4735 type = "hot"; 4736 }; 4737 }; 4738 }; 4739 4740 wlan-thermal { 4741 polling-delay-passive = <250>; 4742 polling-delay = <1000>; 4743 4744 thermal-sensors = <&tsens1 1>; 4745 4746 trips { 4747 wlan_alert0: trip-point0 { 4748 temperature = <90000>; 4749 hysteresis = <2000>; 4750 type = "hot"; 4751 }; 4752 }; 4753 }; 4754 4755 video-thermal { 4756 polling-delay-passive = <250>; 4757 polling-delay = <1000>; 4758 4759 thermal-sensors = <&tsens1 2>; 4760 4761 trips { 4762 video_alert0: trip-point0 { 4763 temperature = <90000>; 4764 hysteresis = <2000>; 4765 type = "hot"; 4766 }; 4767 }; 4768 }; 4769 4770 mem-thermal { 4771 polling-delay-passive = <250>; 4772 polling-delay = <1000>; 4773 4774 thermal-sensors = <&tsens1 3>; 4775 4776 trips { 4777 mem_alert0: trip-point0 { 4778 temperature = <90000>; 4779 hysteresis = <2000>; 4780 type = "hot"; 4781 }; 4782 }; 4783 }; 4784 4785 q6-hvx-thermal { 4786 polling-delay-passive = <250>; 4787 polling-delay = <1000>; 4788 4789 thermal-sensors = <&tsens1 4>; 4790 4791 trips { 4792 q6_hvx_alert0: trip-point0 { 4793 temperature = <90000>; 4794 hysteresis = <2000>; 4795 type = "hot"; 4796 }; 4797 }; 4798 }; 4799 4800 camera-thermal { 4801 polling-delay-passive = <250>; 4802 polling-delay = <1000>; 4803 4804 thermal-sensors = <&tsens1 5>; 4805 4806 trips { 4807 camera_alert0: trip-point0 { 4808 temperature = <90000>; 4809 hysteresis = <2000>; 4810 type = "hot"; 4811 }; 4812 }; 4813 }; 4814 4815 compute-thermal { 4816 polling-delay-passive = <250>; 4817 polling-delay = <1000>; 4818 4819 thermal-sensors = <&tsens1 6>; 4820 4821 trips { 4822 compute_alert0: trip-point0 { 4823 temperature = <90000>; 4824 hysteresis = <2000>; 4825 type = "hot"; 4826 }; 4827 }; 4828 }; 4829 4830 npu-thermal { 4831 polling-delay-passive = <250>; 4832 polling-delay = <1000>; 4833 4834 thermal-sensors = <&tsens1 7>; 4835 4836 trips { 4837 npu_alert0: trip-point0 { 4838 temperature = <90000>; 4839 hysteresis = <2000>; 4840 type = "hot"; 4841 }; 4842 }; 4843 }; 4844 4845 gpu-thermal-bottom { 4846 polling-delay-passive = <250>; 4847 polling-delay = <1000>; 4848 4849 thermal-sensors = <&tsens1 8>; 4850 4851 trips { 4852 gpu2_alert0: trip-point0 { 4853 temperature = <90000>; 4854 hysteresis = <2000>; 4855 type = "hot"; 4856 }; 4857 }; 4858 }; 4859 }; 4860}; 4861