1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 ethernet0 = &gmac2io; 31 ethernet1 = &gmac2phy; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x0 0x0>; 42 clocks = <&cru ARMCLK>; 43 #cooling-cells = <2>; 44 cpu-idle-states = <&CPU_SLEEP>; 45 dynamic-power-coefficient = <120>; 46 enable-method = "psci"; 47 next-level-cache = <&l2>; 48 operating-points-v2 = <&cpu0_opp_table>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x0 0x1>; 55 clocks = <&cru ARMCLK>; 56 #cooling-cells = <2>; 57 cpu-idle-states = <&CPU_SLEEP>; 58 dynamic-power-coefficient = <120>; 59 enable-method = "psci"; 60 next-level-cache = <&l2>; 61 operating-points-v2 = <&cpu0_opp_table>; 62 }; 63 64 cpu2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x0 0x2>; 68 clocks = <&cru ARMCLK>; 69 #cooling-cells = <2>; 70 cpu-idle-states = <&CPU_SLEEP>; 71 dynamic-power-coefficient = <120>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 operating-points-v2 = <&cpu0_opp_table>; 75 }; 76 77 cpu3: cpu@3 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a53"; 80 reg = <0x0 0x3>; 81 clocks = <&cru ARMCLK>; 82 #cooling-cells = <2>; 83 cpu-idle-states = <&CPU_SLEEP>; 84 dynamic-power-coefficient = <120>; 85 enable-method = "psci"; 86 next-level-cache = <&l2>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 }; 102 103 l2: l2-cache0 { 104 compatible = "cache"; 105 }; 106 }; 107 108 cpu0_opp_table: opp_table0 { 109 compatible = "operating-points-v2"; 110 opp-shared; 111 112 opp-408000000 { 113 opp-hz = /bits/ 64 <408000000>; 114 opp-microvolt = <950000>; 115 clock-latency-ns = <40000>; 116 opp-suspend; 117 }; 118 opp-600000000 { 119 opp-hz = /bits/ 64 <600000000>; 120 opp-microvolt = <950000>; 121 clock-latency-ns = <40000>; 122 }; 123 opp-816000000 { 124 opp-hz = /bits/ 64 <816000000>; 125 opp-microvolt = <1000000>; 126 clock-latency-ns = <40000>; 127 }; 128 opp-1008000000 { 129 opp-hz = /bits/ 64 <1008000000>; 130 opp-microvolt = <1100000>; 131 clock-latency-ns = <40000>; 132 }; 133 opp-1200000000 { 134 opp-hz = /bits/ 64 <1200000000>; 135 opp-microvolt = <1225000>; 136 clock-latency-ns = <40000>; 137 }; 138 opp-1296000000 { 139 opp-hz = /bits/ 64 <1296000000>; 140 opp-microvolt = <1300000>; 141 clock-latency-ns = <40000>; 142 }; 143 }; 144 145 analog_sound: analog-sound { 146 compatible = "simple-audio-card"; 147 simple-audio-card,format = "i2s"; 148 simple-audio-card,mclk-fs = <256>; 149 simple-audio-card,name = "Analog"; 150 status = "disabled"; 151 152 simple-audio-card,cpu { 153 sound-dai = <&i2s1>; 154 }; 155 156 simple-audio-card,codec { 157 sound-dai = <&codec>; 158 }; 159 }; 160 161 arm-pmu { 162 compatible = "arm,cortex-a53-pmu"; 163 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 167 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 168 }; 169 170 display_subsystem: display-subsystem { 171 compatible = "rockchip,display-subsystem"; 172 ports = <&vop_out>; 173 }; 174 175 hdmi_sound: hdmi-sound { 176 compatible = "simple-audio-card"; 177 simple-audio-card,format = "i2s"; 178 simple-audio-card,mclk-fs = <128>; 179 simple-audio-card,name = "HDMI"; 180 status = "disabled"; 181 182 simple-audio-card,cpu { 183 sound-dai = <&i2s0>; 184 }; 185 186 simple-audio-card,codec { 187 sound-dai = <&hdmi>; 188 }; 189 }; 190 191 psci { 192 compatible = "arm,psci-1.0", "arm,psci-0.2"; 193 method = "smc"; 194 }; 195 196 timer { 197 compatible = "arm,armv8-timer"; 198 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 199 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 200 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 201 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 202 }; 203 204 xin24m: xin24m { 205 compatible = "fixed-clock"; 206 #clock-cells = <0>; 207 clock-frequency = <24000000>; 208 clock-output-names = "xin24m"; 209 }; 210 211 i2s0: i2s@ff000000 { 212 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 213 reg = <0x0 0xff000000 0x0 0x1000>; 214 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 216 clock-names = "i2s_clk", "i2s_hclk"; 217 dmas = <&dmac 11>, <&dmac 12>; 218 dma-names = "tx", "rx"; 219 #sound-dai-cells = <0>; 220 status = "disabled"; 221 }; 222 223 i2s1: i2s@ff010000 { 224 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 225 reg = <0x0 0xff010000 0x0 0x1000>; 226 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 228 clock-names = "i2s_clk", "i2s_hclk"; 229 dmas = <&dmac 14>, <&dmac 15>; 230 dma-names = "tx", "rx"; 231 #sound-dai-cells = <0>; 232 status = "disabled"; 233 }; 234 235 i2s2: i2s@ff020000 { 236 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 237 reg = <0x0 0xff020000 0x0 0x1000>; 238 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 240 clock-names = "i2s_clk", "i2s_hclk"; 241 dmas = <&dmac 0>, <&dmac 1>; 242 dma-names = "tx", "rx"; 243 #sound-dai-cells = <0>; 244 status = "disabled"; 245 }; 246 247 spdif: spdif@ff030000 { 248 compatible = "rockchip,rk3328-spdif"; 249 reg = <0x0 0xff030000 0x0 0x1000>; 250 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 252 clock-names = "mclk", "hclk"; 253 dmas = <&dmac 10>; 254 dma-names = "tx"; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&spdifm2_tx>; 257 #sound-dai-cells = <0>; 258 status = "disabled"; 259 }; 260 261 pdm: pdm@ff040000 { 262 compatible = "rockchip,pdm"; 263 reg = <0x0 0xff040000 0x0 0x1000>; 264 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 265 clock-names = "pdm_clk", "pdm_hclk"; 266 dmas = <&dmac 16>; 267 dma-names = "rx"; 268 pinctrl-names = "default", "sleep"; 269 pinctrl-0 = <&pdmm0_clk 270 &pdmm0_sdi0 271 &pdmm0_sdi1 272 &pdmm0_sdi2 273 &pdmm0_sdi3>; 274 pinctrl-1 = <&pdmm0_clk_sleep 275 &pdmm0_sdi0_sleep 276 &pdmm0_sdi1_sleep 277 &pdmm0_sdi2_sleep 278 &pdmm0_sdi3_sleep>; 279 status = "disabled"; 280 }; 281 282 grf: syscon@ff100000 { 283 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 284 reg = <0x0 0xff100000 0x0 0x1000>; 285 286 io_domains: io-domains { 287 compatible = "rockchip,rk3328-io-voltage-domain"; 288 status = "disabled"; 289 }; 290 291 grf_gpio: gpio { 292 compatible = "rockchip,rk3328-grf-gpio"; 293 gpio-controller; 294 #gpio-cells = <2>; 295 }; 296 297 power: power-controller { 298 compatible = "rockchip,rk3328-power-controller"; 299 #power-domain-cells = <1>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 303 power-domain@RK3328_PD_HEVC { 304 reg = <RK3328_PD_HEVC>; 305 #power-domain-cells = <0>; 306 }; 307 power-domain@RK3328_PD_VIDEO { 308 reg = <RK3328_PD_VIDEO>; 309 #power-domain-cells = <0>; 310 }; 311 power-domain@RK3328_PD_VPU { 312 reg = <RK3328_PD_VPU>; 313 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 314 #power-domain-cells = <0>; 315 }; 316 }; 317 318 reboot-mode { 319 compatible = "syscon-reboot-mode"; 320 offset = <0x5c8>; 321 mode-normal = <BOOT_NORMAL>; 322 mode-recovery = <BOOT_RECOVERY>; 323 mode-bootloader = <BOOT_FASTBOOT>; 324 mode-loader = <BOOT_BL_DOWNLOAD>; 325 }; 326 }; 327 328 uart0: serial@ff110000 { 329 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 330 reg = <0x0 0xff110000 0x0 0x100>; 331 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 333 clock-names = "baudclk", "apb_pclk"; 334 dmas = <&dmac 2>, <&dmac 3>; 335 dma-names = "tx", "rx"; 336 pinctrl-names = "default"; 337 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 338 reg-io-width = <4>; 339 reg-shift = <2>; 340 status = "disabled"; 341 }; 342 343 uart1: serial@ff120000 { 344 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 345 reg = <0x0 0xff120000 0x0 0x100>; 346 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 348 clock-names = "baudclk", "apb_pclk"; 349 dmas = <&dmac 4>, <&dmac 5>; 350 dma-names = "tx", "rx"; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 353 reg-io-width = <4>; 354 reg-shift = <2>; 355 status = "disabled"; 356 }; 357 358 uart2: serial@ff130000 { 359 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 360 reg = <0x0 0xff130000 0x0 0x100>; 361 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 363 clock-names = "baudclk", "apb_pclk"; 364 dmas = <&dmac 6>, <&dmac 7>; 365 dma-names = "tx", "rx"; 366 pinctrl-names = "default"; 367 pinctrl-0 = <&uart2m1_xfer>; 368 reg-io-width = <4>; 369 reg-shift = <2>; 370 status = "disabled"; 371 }; 372 373 i2c0: i2c@ff150000 { 374 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 375 reg = <0x0 0xff150000 0x0 0x1000>; 376 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 380 clock-names = "i2c", "pclk"; 381 pinctrl-names = "default"; 382 pinctrl-0 = <&i2c0_xfer>; 383 status = "disabled"; 384 }; 385 386 i2c1: i2c@ff160000 { 387 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 388 reg = <0x0 0xff160000 0x0 0x1000>; 389 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 393 clock-names = "i2c", "pclk"; 394 pinctrl-names = "default"; 395 pinctrl-0 = <&i2c1_xfer>; 396 status = "disabled"; 397 }; 398 399 i2c2: i2c@ff170000 { 400 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 401 reg = <0x0 0xff170000 0x0 0x1000>; 402 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 406 clock-names = "i2c", "pclk"; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&i2c2_xfer>; 409 status = "disabled"; 410 }; 411 412 i2c3: i2c@ff180000 { 413 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 414 reg = <0x0 0xff180000 0x0 0x1000>; 415 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 419 clock-names = "i2c", "pclk"; 420 pinctrl-names = "default"; 421 pinctrl-0 = <&i2c3_xfer>; 422 status = "disabled"; 423 }; 424 425 spi0: spi@ff190000 { 426 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 427 reg = <0x0 0xff190000 0x0 0x1000>; 428 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 432 clock-names = "spiclk", "apb_pclk"; 433 dmas = <&dmac 8>, <&dmac 9>; 434 dma-names = "tx", "rx"; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 437 status = "disabled"; 438 }; 439 440 wdt: watchdog@ff1a0000 { 441 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt"; 442 reg = <0x0 0xff1a0000 0x0 0x100>; 443 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&cru PCLK_WDT>; 445 }; 446 447 pwm0: pwm@ff1b0000 { 448 compatible = "rockchip,rk3328-pwm"; 449 reg = <0x0 0xff1b0000 0x0 0x10>; 450 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 451 clock-names = "pwm", "pclk"; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&pwm0_pin>; 454 #pwm-cells = <3>; 455 status = "disabled"; 456 }; 457 458 pwm1: pwm@ff1b0010 { 459 compatible = "rockchip,rk3328-pwm"; 460 reg = <0x0 0xff1b0010 0x0 0x10>; 461 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 462 clock-names = "pwm", "pclk"; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&pwm1_pin>; 465 #pwm-cells = <3>; 466 status = "disabled"; 467 }; 468 469 pwm2: pwm@ff1b0020 { 470 compatible = "rockchip,rk3328-pwm"; 471 reg = <0x0 0xff1b0020 0x0 0x10>; 472 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 473 clock-names = "pwm", "pclk"; 474 pinctrl-names = "default"; 475 pinctrl-0 = <&pwm2_pin>; 476 #pwm-cells = <3>; 477 status = "disabled"; 478 }; 479 480 pwm3: pwm@ff1b0030 { 481 compatible = "rockchip,rk3328-pwm"; 482 reg = <0x0 0xff1b0030 0x0 0x10>; 483 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 485 clock-names = "pwm", "pclk"; 486 pinctrl-names = "default"; 487 pinctrl-0 = <&pwmir_pin>; 488 #pwm-cells = <3>; 489 status = "disabled"; 490 }; 491 492 dmac: dma-controller@ff1f0000 { 493 compatible = "arm,pl330", "arm,primecell"; 494 reg = <0x0 0xff1f0000 0x0 0x4000>; 495 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 497 arm,pl330-periph-burst; 498 clocks = <&cru ACLK_DMAC>; 499 clock-names = "apb_pclk"; 500 #dma-cells = <1>; 501 }; 502 503 thermal-zones { 504 soc_thermal: soc-thermal { 505 polling-delay-passive = <20>; 506 polling-delay = <1000>; 507 sustainable-power = <1000>; 508 509 thermal-sensors = <&tsadc 0>; 510 511 trips { 512 threshold: trip-point0 { 513 temperature = <70000>; 514 hysteresis = <2000>; 515 type = "passive"; 516 }; 517 target: trip-point1 { 518 temperature = <85000>; 519 hysteresis = <2000>; 520 type = "passive"; 521 }; 522 soc_crit: soc-crit { 523 temperature = <95000>; 524 hysteresis = <2000>; 525 type = "critical"; 526 }; 527 }; 528 529 cooling-maps { 530 map0 { 531 trip = <&target>; 532 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 533 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 534 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 535 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 536 contribution = <4096>; 537 }; 538 }; 539 }; 540 541 }; 542 543 tsadc: tsadc@ff250000 { 544 compatible = "rockchip,rk3328-tsadc"; 545 reg = <0x0 0xff250000 0x0 0x100>; 546 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 547 assigned-clocks = <&cru SCLK_TSADC>; 548 assigned-clock-rates = <50000>; 549 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 550 clock-names = "tsadc", "apb_pclk"; 551 pinctrl-names = "init", "default", "sleep"; 552 pinctrl-0 = <&otp_pin>; 553 pinctrl-1 = <&otp_out>; 554 pinctrl-2 = <&otp_pin>; 555 resets = <&cru SRST_TSADC>; 556 reset-names = "tsadc-apb"; 557 rockchip,grf = <&grf>; 558 rockchip,hw-tshut-temp = <100000>; 559 #thermal-sensor-cells = <1>; 560 status = "disabled"; 561 }; 562 563 efuse: efuse@ff260000 { 564 compatible = "rockchip,rk3328-efuse"; 565 reg = <0x0 0xff260000 0x0 0x50>; 566 #address-cells = <1>; 567 #size-cells = <1>; 568 clocks = <&cru SCLK_EFUSE>; 569 clock-names = "pclk_efuse"; 570 rockchip,efuse-size = <0x20>; 571 572 /* Data cells */ 573 efuse_id: id@7 { 574 reg = <0x07 0x10>; 575 }; 576 cpu_leakage: cpu-leakage@17 { 577 reg = <0x17 0x1>; 578 }; 579 logic_leakage: logic-leakage@19 { 580 reg = <0x19 0x1>; 581 }; 582 efuse_cpu_version: cpu-version@1a { 583 reg = <0x1a 0x1>; 584 bits = <3 3>; 585 }; 586 }; 587 588 saradc: adc@ff280000 { 589 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 590 reg = <0x0 0xff280000 0x0 0x100>; 591 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 592 #io-channel-cells = <1>; 593 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 594 clock-names = "saradc", "apb_pclk"; 595 resets = <&cru SRST_SARADC_P>; 596 reset-names = "saradc-apb"; 597 status = "disabled"; 598 }; 599 600 gpu: gpu@ff300000 { 601 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 602 reg = <0x0 0xff300000 0x0 0x30000>; 603 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 610 interrupt-names = "gp", 611 "gpmmu", 612 "pp", 613 "pp0", 614 "ppmmu0", 615 "pp1", 616 "ppmmu1"; 617 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 618 clock-names = "bus", "core"; 619 resets = <&cru SRST_GPU_A>; 620 }; 621 622 h265e_mmu: iommu@ff330200 { 623 compatible = "rockchip,iommu"; 624 reg = <0x0 0xff330200 0 0x100>; 625 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 626 interrupt-names = "h265e_mmu"; 627 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 628 clock-names = "aclk", "iface"; 629 #iommu-cells = <0>; 630 status = "disabled"; 631 }; 632 633 vepu_mmu: iommu@ff340800 { 634 compatible = "rockchip,iommu"; 635 reg = <0x0 0xff340800 0x0 0x40>; 636 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 637 interrupt-names = "vepu_mmu"; 638 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 639 clock-names = "aclk", "iface"; 640 #iommu-cells = <0>; 641 status = "disabled"; 642 }; 643 644 vpu: video-codec@ff350000 { 645 compatible = "rockchip,rk3328-vpu"; 646 reg = <0x0 0xff350000 0x0 0x800>; 647 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 648 interrupt-names = "vdpu"; 649 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 650 clock-names = "aclk", "hclk"; 651 iommus = <&vpu_mmu>; 652 power-domains = <&power RK3328_PD_VPU>; 653 }; 654 655 vpu_mmu: iommu@ff350800 { 656 compatible = "rockchip,iommu"; 657 reg = <0x0 0xff350800 0x0 0x40>; 658 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 659 interrupt-names = "vpu_mmu"; 660 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 661 clock-names = "aclk", "iface"; 662 #iommu-cells = <0>; 663 power-domains = <&power RK3328_PD_VPU>; 664 }; 665 666 rkvdec_mmu: iommu@ff360480 { 667 compatible = "rockchip,iommu"; 668 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 669 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 670 interrupt-names = "rkvdec_mmu"; 671 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 672 clock-names = "aclk", "iface"; 673 #iommu-cells = <0>; 674 status = "disabled"; 675 }; 676 677 vop: vop@ff370000 { 678 compatible = "rockchip,rk3328-vop"; 679 reg = <0x0 0xff370000 0x0 0x3efc>; 680 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 682 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 683 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 684 reset-names = "axi", "ahb", "dclk"; 685 iommus = <&vop_mmu>; 686 status = "disabled"; 687 688 vop_out: port { 689 #address-cells = <1>; 690 #size-cells = <0>; 691 692 vop_out_hdmi: endpoint@0 { 693 reg = <0>; 694 remote-endpoint = <&hdmi_in_vop>; 695 }; 696 }; 697 }; 698 699 vop_mmu: iommu@ff373f00 { 700 compatible = "rockchip,iommu"; 701 reg = <0x0 0xff373f00 0x0 0x100>; 702 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 703 interrupt-names = "vop_mmu"; 704 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 705 clock-names = "aclk", "iface"; 706 #iommu-cells = <0>; 707 status = "disabled"; 708 }; 709 710 hdmi: hdmi@ff3c0000 { 711 compatible = "rockchip,rk3328-dw-hdmi"; 712 reg = <0x0 0xff3c0000 0x0 0x20000>; 713 reg-io-width = <4>; 714 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&cru PCLK_HDMI>, 717 <&cru SCLK_HDMI_SFC>, 718 <&cru SCLK_RTC32K>; 719 clock-names = "iahb", 720 "isfr", 721 "cec"; 722 phys = <&hdmiphy>; 723 phy-names = "hdmi"; 724 pinctrl-names = "default"; 725 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 726 rockchip,grf = <&grf>; 727 #sound-dai-cells = <0>; 728 status = "disabled"; 729 730 ports { 731 hdmi_in: port { 732 hdmi_in_vop: endpoint { 733 remote-endpoint = <&vop_out_hdmi>; 734 }; 735 }; 736 }; 737 }; 738 739 codec: codec@ff410000 { 740 compatible = "rockchip,rk3328-codec"; 741 reg = <0x0 0xff410000 0x0 0x1000>; 742 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 743 clock-names = "pclk", "mclk"; 744 rockchip,grf = <&grf>; 745 #sound-dai-cells = <0>; 746 status = "disabled"; 747 }; 748 749 hdmiphy: phy@ff430000 { 750 compatible = "rockchip,rk3328-hdmi-phy"; 751 reg = <0x0 0xff430000 0x0 0x10000>; 752 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 754 clock-names = "sysclk", "refoclk", "refpclk"; 755 clock-output-names = "hdmi_phy"; 756 #clock-cells = <0>; 757 nvmem-cells = <&efuse_cpu_version>; 758 nvmem-cell-names = "cpu-version"; 759 #phy-cells = <0>; 760 status = "disabled"; 761 }; 762 763 cru: clock-controller@ff440000 { 764 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 765 reg = <0x0 0xff440000 0x0 0x1000>; 766 rockchip,grf = <&grf>; 767 #clock-cells = <1>; 768 #reset-cells = <1>; 769 assigned-clocks = 770 /* 771 * CPLL should run at 1200, but that is to high for 772 * the initial dividers of most of its children. 773 * We need set cpll child clk div first, 774 * and then set the cpll frequency. 775 */ 776 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 777 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 778 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 779 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 780 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 781 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 782 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 783 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 784 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 785 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 786 <&cru SCLK_WIFI>, <&cru ARMCLK>, 787 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 788 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 789 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 790 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 791 <&cru SCLK_RTC32K>; 792 assigned-clock-parents = 793 <&cru HDMIPHY>, <&cru PLL_APLL>, 794 <&cru PLL_GPLL>, <&xin24m>, 795 <&xin24m>, <&xin24m>; 796 assigned-clock-rates = 797 <0>, <61440000>, 798 <0>, <24000000>, 799 <24000000>, <24000000>, 800 <15000000>, <15000000>, 801 <100000000>, <100000000>, 802 <100000000>, <100000000>, 803 <50000000>, <100000000>, 804 <100000000>, <100000000>, 805 <50000000>, <50000000>, 806 <50000000>, <50000000>, 807 <24000000>, <600000000>, 808 <491520000>, <1200000000>, 809 <150000000>, <75000000>, 810 <75000000>, <150000000>, 811 <75000000>, <75000000>, 812 <32768>; 813 }; 814 815 usb2phy_grf: syscon@ff450000 { 816 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 817 "simple-mfd"; 818 reg = <0x0 0xff450000 0x0 0x10000>; 819 #address-cells = <1>; 820 #size-cells = <1>; 821 822 u2phy: usb2phy@100 { 823 compatible = "rockchip,rk3328-usb2phy"; 824 reg = <0x100 0x10>; 825 clocks = <&xin24m>; 826 clock-names = "phyclk"; 827 clock-output-names = "usb480m_phy"; 828 #clock-cells = <0>; 829 assigned-clocks = <&cru USB480M>; 830 assigned-clock-parents = <&u2phy>; 831 status = "disabled"; 832 833 u2phy_otg: otg-port { 834 #phy-cells = <0>; 835 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 838 interrupt-names = "otg-bvalid", "otg-id", 839 "linestate"; 840 status = "disabled"; 841 }; 842 843 u2phy_host: host-port { 844 #phy-cells = <0>; 845 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 846 interrupt-names = "linestate"; 847 status = "disabled"; 848 }; 849 }; 850 }; 851 852 sdmmc: mmc@ff500000 { 853 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 854 reg = <0x0 0xff500000 0x0 0x4000>; 855 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 857 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 858 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 859 fifo-depth = <0x100>; 860 max-frequency = <150000000>; 861 status = "disabled"; 862 }; 863 864 sdio: mmc@ff510000 { 865 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 866 reg = <0x0 0xff510000 0x0 0x4000>; 867 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 869 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 870 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 871 fifo-depth = <0x100>; 872 max-frequency = <150000000>; 873 status = "disabled"; 874 }; 875 876 emmc: mmc@ff520000 { 877 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 878 reg = <0x0 0xff520000 0x0 0x4000>; 879 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 881 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 882 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 883 fifo-depth = <0x100>; 884 max-frequency = <150000000>; 885 status = "disabled"; 886 }; 887 888 gmac2io: ethernet@ff540000 { 889 compatible = "rockchip,rk3328-gmac"; 890 reg = <0x0 0xff540000 0x0 0x10000>; 891 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 892 interrupt-names = "macirq"; 893 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 894 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 895 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 896 <&cru PCLK_MAC2IO>; 897 clock-names = "stmmaceth", "mac_clk_rx", 898 "mac_clk_tx", "clk_mac_ref", 899 "clk_mac_refout", "aclk_mac", 900 "pclk_mac"; 901 resets = <&cru SRST_GMAC2IO_A>; 902 reset-names = "stmmaceth"; 903 rockchip,grf = <&grf>; 904 snps,txpbl = <0x4>; 905 status = "disabled"; 906 }; 907 908 gmac2phy: ethernet@ff550000 { 909 compatible = "rockchip,rk3328-gmac"; 910 reg = <0x0 0xff550000 0x0 0x10000>; 911 rockchip,grf = <&grf>; 912 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 913 interrupt-names = "macirq"; 914 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 915 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 916 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 917 <&cru SCLK_MAC2PHY_OUT>; 918 clock-names = "stmmaceth", "mac_clk_rx", 919 "mac_clk_tx", "clk_mac_ref", 920 "aclk_mac", "pclk_mac", 921 "clk_macphy"; 922 resets = <&cru SRST_GMAC2PHY_A>; 923 reset-names = "stmmaceth"; 924 phy-mode = "rmii"; 925 phy-handle = <&phy>; 926 snps,txpbl = <0x4>; 927 clock_in_out = "output"; 928 status = "disabled"; 929 930 mdio { 931 compatible = "snps,dwmac-mdio"; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 935 phy: ethernet-phy@0 { 936 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 937 reg = <0>; 938 clocks = <&cru SCLK_MAC2PHY_OUT>; 939 resets = <&cru SRST_MACPHY>; 940 pinctrl-names = "default"; 941 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 942 phy-is-integrated; 943 }; 944 }; 945 }; 946 947 usb20_otg: usb@ff580000 { 948 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 949 "snps,dwc2"; 950 reg = <0x0 0xff580000 0x0 0x40000>; 951 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 952 clocks = <&cru HCLK_OTG>; 953 clock-names = "otg"; 954 dr_mode = "otg"; 955 g-np-tx-fifo-size = <16>; 956 g-rx-fifo-size = <280>; 957 g-tx-fifo-size = <256 128 128 64 32 16>; 958 phys = <&u2phy_otg>; 959 phy-names = "usb2-phy"; 960 status = "disabled"; 961 }; 962 963 usb_host0_ehci: usb@ff5c0000 { 964 compatible = "generic-ehci"; 965 reg = <0x0 0xff5c0000 0x0 0x10000>; 966 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&cru HCLK_HOST0>, <&u2phy>; 968 phys = <&u2phy_host>; 969 phy-names = "usb"; 970 status = "disabled"; 971 }; 972 973 usb_host0_ohci: usb@ff5d0000 { 974 compatible = "generic-ohci"; 975 reg = <0x0 0xff5d0000 0x0 0x10000>; 976 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 977 clocks = <&cru HCLK_HOST0>, <&u2phy>; 978 phys = <&u2phy_host>; 979 phy-names = "usb"; 980 status = "disabled"; 981 }; 982 983 usbdrd3: usb@ff600000 { 984 compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; 985 reg = <0x0 0xff600000 0x0 0x100000>; 986 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 988 <&cru ACLK_USB3OTG>; 989 clock-names = "ref_clk", "suspend_clk", 990 "bus_clk"; 991 dr_mode = "otg"; 992 phy_type = "utmi_wide"; 993 snps,dis-del-phy-power-chg-quirk; 994 snps,dis_enblslpm_quirk; 995 snps,dis-tx-ipgap-linecheck-quirk; 996 snps,dis-u2-freeclk-exists-quirk; 997 snps,dis_u2_susphy_quirk; 998 snps,dis_u3_susphy_quirk; 999 status = "disabled"; 1000 }; 1001 1002 gic: interrupt-controller@ff811000 { 1003 compatible = "arm,gic-400"; 1004 #interrupt-cells = <3>; 1005 #address-cells = <0>; 1006 interrupt-controller; 1007 reg = <0x0 0xff811000 0 0x1000>, 1008 <0x0 0xff812000 0 0x2000>, 1009 <0x0 0xff814000 0 0x2000>, 1010 <0x0 0xff816000 0 0x2000>; 1011 interrupts = <GIC_PPI 9 1012 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1013 }; 1014 1015 pinctrl: pinctrl { 1016 compatible = "rockchip,rk3328-pinctrl"; 1017 rockchip,grf = <&grf>; 1018 #address-cells = <2>; 1019 #size-cells = <2>; 1020 ranges; 1021 1022 gpio0: gpio0@ff210000 { 1023 compatible = "rockchip,gpio-bank"; 1024 reg = <0x0 0xff210000 0x0 0x100>; 1025 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&cru PCLK_GPIO0>; 1027 1028 gpio-controller; 1029 #gpio-cells = <2>; 1030 1031 interrupt-controller; 1032 #interrupt-cells = <2>; 1033 }; 1034 1035 gpio1: gpio1@ff220000 { 1036 compatible = "rockchip,gpio-bank"; 1037 reg = <0x0 0xff220000 0x0 0x100>; 1038 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&cru PCLK_GPIO1>; 1040 1041 gpio-controller; 1042 #gpio-cells = <2>; 1043 1044 interrupt-controller; 1045 #interrupt-cells = <2>; 1046 }; 1047 1048 gpio2: gpio2@ff230000 { 1049 compatible = "rockchip,gpio-bank"; 1050 reg = <0x0 0xff230000 0x0 0x100>; 1051 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1052 clocks = <&cru PCLK_GPIO2>; 1053 1054 gpio-controller; 1055 #gpio-cells = <2>; 1056 1057 interrupt-controller; 1058 #interrupt-cells = <2>; 1059 }; 1060 1061 gpio3: gpio3@ff240000 { 1062 compatible = "rockchip,gpio-bank"; 1063 reg = <0x0 0xff240000 0x0 0x100>; 1064 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&cru PCLK_GPIO3>; 1066 1067 gpio-controller; 1068 #gpio-cells = <2>; 1069 1070 interrupt-controller; 1071 #interrupt-cells = <2>; 1072 }; 1073 1074 pcfg_pull_up: pcfg-pull-up { 1075 bias-pull-up; 1076 }; 1077 1078 pcfg_pull_down: pcfg-pull-down { 1079 bias-pull-down; 1080 }; 1081 1082 pcfg_pull_none: pcfg-pull-none { 1083 bias-disable; 1084 }; 1085 1086 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1087 bias-disable; 1088 drive-strength = <2>; 1089 }; 1090 1091 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1092 bias-pull-up; 1093 drive-strength = <2>; 1094 }; 1095 1096 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1097 bias-pull-up; 1098 drive-strength = <4>; 1099 }; 1100 1101 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1102 bias-disable; 1103 drive-strength = <4>; 1104 }; 1105 1106 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1107 bias-pull-down; 1108 drive-strength = <4>; 1109 }; 1110 1111 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1112 bias-disable; 1113 drive-strength = <8>; 1114 }; 1115 1116 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1117 bias-pull-up; 1118 drive-strength = <8>; 1119 }; 1120 1121 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1122 bias-disable; 1123 drive-strength = <12>; 1124 }; 1125 1126 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1127 bias-pull-up; 1128 drive-strength = <12>; 1129 }; 1130 1131 pcfg_output_high: pcfg-output-high { 1132 output-high; 1133 }; 1134 1135 pcfg_output_low: pcfg-output-low { 1136 output-low; 1137 }; 1138 1139 pcfg_input_high: pcfg-input-high { 1140 bias-pull-up; 1141 input-enable; 1142 }; 1143 1144 pcfg_input: pcfg-input { 1145 input-enable; 1146 }; 1147 1148 i2c0 { 1149 i2c0_xfer: i2c0-xfer { 1150 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1151 <2 RK_PD1 1 &pcfg_pull_none>; 1152 }; 1153 }; 1154 1155 i2c1 { 1156 i2c1_xfer: i2c1-xfer { 1157 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1158 <2 RK_PA5 2 &pcfg_pull_none>; 1159 }; 1160 }; 1161 1162 i2c2 { 1163 i2c2_xfer: i2c2-xfer { 1164 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1165 <2 RK_PB6 1 &pcfg_pull_none>; 1166 }; 1167 }; 1168 1169 i2c3 { 1170 i2c3_xfer: i2c3-xfer { 1171 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1172 <0 RK_PA6 2 &pcfg_pull_none>; 1173 }; 1174 i2c3_pins: i2c3-pins { 1175 rockchip,pins = 1176 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1177 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1178 }; 1179 }; 1180 1181 hdmi_i2c { 1182 hdmii2c_xfer: hdmii2c-xfer { 1183 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1184 <0 RK_PA6 1 &pcfg_pull_none>; 1185 }; 1186 }; 1187 1188 pdm-0 { 1189 pdmm0_clk: pdmm0-clk { 1190 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1191 }; 1192 1193 pdmm0_fsync: pdmm0-fsync { 1194 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1195 }; 1196 1197 pdmm0_sdi0: pdmm0-sdi0 { 1198 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1199 }; 1200 1201 pdmm0_sdi1: pdmm0-sdi1 { 1202 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1203 }; 1204 1205 pdmm0_sdi2: pdmm0-sdi2 { 1206 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1207 }; 1208 1209 pdmm0_sdi3: pdmm0-sdi3 { 1210 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1211 }; 1212 1213 pdmm0_clk_sleep: pdmm0-clk-sleep { 1214 rockchip,pins = 1215 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1216 }; 1217 1218 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1219 rockchip,pins = 1220 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1221 }; 1222 1223 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1224 rockchip,pins = 1225 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1226 }; 1227 1228 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1229 rockchip,pins = 1230 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1231 }; 1232 1233 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1234 rockchip,pins = 1235 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1236 }; 1237 1238 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1239 rockchip,pins = 1240 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1241 }; 1242 }; 1243 1244 tsadc { 1245 otp_pin: otp-pin { 1246 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1247 }; 1248 1249 otp_out: otp-out { 1250 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1251 }; 1252 }; 1253 1254 uart0 { 1255 uart0_xfer: uart0-xfer { 1256 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1257 <1 RK_PB0 1 &pcfg_pull_up>; 1258 }; 1259 1260 uart0_cts: uart0-cts { 1261 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1262 }; 1263 1264 uart0_rts: uart0-rts { 1265 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1266 }; 1267 1268 uart0_rts_pin: uart0-rts-pin { 1269 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1270 }; 1271 }; 1272 1273 uart1 { 1274 uart1_xfer: uart1-xfer { 1275 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, 1276 <3 RK_PA6 4 &pcfg_pull_up>; 1277 }; 1278 1279 uart1_cts: uart1-cts { 1280 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1281 }; 1282 1283 uart1_rts: uart1-rts { 1284 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1285 }; 1286 1287 uart1_rts_pin: uart1-rts-pin { 1288 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1289 }; 1290 }; 1291 1292 uart2-0 { 1293 uart2m0_xfer: uart2m0-xfer { 1294 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, 1295 <1 RK_PA1 2 &pcfg_pull_up>; 1296 }; 1297 }; 1298 1299 uart2-1 { 1300 uart2m1_xfer: uart2m1-xfer { 1301 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 1302 <2 RK_PA1 1 &pcfg_pull_up>; 1303 }; 1304 }; 1305 1306 spi0-0 { 1307 spi0m0_clk: spi0m0-clk { 1308 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1309 }; 1310 1311 spi0m0_cs0: spi0m0-cs0 { 1312 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1313 }; 1314 1315 spi0m0_tx: spi0m0-tx { 1316 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1317 }; 1318 1319 spi0m0_rx: spi0m0-rx { 1320 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1321 }; 1322 1323 spi0m0_cs1: spi0m0-cs1 { 1324 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1325 }; 1326 }; 1327 1328 spi0-1 { 1329 spi0m1_clk: spi0m1-clk { 1330 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1331 }; 1332 1333 spi0m1_cs0: spi0m1-cs0 { 1334 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1335 }; 1336 1337 spi0m1_tx: spi0m1-tx { 1338 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1339 }; 1340 1341 spi0m1_rx: spi0m1-rx { 1342 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1343 }; 1344 1345 spi0m1_cs1: spi0m1-cs1 { 1346 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1347 }; 1348 }; 1349 1350 spi0-2 { 1351 spi0m2_clk: spi0m2-clk { 1352 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1353 }; 1354 1355 spi0m2_cs0: spi0m2-cs0 { 1356 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1357 }; 1358 1359 spi0m2_tx: spi0m2-tx { 1360 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1361 }; 1362 1363 spi0m2_rx: spi0m2-rx { 1364 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1365 }; 1366 }; 1367 1368 i2s1 { 1369 i2s1_mclk: i2s1-mclk { 1370 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1371 }; 1372 1373 i2s1_sclk: i2s1-sclk { 1374 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1375 }; 1376 1377 i2s1_lrckrx: i2s1-lrckrx { 1378 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1379 }; 1380 1381 i2s1_lrcktx: i2s1-lrcktx { 1382 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1383 }; 1384 1385 i2s1_sdi: i2s1-sdi { 1386 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1387 }; 1388 1389 i2s1_sdo: i2s1-sdo { 1390 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1391 }; 1392 1393 i2s1_sdio1: i2s1-sdio1 { 1394 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1395 }; 1396 1397 i2s1_sdio2: i2s1-sdio2 { 1398 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1399 }; 1400 1401 i2s1_sdio3: i2s1-sdio3 { 1402 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1403 }; 1404 1405 i2s1_sleep: i2s1-sleep { 1406 rockchip,pins = 1407 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1408 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1409 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1410 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1411 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1412 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1413 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1414 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1415 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1416 }; 1417 }; 1418 1419 i2s2-0 { 1420 i2s2m0_mclk: i2s2m0-mclk { 1421 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1422 }; 1423 1424 i2s2m0_sclk: i2s2m0-sclk { 1425 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1426 }; 1427 1428 i2s2m0_lrckrx: i2s2m0-lrckrx { 1429 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1430 }; 1431 1432 i2s2m0_lrcktx: i2s2m0-lrcktx { 1433 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1434 }; 1435 1436 i2s2m0_sdi: i2s2m0-sdi { 1437 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1438 }; 1439 1440 i2s2m0_sdo: i2s2m0-sdo { 1441 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1442 }; 1443 1444 i2s2m0_sleep: i2s2m0-sleep { 1445 rockchip,pins = 1446 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1447 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1448 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1449 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1450 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1451 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1452 }; 1453 }; 1454 1455 i2s2-1 { 1456 i2s2m1_mclk: i2s2m1-mclk { 1457 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1458 }; 1459 1460 i2s2m1_sclk: i2s2m1-sclk { 1461 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1462 }; 1463 1464 i2s2m1_lrckrx: i2sm1-lrckrx { 1465 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1466 }; 1467 1468 i2s2m1_lrcktx: i2s2m1-lrcktx { 1469 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1470 }; 1471 1472 i2s2m1_sdi: i2s2m1-sdi { 1473 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1474 }; 1475 1476 i2s2m1_sdo: i2s2m1-sdo { 1477 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1478 }; 1479 1480 i2s2m1_sleep: i2s2m1-sleep { 1481 rockchip,pins = 1482 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1483 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1484 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1485 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1486 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1487 }; 1488 }; 1489 1490 spdif-0 { 1491 spdifm0_tx: spdifm0-tx { 1492 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1493 }; 1494 }; 1495 1496 spdif-1 { 1497 spdifm1_tx: spdifm1-tx { 1498 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1499 }; 1500 }; 1501 1502 spdif-2 { 1503 spdifm2_tx: spdifm2-tx { 1504 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1505 }; 1506 }; 1507 1508 sdmmc0-0 { 1509 sdmmc0m0_pwren: sdmmc0m0-pwren { 1510 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1511 }; 1512 1513 sdmmc0m0_pin: sdmmc0m0-pin { 1514 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1515 }; 1516 }; 1517 1518 sdmmc0-1 { 1519 sdmmc0m1_pwren: sdmmc0m1-pwren { 1520 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1521 }; 1522 1523 sdmmc0m1_pin: sdmmc0m1-pin { 1524 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1525 }; 1526 }; 1527 1528 sdmmc0 { 1529 sdmmc0_clk: sdmmc0-clk { 1530 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1531 }; 1532 1533 sdmmc0_cmd: sdmmc0-cmd { 1534 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1535 }; 1536 1537 sdmmc0_dectn: sdmmc0-dectn { 1538 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1539 }; 1540 1541 sdmmc0_wrprt: sdmmc0-wrprt { 1542 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1543 }; 1544 1545 sdmmc0_bus1: sdmmc0-bus1 { 1546 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1547 }; 1548 1549 sdmmc0_bus4: sdmmc0-bus4 { 1550 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1551 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1552 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1553 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1554 }; 1555 1556 sdmmc0_pins: sdmmc0-pins { 1557 rockchip,pins = 1558 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1559 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1560 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1561 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1562 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1563 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1564 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1565 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1566 }; 1567 }; 1568 1569 sdmmc0ext { 1570 sdmmc0ext_clk: sdmmc0ext-clk { 1571 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1572 }; 1573 1574 sdmmc0ext_cmd: sdmmc0ext-cmd { 1575 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1576 }; 1577 1578 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1579 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1580 }; 1581 1582 sdmmc0ext_dectn: sdmmc0ext-dectn { 1583 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1584 }; 1585 1586 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1587 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1588 }; 1589 1590 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1591 rockchip,pins = 1592 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1593 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1594 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1595 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1596 }; 1597 1598 sdmmc0ext_pins: sdmmc0ext-pins { 1599 rockchip,pins = 1600 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1601 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1602 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1603 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1604 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1605 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1606 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1607 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1608 }; 1609 }; 1610 1611 sdmmc1 { 1612 sdmmc1_clk: sdmmc1-clk { 1613 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1614 }; 1615 1616 sdmmc1_cmd: sdmmc1-cmd { 1617 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1618 }; 1619 1620 sdmmc1_pwren: sdmmc1-pwren { 1621 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1622 }; 1623 1624 sdmmc1_wrprt: sdmmc1-wrprt { 1625 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1626 }; 1627 1628 sdmmc1_dectn: sdmmc1-dectn { 1629 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1630 }; 1631 1632 sdmmc1_bus1: sdmmc1-bus1 { 1633 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1634 }; 1635 1636 sdmmc1_bus4: sdmmc1-bus4 { 1637 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1638 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1639 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1640 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1641 }; 1642 1643 sdmmc1_pins: sdmmc1-pins { 1644 rockchip,pins = 1645 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1646 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1647 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1648 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1649 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1650 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1651 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1652 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1653 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1654 }; 1655 }; 1656 1657 emmc { 1658 emmc_clk: emmc-clk { 1659 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1660 }; 1661 1662 emmc_cmd: emmc-cmd { 1663 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1664 }; 1665 1666 emmc_pwren: emmc-pwren { 1667 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1668 }; 1669 1670 emmc_rstnout: emmc-rstnout { 1671 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1672 }; 1673 1674 emmc_bus1: emmc-bus1 { 1675 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1676 }; 1677 1678 emmc_bus4: emmc-bus4 { 1679 rockchip,pins = 1680 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1681 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1682 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1683 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1684 }; 1685 1686 emmc_bus8: emmc-bus8 { 1687 rockchip,pins = 1688 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1689 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1690 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1691 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1692 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1693 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1694 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1695 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1696 }; 1697 }; 1698 1699 pwm0 { 1700 pwm0_pin: pwm0-pin { 1701 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1702 }; 1703 }; 1704 1705 pwm1 { 1706 pwm1_pin: pwm1-pin { 1707 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1708 }; 1709 }; 1710 1711 pwm2 { 1712 pwm2_pin: pwm2-pin { 1713 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1714 }; 1715 }; 1716 1717 pwmir { 1718 pwmir_pin: pwmir-pin { 1719 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1720 }; 1721 }; 1722 1723 gmac-1 { 1724 rgmiim1_pins: rgmiim1-pins { 1725 rockchip,pins = 1726 /* mac_txclk */ 1727 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1728 /* mac_rxclk */ 1729 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1730 /* mac_mdio */ 1731 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1732 /* mac_txen */ 1733 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1734 /* mac_clk */ 1735 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1736 /* mac_rxdv */ 1737 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1738 /* mac_mdc */ 1739 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1740 /* mac_rxd1 */ 1741 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1742 /* mac_rxd0 */ 1743 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1744 /* mac_txd1 */ 1745 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1746 /* mac_txd0 */ 1747 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1748 /* mac_rxd3 */ 1749 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1750 /* mac_rxd2 */ 1751 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1752 /* mac_txd3 */ 1753 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1754 /* mac_txd2 */ 1755 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1756 1757 /* mac_txclk */ 1758 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1759 /* mac_txen */ 1760 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1761 /* mac_clk */ 1762 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1763 /* mac_txd1 */ 1764 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1765 /* mac_txd0 */ 1766 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1767 /* mac_txd3 */ 1768 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1769 /* mac_txd2 */ 1770 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1771 }; 1772 1773 rmiim1_pins: rmiim1-pins { 1774 rockchip,pins = 1775 /* mac_mdio */ 1776 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1777 /* mac_txen */ 1778 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1779 /* mac_clk */ 1780 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1781 /* mac_rxer */ 1782 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1783 /* mac_rxdv */ 1784 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1785 /* mac_mdc */ 1786 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1787 /* mac_rxd1 */ 1788 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1789 /* mac_rxd0 */ 1790 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1791 /* mac_txd1 */ 1792 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1793 /* mac_txd0 */ 1794 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1795 1796 /* mac_mdio */ 1797 <0 RK_PB3 1 &pcfg_pull_none>, 1798 /* mac_txen */ 1799 <0 RK_PB4 1 &pcfg_pull_none>, 1800 /* mac_clk */ 1801 <0 RK_PD0 1 &pcfg_pull_none>, 1802 /* mac_mdc */ 1803 <0 RK_PC3 1 &pcfg_pull_none>, 1804 /* mac_txd1 */ 1805 <0 RK_PC0 1 &pcfg_pull_none>, 1806 /* mac_txd0 */ 1807 <0 RK_PC1 1 &pcfg_pull_none>; 1808 }; 1809 }; 1810 1811 gmac2phy { 1812 fephyled_speed10: fephyled-speed10 { 1813 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1814 }; 1815 1816 fephyled_duplex: fephyled-duplex { 1817 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1818 }; 1819 1820 fephyled_rxm1: fephyled-rxm1 { 1821 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1822 }; 1823 1824 fephyled_txm1: fephyled-txm1 { 1825 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1826 }; 1827 1828 fephyled_linkm1: fephyled-linkm1 { 1829 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1830 }; 1831 }; 1832 1833 tsadc_pin { 1834 tsadc_int: tsadc-int { 1835 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1836 }; 1837 tsadc_pin: tsadc-pin { 1838 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1839 }; 1840 }; 1841 1842 hdmi_pin { 1843 hdmi_cec: hdmi-cec { 1844 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1845 }; 1846 1847 hdmi_hpd: hdmi-hpd { 1848 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1849 }; 1850 }; 1851 1852 cif-0 { 1853 dvp_d2d9_m0:dvp-d2d9-m0 { 1854 rockchip,pins = 1855 /* cif_d0 */ 1856 <3 RK_PA4 2 &pcfg_pull_none>, 1857 /* cif_d1 */ 1858 <3 RK_PA5 2 &pcfg_pull_none>, 1859 /* cif_d2 */ 1860 <3 RK_PA6 2 &pcfg_pull_none>, 1861 /* cif_d3 */ 1862 <3 RK_PA7 2 &pcfg_pull_none>, 1863 /* cif_d4 */ 1864 <3 RK_PB0 2 &pcfg_pull_none>, 1865 /* cif_d5m0 */ 1866 <3 RK_PB1 2 &pcfg_pull_none>, 1867 /* cif_d6m0 */ 1868 <3 RK_PB2 2 &pcfg_pull_none>, 1869 /* cif_d7m0 */ 1870 <3 RK_PB3 2 &pcfg_pull_none>, 1871 /* cif_href */ 1872 <3 RK_PA1 2 &pcfg_pull_none>, 1873 /* cif_vsync */ 1874 <3 RK_PA0 2 &pcfg_pull_none>, 1875 /* cif_clkoutm0 */ 1876 <3 RK_PA3 2 &pcfg_pull_none>, 1877 /* cif_clkin */ 1878 <3 RK_PA2 2 &pcfg_pull_none>; 1879 }; 1880 }; 1881 1882 cif-1 { 1883 dvp_d2d9_m1:dvp-d2d9-m1 { 1884 rockchip,pins = 1885 /* cif_d0 */ 1886 <3 RK_PA4 2 &pcfg_pull_none>, 1887 /* cif_d1 */ 1888 <3 RK_PA5 2 &pcfg_pull_none>, 1889 /* cif_d2 */ 1890 <3 RK_PA6 2 &pcfg_pull_none>, 1891 /* cif_d3 */ 1892 <3 RK_PA7 2 &pcfg_pull_none>, 1893 /* cif_d4 */ 1894 <3 RK_PB0 2 &pcfg_pull_none>, 1895 /* cif_d5m1 */ 1896 <2 RK_PC0 4 &pcfg_pull_none>, 1897 /* cif_d6m1 */ 1898 <2 RK_PC1 4 &pcfg_pull_none>, 1899 /* cif_d7m1 */ 1900 <2 RK_PC2 4 &pcfg_pull_none>, 1901 /* cif_href */ 1902 <3 RK_PA1 2 &pcfg_pull_none>, 1903 /* cif_vsync */ 1904 <3 RK_PA0 2 &pcfg_pull_none>, 1905 /* cif_clkoutm1 */ 1906 <2 RK_PB7 4 &pcfg_pull_none>, 1907 /* cif_clkin */ 1908 <3 RK_PA2 2 &pcfg_pull_none>; 1909 }; 1910 }; 1911 }; 1912}; 1913