1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu-map { 44 cluster0 { 45 core0 { 46 cpu = <&cpu_l0>; 47 }; 48 core1 { 49 cpu = <&cpu_l1>; 50 }; 51 core2 { 52 cpu = <&cpu_l2>; 53 }; 54 core3 { 55 cpu = <&cpu_l3>; 56 }; 57 }; 58 59 cluster1 { 60 core0 { 61 cpu = <&cpu_b0>; 62 }; 63 core1 { 64 cpu = <&cpu_b1>; 65 }; 66 }; 67 }; 68 69 cpu_l0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 capacity-dmips-mhz = <485>; 75 clocks = <&cru ARMCLKL>; 76 #cooling-cells = <2>; /* min followed by max */ 77 dynamic-power-coefficient = <100>; 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 79 }; 80 81 cpu_l1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x0 0x1>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <485>; 87 clocks = <&cru ARMCLKL>; 88 #cooling-cells = <2>; /* min followed by max */ 89 dynamic-power-coefficient = <100>; 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 91 }; 92 93 cpu_l2: cpu@2 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x2>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <485>; 99 clocks = <&cru ARMCLKL>; 100 #cooling-cells = <2>; /* min followed by max */ 101 dynamic-power-coefficient = <100>; 102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 103 }; 104 105 cpu_l3: cpu@3 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x0 0x3>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <485>; 111 clocks = <&cru ARMCLKL>; 112 #cooling-cells = <2>; /* min followed by max */ 113 dynamic-power-coefficient = <100>; 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 115 }; 116 117 cpu_b0: cpu@100 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a72"; 120 reg = <0x0 0x100>; 121 enable-method = "psci"; 122 capacity-dmips-mhz = <1024>; 123 clocks = <&cru ARMCLKB>; 124 #cooling-cells = <2>; /* min followed by max */ 125 dynamic-power-coefficient = <436>; 126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 127 }; 128 129 cpu_b1: cpu@101 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a72"; 132 reg = <0x0 0x101>; 133 enable-method = "psci"; 134 capacity-dmips-mhz = <1024>; 135 clocks = <&cru ARMCLKB>; 136 #cooling-cells = <2>; /* min followed by max */ 137 dynamic-power-coefficient = <436>; 138 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 139 }; 140 141 idle-states { 142 entry-method = "psci"; 143 144 CPU_SLEEP: cpu-sleep { 145 compatible = "arm,idle-state"; 146 local-timer-stop; 147 arm,psci-suspend-param = <0x0010000>; 148 entry-latency-us = <120>; 149 exit-latency-us = <250>; 150 min-residency-us = <900>; 151 }; 152 153 CLUSTER_SLEEP: cluster-sleep { 154 compatible = "arm,idle-state"; 155 local-timer-stop; 156 arm,psci-suspend-param = <0x1010000>; 157 entry-latency-us = <400>; 158 exit-latency-us = <500>; 159 min-residency-us = <2000>; 160 }; 161 }; 162 }; 163 164 display-subsystem { 165 compatible = "rockchip,display-subsystem"; 166 ports = <&vopl_out>, <&vopb_out>; 167 }; 168 169 pmu_a53 { 170 compatible = "arm,cortex-a53-pmu"; 171 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 172 }; 173 174 pmu_a72 { 175 compatible = "arm,cortex-a72-pmu"; 176 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 177 }; 178 179 psci { 180 compatible = "arm,psci-1.0"; 181 method = "smc"; 182 }; 183 184 timer { 185 compatible = "arm,armv8-timer"; 186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 190 arm,no-tick-in-suspend; 191 }; 192 193 xin24m: xin24m { 194 compatible = "fixed-clock"; 195 clock-frequency = <24000000>; 196 clock-output-names = "xin24m"; 197 #clock-cells = <0>; 198 }; 199 200 pcie0: pcie@f8000000 { 201 compatible = "rockchip,rk3399-pcie"; 202 reg = <0x0 0xf8000000 0x0 0x2000000>, 203 <0x0 0xfd000000 0x0 0x1000000>; 204 reg-names = "axi-base", "apb-base"; 205 device_type = "pci"; 206 #address-cells = <3>; 207 #size-cells = <2>; 208 #interrupt-cells = <1>; 209 aspm-no-l0s; 210 bus-range = <0x0 0x1f>; 211 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 212 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 213 clock-names = "aclk", "aclk-perf", 214 "hclk", "pm"; 215 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 216 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 217 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 218 interrupt-names = "sys", "legacy", "client"; 219 interrupt-map-mask = <0 0 0 7>; 220 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 221 <0 0 0 2 &pcie0_intc 1>, 222 <0 0 0 3 &pcie0_intc 2>, 223 <0 0 0 4 &pcie0_intc 3>; 224 max-link-speed = <1>; 225 msi-map = <0x0 &its 0x0 0x1000>; 226 phys = <&pcie_phy 0>, <&pcie_phy 1>, 227 <&pcie_phy 2>, <&pcie_phy 3>; 228 phy-names = "pcie-phy-0", "pcie-phy-1", 229 "pcie-phy-2", "pcie-phy-3"; 230 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>, 231 <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 232 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 233 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 234 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 235 <&cru SRST_A_PCIE>; 236 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 237 "pm", "pclk", "aclk"; 238 status = "disabled"; 239 240 pcie0_intc: interrupt-controller { 241 interrupt-controller; 242 #address-cells = <0>; 243 #interrupt-cells = <1>; 244 }; 245 }; 246 247 gmac: ethernet@fe300000 { 248 compatible = "rockchip,rk3399-gmac"; 249 reg = <0x0 0xfe300000 0x0 0x10000>; 250 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 251 interrupt-names = "macirq"; 252 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 253 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 254 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 255 <&cru PCLK_GMAC>; 256 clock-names = "stmmaceth", "mac_clk_rx", 257 "mac_clk_tx", "clk_mac_ref", 258 "clk_mac_refout", "aclk_mac", 259 "pclk_mac"; 260 power-domains = <&power RK3399_PD_GMAC>; 261 resets = <&cru SRST_A_GMAC>; 262 reset-names = "stmmaceth"; 263 rockchip,grf = <&grf>; 264 snps,txpbl = <0x4>; 265 status = "disabled"; 266 }; 267 268 sdio0: mmc@fe310000 { 269 compatible = "rockchip,rk3399-dw-mshc", 270 "rockchip,rk3288-dw-mshc"; 271 reg = <0x0 0xfe310000 0x0 0x4000>; 272 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 273 max-frequency = <150000000>; 274 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 275 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 276 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 277 fifo-depth = <0x100>; 278 power-domains = <&power RK3399_PD_SDIOAUDIO>; 279 resets = <&cru SRST_SDIO0>; 280 reset-names = "reset"; 281 status = "disabled"; 282 }; 283 284 sdmmc: mmc@fe320000 { 285 compatible = "rockchip,rk3399-dw-mshc", 286 "rockchip,rk3288-dw-mshc"; 287 reg = <0x0 0xfe320000 0x0 0x4000>; 288 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 289 max-frequency = <150000000>; 290 assigned-clocks = <&cru HCLK_SD>; 291 assigned-clock-rates = <200000000>; 292 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 293 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 294 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 295 fifo-depth = <0x100>; 296 power-domains = <&power RK3399_PD_SD>; 297 resets = <&cru SRST_SDMMC>; 298 reset-names = "reset"; 299 status = "disabled"; 300 }; 301 302 sdhci: mmc@fe330000 { 303 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 304 reg = <0x0 0xfe330000 0x0 0x10000>; 305 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 306 arasan,soc-ctl-syscon = <&grf>; 307 assigned-clocks = <&cru SCLK_EMMC>; 308 assigned-clock-rates = <200000000>; 309 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 310 clock-names = "clk_xin", "clk_ahb"; 311 clock-output-names = "emmc_cardclock"; 312 #clock-cells = <0>; 313 phys = <&emmc_phy>; 314 phy-names = "phy_arasan"; 315 power-domains = <&power RK3399_PD_EMMC>; 316 disable-cqe-dcmd; 317 status = "disabled"; 318 }; 319 320 usb_host0_ehci: usb@fe380000 { 321 compatible = "generic-ehci"; 322 reg = <0x0 0xfe380000 0x0 0x20000>; 323 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 324 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 325 <&u2phy0>; 326 phys = <&u2phy0_host>; 327 phy-names = "usb"; 328 status = "disabled"; 329 }; 330 331 usb_host0_ohci: usb@fe3a0000 { 332 compatible = "generic-ohci"; 333 reg = <0x0 0xfe3a0000 0x0 0x20000>; 334 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 335 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 336 <&u2phy0>; 337 phys = <&u2phy0_host>; 338 phy-names = "usb"; 339 status = "disabled"; 340 }; 341 342 usb_host1_ehci: usb@fe3c0000 { 343 compatible = "generic-ehci"; 344 reg = <0x0 0xfe3c0000 0x0 0x20000>; 345 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 346 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 347 <&u2phy1>; 348 phys = <&u2phy1_host>; 349 phy-names = "usb"; 350 status = "disabled"; 351 }; 352 353 usb_host1_ohci: usb@fe3e0000 { 354 compatible = "generic-ohci"; 355 reg = <0x0 0xfe3e0000 0x0 0x20000>; 356 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 357 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 358 <&u2phy1>; 359 phys = <&u2phy1_host>; 360 phy-names = "usb"; 361 status = "disabled"; 362 }; 363 364 usbdrd3_0: usb@fe800000 { 365 compatible = "rockchip,rk3399-dwc3"; 366 #address-cells = <2>; 367 #size-cells = <2>; 368 ranges; 369 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 370 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 371 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 372 clock-names = "ref_clk", "suspend_clk", 373 "bus_clk", "aclk_usb3_rksoc_axi_perf", 374 "aclk_usb3", "grf_clk"; 375 resets = <&cru SRST_A_USB3_OTG0>; 376 reset-names = "usb3-otg"; 377 status = "disabled"; 378 379 usbdrd_dwc3_0: usb@fe800000 { 380 compatible = "snps,dwc3"; 381 reg = <0x0 0xfe800000 0x0 0x100000>; 382 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 383 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, 384 <&cru SCLK_USB3OTG0_SUSPEND>; 385 clock-names = "ref", "bus_early", "suspend"; 386 dr_mode = "otg"; 387 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 388 phy-names = "usb2-phy", "usb3-phy"; 389 phy_type = "utmi_wide"; 390 snps,dis_enblslpm_quirk; 391 snps,dis-u2-freeclk-exists-quirk; 392 snps,dis_u2_susphy_quirk; 393 snps,dis-del-phy-power-chg-quirk; 394 snps,dis-tx-ipgap-linecheck-quirk; 395 power-domains = <&power RK3399_PD_USB3>; 396 status = "disabled"; 397 }; 398 }; 399 400 usbdrd3_1: usb@fe900000 { 401 compatible = "rockchip,rk3399-dwc3"; 402 #address-cells = <2>; 403 #size-cells = <2>; 404 ranges; 405 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 406 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 407 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 408 clock-names = "ref_clk", "suspend_clk", 409 "bus_clk", "aclk_usb3_rksoc_axi_perf", 410 "aclk_usb3", "grf_clk"; 411 resets = <&cru SRST_A_USB3_OTG1>; 412 reset-names = "usb3-otg"; 413 status = "disabled"; 414 415 usbdrd_dwc3_1: usb@fe900000 { 416 compatible = "snps,dwc3"; 417 reg = <0x0 0xfe900000 0x0 0x100000>; 418 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 419 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, 420 <&cru SCLK_USB3OTG1_SUSPEND>; 421 clock-names = "ref", "bus_early", "suspend"; 422 dr_mode = "otg"; 423 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 424 phy-names = "usb2-phy", "usb3-phy"; 425 phy_type = "utmi_wide"; 426 snps,dis_enblslpm_quirk; 427 snps,dis-u2-freeclk-exists-quirk; 428 snps,dis_u2_susphy_quirk; 429 snps,dis-del-phy-power-chg-quirk; 430 snps,dis-tx-ipgap-linecheck-quirk; 431 power-domains = <&power RK3399_PD_USB3>; 432 status = "disabled"; 433 }; 434 }; 435 436 cdn_dp: dp@fec00000 { 437 compatible = "rockchip,rk3399-cdn-dp"; 438 reg = <0x0 0xfec00000 0x0 0x100000>; 439 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 440 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 441 assigned-clock-rates = <100000000>, <200000000>; 442 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 443 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 444 clock-names = "core-clk", "pclk", "spdif", "grf"; 445 phys = <&tcphy0_dp>, <&tcphy1_dp>; 446 power-domains = <&power RK3399_PD_HDCP>; 447 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 448 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 449 reset-names = "spdif", "dptx", "apb", "core"; 450 rockchip,grf = <&grf>; 451 #sound-dai-cells = <1>; 452 status = "disabled"; 453 454 ports { 455 dp_in: port { 456 #address-cells = <1>; 457 #size-cells = <0>; 458 459 dp_in_vopb: endpoint@0 { 460 reg = <0>; 461 remote-endpoint = <&vopb_out_dp>; 462 }; 463 464 dp_in_vopl: endpoint@1 { 465 reg = <1>; 466 remote-endpoint = <&vopl_out_dp>; 467 }; 468 }; 469 }; 470 }; 471 472 gic: interrupt-controller@fee00000 { 473 compatible = "arm,gic-v3"; 474 #interrupt-cells = <4>; 475 #address-cells = <2>; 476 #size-cells = <2>; 477 ranges; 478 interrupt-controller; 479 480 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 481 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 482 <0x0 0xfff00000 0 0x10000>, /* GICC */ 483 <0x0 0xfff10000 0 0x10000>, /* GICH */ 484 <0x0 0xfff20000 0 0x10000>; /* GICV */ 485 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 486 its: interrupt-controller@fee20000 { 487 compatible = "arm,gic-v3-its"; 488 msi-controller; 489 #msi-cells = <1>; 490 reg = <0x0 0xfee20000 0x0 0x20000>; 491 }; 492 493 ppi-partitions { 494 ppi_cluster0: interrupt-partition-0 { 495 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 496 }; 497 498 ppi_cluster1: interrupt-partition-1 { 499 affinity = <&cpu_b0 &cpu_b1>; 500 }; 501 }; 502 }; 503 504 saradc: saradc@ff100000 { 505 compatible = "rockchip,rk3399-saradc"; 506 reg = <0x0 0xff100000 0x0 0x100>; 507 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 508 #io-channel-cells = <1>; 509 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 510 clock-names = "saradc", "apb_pclk"; 511 resets = <&cru SRST_P_SARADC>; 512 reset-names = "saradc-apb"; 513 status = "disabled"; 514 }; 515 516 i2c1: i2c@ff110000 { 517 compatible = "rockchip,rk3399-i2c"; 518 reg = <0x0 0xff110000 0x0 0x1000>; 519 assigned-clocks = <&cru SCLK_I2C1>; 520 assigned-clock-rates = <200000000>; 521 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 522 clock-names = "i2c", "pclk"; 523 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 524 pinctrl-names = "default"; 525 pinctrl-0 = <&i2c1_xfer>; 526 #address-cells = <1>; 527 #size-cells = <0>; 528 status = "disabled"; 529 }; 530 531 i2c2: i2c@ff120000 { 532 compatible = "rockchip,rk3399-i2c"; 533 reg = <0x0 0xff120000 0x0 0x1000>; 534 assigned-clocks = <&cru SCLK_I2C2>; 535 assigned-clock-rates = <200000000>; 536 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 537 clock-names = "i2c", "pclk"; 538 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 539 pinctrl-names = "default"; 540 pinctrl-0 = <&i2c2_xfer>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 status = "disabled"; 544 }; 545 546 i2c3: i2c@ff130000 { 547 compatible = "rockchip,rk3399-i2c"; 548 reg = <0x0 0xff130000 0x0 0x1000>; 549 assigned-clocks = <&cru SCLK_I2C3>; 550 assigned-clock-rates = <200000000>; 551 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 552 clock-names = "i2c", "pclk"; 553 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&i2c3_xfer>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 status = "disabled"; 559 }; 560 561 i2c5: i2c@ff140000 { 562 compatible = "rockchip,rk3399-i2c"; 563 reg = <0x0 0xff140000 0x0 0x1000>; 564 assigned-clocks = <&cru SCLK_I2C5>; 565 assigned-clock-rates = <200000000>; 566 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 567 clock-names = "i2c", "pclk"; 568 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&i2c5_xfer>; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 status = "disabled"; 574 }; 575 576 i2c6: i2c@ff150000 { 577 compatible = "rockchip,rk3399-i2c"; 578 reg = <0x0 0xff150000 0x0 0x1000>; 579 assigned-clocks = <&cru SCLK_I2C6>; 580 assigned-clock-rates = <200000000>; 581 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 582 clock-names = "i2c", "pclk"; 583 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&i2c6_xfer>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 status = "disabled"; 589 }; 590 591 i2c7: i2c@ff160000 { 592 compatible = "rockchip,rk3399-i2c"; 593 reg = <0x0 0xff160000 0x0 0x1000>; 594 assigned-clocks = <&cru SCLK_I2C7>; 595 assigned-clock-rates = <200000000>; 596 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 597 clock-names = "i2c", "pclk"; 598 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 599 pinctrl-names = "default"; 600 pinctrl-0 = <&i2c7_xfer>; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 status = "disabled"; 604 }; 605 606 uart0: serial@ff180000 { 607 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 608 reg = <0x0 0xff180000 0x0 0x100>; 609 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 610 clock-names = "baudclk", "apb_pclk"; 611 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 612 reg-shift = <2>; 613 reg-io-width = <4>; 614 pinctrl-names = "default"; 615 pinctrl-0 = <&uart0_xfer>; 616 status = "disabled"; 617 }; 618 619 uart1: serial@ff190000 { 620 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 621 reg = <0x0 0xff190000 0x0 0x100>; 622 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 623 clock-names = "baudclk", "apb_pclk"; 624 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 625 reg-shift = <2>; 626 reg-io-width = <4>; 627 pinctrl-names = "default"; 628 pinctrl-0 = <&uart1_xfer>; 629 status = "disabled"; 630 }; 631 632 uart2: serial@ff1a0000 { 633 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 634 reg = <0x0 0xff1a0000 0x0 0x100>; 635 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 636 clock-names = "baudclk", "apb_pclk"; 637 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 638 reg-shift = <2>; 639 reg-io-width = <4>; 640 pinctrl-names = "default"; 641 pinctrl-0 = <&uart2c_xfer>; 642 status = "disabled"; 643 }; 644 645 uart3: serial@ff1b0000 { 646 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 647 reg = <0x0 0xff1b0000 0x0 0x100>; 648 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 649 clock-names = "baudclk", "apb_pclk"; 650 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 651 reg-shift = <2>; 652 reg-io-width = <4>; 653 pinctrl-names = "default"; 654 pinctrl-0 = <&uart3_xfer>; 655 status = "disabled"; 656 }; 657 658 spi0: spi@ff1c0000 { 659 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 660 reg = <0x0 0xff1c0000 0x0 0x1000>; 661 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 662 clock-names = "spiclk", "apb_pclk"; 663 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 664 dmas = <&dmac_peri 10>, <&dmac_peri 11>; 665 dma-names = "tx", "rx"; 666 pinctrl-names = "default"; 667 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 status = "disabled"; 671 }; 672 673 spi1: spi@ff1d0000 { 674 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 675 reg = <0x0 0xff1d0000 0x0 0x1000>; 676 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 677 clock-names = "spiclk", "apb_pclk"; 678 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 679 dmas = <&dmac_peri 12>, <&dmac_peri 13>; 680 dma-names = "tx", "rx"; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 683 #address-cells = <1>; 684 #size-cells = <0>; 685 status = "disabled"; 686 }; 687 688 spi2: spi@ff1e0000 { 689 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 690 reg = <0x0 0xff1e0000 0x0 0x1000>; 691 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 692 clock-names = "spiclk", "apb_pclk"; 693 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 694 dmas = <&dmac_peri 14>, <&dmac_peri 15>; 695 dma-names = "tx", "rx"; 696 pinctrl-names = "default"; 697 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 status = "disabled"; 701 }; 702 703 spi4: spi@ff1f0000 { 704 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 705 reg = <0x0 0xff1f0000 0x0 0x1000>; 706 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 707 clock-names = "spiclk", "apb_pclk"; 708 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 709 dmas = <&dmac_peri 18>, <&dmac_peri 19>; 710 dma-names = "tx", "rx"; 711 pinctrl-names = "default"; 712 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 status = "disabled"; 716 }; 717 718 spi5: spi@ff200000 { 719 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 720 reg = <0x0 0xff200000 0x0 0x1000>; 721 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 722 clock-names = "spiclk", "apb_pclk"; 723 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 724 dmas = <&dmac_bus 8>, <&dmac_bus 9>; 725 dma-names = "tx", "rx"; 726 pinctrl-names = "default"; 727 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 728 power-domains = <&power RK3399_PD_SDIOAUDIO>; 729 #address-cells = <1>; 730 #size-cells = <0>; 731 status = "disabled"; 732 }; 733 734 thermal_zones: thermal-zones { 735 cpu_thermal: cpu-thermal { 736 polling-delay-passive = <100>; 737 polling-delay = <1000>; 738 739 thermal-sensors = <&tsadc 0>; 740 741 trips { 742 cpu_alert0: cpu_alert0 { 743 temperature = <70000>; 744 hysteresis = <2000>; 745 type = "passive"; 746 }; 747 cpu_alert1: cpu_alert1 { 748 temperature = <75000>; 749 hysteresis = <2000>; 750 type = "passive"; 751 }; 752 cpu_crit: cpu_crit { 753 temperature = <95000>; 754 hysteresis = <2000>; 755 type = "critical"; 756 }; 757 }; 758 759 cooling-maps { 760 map0 { 761 trip = <&cpu_alert0>; 762 cooling-device = 763 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 764 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 765 }; 766 map1 { 767 trip = <&cpu_alert1>; 768 cooling-device = 769 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 770 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 771 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 772 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 773 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 774 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 775 }; 776 }; 777 }; 778 779 gpu_thermal: gpu-thermal { 780 polling-delay-passive = <100>; 781 polling-delay = <1000>; 782 783 thermal-sensors = <&tsadc 1>; 784 785 trips { 786 gpu_alert0: gpu_alert0 { 787 temperature = <75000>; 788 hysteresis = <2000>; 789 type = "passive"; 790 }; 791 gpu_crit: gpu_crit { 792 temperature = <95000>; 793 hysteresis = <2000>; 794 type = "critical"; 795 }; 796 }; 797 798 cooling-maps { 799 map0 { 800 trip = <&gpu_alert0>; 801 cooling-device = 802 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 803 }; 804 }; 805 }; 806 }; 807 808 tsadc: tsadc@ff260000 { 809 compatible = "rockchip,rk3399-tsadc"; 810 reg = <0x0 0xff260000 0x0 0x100>; 811 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 812 assigned-clocks = <&cru SCLK_TSADC>; 813 assigned-clock-rates = <750000>; 814 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 815 clock-names = "tsadc", "apb_pclk"; 816 resets = <&cru SRST_TSADC>; 817 reset-names = "tsadc-apb"; 818 rockchip,grf = <&grf>; 819 rockchip,hw-tshut-temp = <95000>; 820 pinctrl-names = "init", "default", "sleep"; 821 pinctrl-0 = <&otp_pin>; 822 pinctrl-1 = <&otp_out>; 823 pinctrl-2 = <&otp_pin>; 824 #thermal-sensor-cells = <1>; 825 status = "disabled"; 826 }; 827 828 qos_emmc: qos@ffa58000 { 829 compatible = "rockchip,rk3399-qos", "syscon"; 830 reg = <0x0 0xffa58000 0x0 0x20>; 831 }; 832 833 qos_gmac: qos@ffa5c000 { 834 compatible = "rockchip,rk3399-qos", "syscon"; 835 reg = <0x0 0xffa5c000 0x0 0x20>; 836 }; 837 838 qos_pcie: qos@ffa60080 { 839 compatible = "rockchip,rk3399-qos", "syscon"; 840 reg = <0x0 0xffa60080 0x0 0x20>; 841 }; 842 843 qos_usb_host0: qos@ffa60100 { 844 compatible = "rockchip,rk3399-qos", "syscon"; 845 reg = <0x0 0xffa60100 0x0 0x20>; 846 }; 847 848 qos_usb_host1: qos@ffa60180 { 849 compatible = "rockchip,rk3399-qos", "syscon"; 850 reg = <0x0 0xffa60180 0x0 0x20>; 851 }; 852 853 qos_usb_otg0: qos@ffa70000 { 854 compatible = "rockchip,rk3399-qos", "syscon"; 855 reg = <0x0 0xffa70000 0x0 0x20>; 856 }; 857 858 qos_usb_otg1: qos@ffa70080 { 859 compatible = "rockchip,rk3399-qos", "syscon"; 860 reg = <0x0 0xffa70080 0x0 0x20>; 861 }; 862 863 qos_sd: qos@ffa74000 { 864 compatible = "rockchip,rk3399-qos", "syscon"; 865 reg = <0x0 0xffa74000 0x0 0x20>; 866 }; 867 868 qos_sdioaudio: qos@ffa76000 { 869 compatible = "rockchip,rk3399-qos", "syscon"; 870 reg = <0x0 0xffa76000 0x0 0x20>; 871 }; 872 873 qos_hdcp: qos@ffa90000 { 874 compatible = "rockchip,rk3399-qos", "syscon"; 875 reg = <0x0 0xffa90000 0x0 0x20>; 876 }; 877 878 qos_iep: qos@ffa98000 { 879 compatible = "rockchip,rk3399-qos", "syscon"; 880 reg = <0x0 0xffa98000 0x0 0x20>; 881 }; 882 883 qos_isp0_m0: qos@ffaa0000 { 884 compatible = "rockchip,rk3399-qos", "syscon"; 885 reg = <0x0 0xffaa0000 0x0 0x20>; 886 }; 887 888 qos_isp0_m1: qos@ffaa0080 { 889 compatible = "rockchip,rk3399-qos", "syscon"; 890 reg = <0x0 0xffaa0080 0x0 0x20>; 891 }; 892 893 qos_isp1_m0: qos@ffaa8000 { 894 compatible = "rockchip,rk3399-qos", "syscon"; 895 reg = <0x0 0xffaa8000 0x0 0x20>; 896 }; 897 898 qos_isp1_m1: qos@ffaa8080 { 899 compatible = "rockchip,rk3399-qos", "syscon"; 900 reg = <0x0 0xffaa8080 0x0 0x20>; 901 }; 902 903 qos_rga_r: qos@ffab0000 { 904 compatible = "rockchip,rk3399-qos", "syscon"; 905 reg = <0x0 0xffab0000 0x0 0x20>; 906 }; 907 908 qos_rga_w: qos@ffab0080 { 909 compatible = "rockchip,rk3399-qos", "syscon"; 910 reg = <0x0 0xffab0080 0x0 0x20>; 911 }; 912 913 qos_video_m0: qos@ffab8000 { 914 compatible = "rockchip,rk3399-qos", "syscon"; 915 reg = <0x0 0xffab8000 0x0 0x20>; 916 }; 917 918 qos_video_m1_r: qos@ffac0000 { 919 compatible = "rockchip,rk3399-qos", "syscon"; 920 reg = <0x0 0xffac0000 0x0 0x20>; 921 }; 922 923 qos_video_m1_w: qos@ffac0080 { 924 compatible = "rockchip,rk3399-qos", "syscon"; 925 reg = <0x0 0xffac0080 0x0 0x20>; 926 }; 927 928 qos_vop_big_r: qos@ffac8000 { 929 compatible = "rockchip,rk3399-qos", "syscon"; 930 reg = <0x0 0xffac8000 0x0 0x20>; 931 }; 932 933 qos_vop_big_w: qos@ffac8080 { 934 compatible = "rockchip,rk3399-qos", "syscon"; 935 reg = <0x0 0xffac8080 0x0 0x20>; 936 }; 937 938 qos_vop_little: qos@ffad0000 { 939 compatible = "rockchip,rk3399-qos", "syscon"; 940 reg = <0x0 0xffad0000 0x0 0x20>; 941 }; 942 943 qos_perihp: qos@ffad8080 { 944 compatible = "rockchip,rk3399-qos", "syscon"; 945 reg = <0x0 0xffad8080 0x0 0x20>; 946 }; 947 948 qos_gpu: qos@ffae0000 { 949 compatible = "rockchip,rk3399-qos", "syscon"; 950 reg = <0x0 0xffae0000 0x0 0x20>; 951 }; 952 953 pmu: power-management@ff310000 { 954 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 955 reg = <0x0 0xff310000 0x0 0x1000>; 956 957 /* 958 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 959 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 960 * Some of the power domains are grouped together for every 961 * voltage domain. 962 * The detail contents as below. 963 */ 964 power: power-controller { 965 compatible = "rockchip,rk3399-power-controller"; 966 #power-domain-cells = <1>; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 970 /* These power domains are grouped by VD_CENTER */ 971 power-domain@RK3399_PD_IEP { 972 reg = <RK3399_PD_IEP>; 973 clocks = <&cru ACLK_IEP>, 974 <&cru HCLK_IEP>; 975 pm_qos = <&qos_iep>; 976 #power-domain-cells = <0>; 977 }; 978 power-domain@RK3399_PD_RGA { 979 reg = <RK3399_PD_RGA>; 980 clocks = <&cru ACLK_RGA>, 981 <&cru HCLK_RGA>; 982 pm_qos = <&qos_rga_r>, 983 <&qos_rga_w>; 984 #power-domain-cells = <0>; 985 }; 986 power-domain@RK3399_PD_VCODEC { 987 reg = <RK3399_PD_VCODEC>; 988 clocks = <&cru ACLK_VCODEC>, 989 <&cru HCLK_VCODEC>; 990 pm_qos = <&qos_video_m0>; 991 #power-domain-cells = <0>; 992 }; 993 power-domain@RK3399_PD_VDU { 994 reg = <RK3399_PD_VDU>; 995 clocks = <&cru ACLK_VDU>, 996 <&cru HCLK_VDU>, 997 <&cru SCLK_VDU_CA>, 998 <&cru SCLK_VDU_CORE>; 999 pm_qos = <&qos_video_m1_r>, 1000 <&qos_video_m1_w>; 1001 #power-domain-cells = <0>; 1002 }; 1003 1004 /* These power domains are grouped by VD_GPU */ 1005 power-domain@RK3399_PD_GPU { 1006 reg = <RK3399_PD_GPU>; 1007 clocks = <&cru ACLK_GPU>; 1008 pm_qos = <&qos_gpu>; 1009 #power-domain-cells = <0>; 1010 }; 1011 1012 /* These power domains are grouped by VD_LOGIC */ 1013 power-domain@RK3399_PD_EDP { 1014 reg = <RK3399_PD_EDP>; 1015 clocks = <&cru PCLK_EDP_CTRL>; 1016 #power-domain-cells = <0>; 1017 }; 1018 power-domain@RK3399_PD_EMMC { 1019 reg = <RK3399_PD_EMMC>; 1020 clocks = <&cru ACLK_EMMC>; 1021 pm_qos = <&qos_emmc>; 1022 #power-domain-cells = <0>; 1023 }; 1024 power-domain@RK3399_PD_GMAC { 1025 reg = <RK3399_PD_GMAC>; 1026 clocks = <&cru ACLK_GMAC>, 1027 <&cru PCLK_GMAC>; 1028 pm_qos = <&qos_gmac>; 1029 #power-domain-cells = <0>; 1030 }; 1031 power-domain@RK3399_PD_SD { 1032 reg = <RK3399_PD_SD>; 1033 clocks = <&cru HCLK_SDMMC>, 1034 <&cru SCLK_SDMMC>; 1035 pm_qos = <&qos_sd>; 1036 #power-domain-cells = <0>; 1037 }; 1038 power-domain@RK3399_PD_SDIOAUDIO { 1039 reg = <RK3399_PD_SDIOAUDIO>; 1040 clocks = <&cru HCLK_SDIO>; 1041 pm_qos = <&qos_sdioaudio>; 1042 #power-domain-cells = <0>; 1043 }; 1044 power-domain@RK3399_PD_TCPD0 { 1045 reg = <RK3399_PD_TCPD0>; 1046 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1047 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1048 #power-domain-cells = <0>; 1049 }; 1050 power-domain@RK3399_PD_TCPD1 { 1051 reg = <RK3399_PD_TCPD1>; 1052 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1053 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1054 #power-domain-cells = <0>; 1055 }; 1056 power-domain@RK3399_PD_USB3 { 1057 reg = <RK3399_PD_USB3>; 1058 clocks = <&cru ACLK_USB3>; 1059 pm_qos = <&qos_usb_otg0>, 1060 <&qos_usb_otg1>; 1061 #power-domain-cells = <0>; 1062 }; 1063 power-domain@RK3399_PD_VIO { 1064 reg = <RK3399_PD_VIO>; 1065 #power-domain-cells = <1>; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 1069 power-domain@RK3399_PD_HDCP { 1070 reg = <RK3399_PD_HDCP>; 1071 clocks = <&cru ACLK_HDCP>, 1072 <&cru HCLK_HDCP>, 1073 <&cru PCLK_HDCP>; 1074 pm_qos = <&qos_hdcp>; 1075 #power-domain-cells = <0>; 1076 }; 1077 power-domain@RK3399_PD_ISP0 { 1078 reg = <RK3399_PD_ISP0>; 1079 clocks = <&cru ACLK_ISP0>, 1080 <&cru HCLK_ISP0>; 1081 pm_qos = <&qos_isp0_m0>, 1082 <&qos_isp0_m1>; 1083 #power-domain-cells = <0>; 1084 }; 1085 power-domain@RK3399_PD_ISP1 { 1086 reg = <RK3399_PD_ISP1>; 1087 clocks = <&cru ACLK_ISP1>, 1088 <&cru HCLK_ISP1>; 1089 pm_qos = <&qos_isp1_m0>, 1090 <&qos_isp1_m1>; 1091 #power-domain-cells = <0>; 1092 }; 1093 power-domain@RK3399_PD_VO { 1094 reg = <RK3399_PD_VO>; 1095 #power-domain-cells = <1>; 1096 #address-cells = <1>; 1097 #size-cells = <0>; 1098 1099 power-domain@RK3399_PD_VOPB { 1100 reg = <RK3399_PD_VOPB>; 1101 clocks = <&cru ACLK_VOP0>, 1102 <&cru HCLK_VOP0>; 1103 pm_qos = <&qos_vop_big_r>, 1104 <&qos_vop_big_w>; 1105 #power-domain-cells = <0>; 1106 }; 1107 power-domain@RK3399_PD_VOPL { 1108 reg = <RK3399_PD_VOPL>; 1109 clocks = <&cru ACLK_VOP1>, 1110 <&cru HCLK_VOP1>; 1111 pm_qos = <&qos_vop_little>; 1112 #power-domain-cells = <0>; 1113 }; 1114 }; 1115 }; 1116 }; 1117 }; 1118 1119 pmugrf: syscon@ff320000 { 1120 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1121 reg = <0x0 0xff320000 0x0 0x1000>; 1122 1123 pmu_io_domains: io-domains { 1124 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1125 status = "disabled"; 1126 }; 1127 }; 1128 1129 spi3: spi@ff350000 { 1130 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1131 reg = <0x0 0xff350000 0x0 0x1000>; 1132 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1133 clock-names = "spiclk", "apb_pclk"; 1134 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1135 pinctrl-names = "default"; 1136 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 status = "disabled"; 1140 }; 1141 1142 uart4: serial@ff370000 { 1143 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1144 reg = <0x0 0xff370000 0x0 0x100>; 1145 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1146 clock-names = "baudclk", "apb_pclk"; 1147 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1148 reg-shift = <2>; 1149 reg-io-width = <4>; 1150 pinctrl-names = "default"; 1151 pinctrl-0 = <&uart4_xfer>; 1152 status = "disabled"; 1153 }; 1154 1155 i2c0: i2c@ff3c0000 { 1156 compatible = "rockchip,rk3399-i2c"; 1157 reg = <0x0 0xff3c0000 0x0 0x1000>; 1158 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1159 assigned-clock-rates = <200000000>; 1160 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1161 clock-names = "i2c", "pclk"; 1162 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&i2c0_xfer>; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 status = "disabled"; 1168 }; 1169 1170 i2c4: i2c@ff3d0000 { 1171 compatible = "rockchip,rk3399-i2c"; 1172 reg = <0x0 0xff3d0000 0x0 0x1000>; 1173 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1174 assigned-clock-rates = <200000000>; 1175 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1176 clock-names = "i2c", "pclk"; 1177 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1178 pinctrl-names = "default"; 1179 pinctrl-0 = <&i2c4_xfer>; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 status = "disabled"; 1183 }; 1184 1185 i2c8: i2c@ff3e0000 { 1186 compatible = "rockchip,rk3399-i2c"; 1187 reg = <0x0 0xff3e0000 0x0 0x1000>; 1188 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1189 assigned-clock-rates = <200000000>; 1190 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1191 clock-names = "i2c", "pclk"; 1192 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&i2c8_xfer>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 status = "disabled"; 1198 }; 1199 1200 pwm0: pwm@ff420000 { 1201 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1202 reg = <0x0 0xff420000 0x0 0x10>; 1203 #pwm-cells = <3>; 1204 pinctrl-names = "default"; 1205 pinctrl-0 = <&pwm0_pin>; 1206 clocks = <&pmucru PCLK_RKPWM_PMU>; 1207 status = "disabled"; 1208 }; 1209 1210 pwm1: pwm@ff420010 { 1211 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1212 reg = <0x0 0xff420010 0x0 0x10>; 1213 #pwm-cells = <3>; 1214 pinctrl-names = "default"; 1215 pinctrl-0 = <&pwm1_pin>; 1216 clocks = <&pmucru PCLK_RKPWM_PMU>; 1217 status = "disabled"; 1218 }; 1219 1220 pwm2: pwm@ff420020 { 1221 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1222 reg = <0x0 0xff420020 0x0 0x10>; 1223 #pwm-cells = <3>; 1224 pinctrl-names = "default"; 1225 pinctrl-0 = <&pwm2_pin>; 1226 clocks = <&pmucru PCLK_RKPWM_PMU>; 1227 status = "disabled"; 1228 }; 1229 1230 pwm3: pwm@ff420030 { 1231 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1232 reg = <0x0 0xff420030 0x0 0x10>; 1233 #pwm-cells = <3>; 1234 pinctrl-names = "default"; 1235 pinctrl-0 = <&pwm3a_pin>; 1236 clocks = <&pmucru PCLK_RKPWM_PMU>; 1237 status = "disabled"; 1238 }; 1239 1240 vpu: video-codec@ff650000 { 1241 compatible = "rockchip,rk3399-vpu"; 1242 reg = <0x0 0xff650000 0x0 0x800>; 1243 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 1244 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1245 interrupt-names = "vepu", "vdpu"; 1246 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1247 clock-names = "aclk", "hclk"; 1248 iommus = <&vpu_mmu>; 1249 power-domains = <&power RK3399_PD_VCODEC>; 1250 }; 1251 1252 vpu_mmu: iommu@ff650800 { 1253 compatible = "rockchip,iommu"; 1254 reg = <0x0 0xff650800 0x0 0x40>; 1255 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1256 interrupt-names = "vpu_mmu"; 1257 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1258 clock-names = "aclk", "iface"; 1259 #iommu-cells = <0>; 1260 power-domains = <&power RK3399_PD_VCODEC>; 1261 }; 1262 1263 vdec: video-codec@ff660000 { 1264 compatible = "rockchip,rk3399-vdec"; 1265 reg = <0x0 0xff660000 0x0 0x480>; 1266 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1267 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, 1268 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; 1269 clock-names = "axi", "ahb", "cabac", "core"; 1270 iommus = <&vdec_mmu>; 1271 power-domains = <&power RK3399_PD_VDU>; 1272 }; 1273 1274 vdec_mmu: iommu@ff660480 { 1275 compatible = "rockchip,iommu"; 1276 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1277 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1278 interrupt-names = "vdec_mmu"; 1279 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1280 clock-names = "aclk", "iface"; 1281 power-domains = <&power RK3399_PD_VDU>; 1282 #iommu-cells = <0>; 1283 }; 1284 1285 iep_mmu: iommu@ff670800 { 1286 compatible = "rockchip,iommu"; 1287 reg = <0x0 0xff670800 0x0 0x40>; 1288 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1289 interrupt-names = "iep_mmu"; 1290 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1291 clock-names = "aclk", "iface"; 1292 #iommu-cells = <0>; 1293 status = "disabled"; 1294 }; 1295 1296 rga: rga@ff680000 { 1297 compatible = "rockchip,rk3399-rga"; 1298 reg = <0x0 0xff680000 0x0 0x10000>; 1299 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1300 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1301 clock-names = "aclk", "hclk", "sclk"; 1302 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1303 reset-names = "core", "axi", "ahb"; 1304 power-domains = <&power RK3399_PD_RGA>; 1305 }; 1306 1307 efuse0: efuse@ff690000 { 1308 compatible = "rockchip,rk3399-efuse"; 1309 reg = <0x0 0xff690000 0x0 0x80>; 1310 #address-cells = <1>; 1311 #size-cells = <1>; 1312 clocks = <&cru PCLK_EFUSE1024NS>; 1313 clock-names = "pclk_efuse"; 1314 1315 /* Data cells */ 1316 cpu_id: cpu-id@7 { 1317 reg = <0x07 0x10>; 1318 }; 1319 cpub_leakage: cpu-leakage@17 { 1320 reg = <0x17 0x1>; 1321 }; 1322 gpu_leakage: gpu-leakage@18 { 1323 reg = <0x18 0x1>; 1324 }; 1325 center_leakage: center-leakage@19 { 1326 reg = <0x19 0x1>; 1327 }; 1328 cpul_leakage: cpu-leakage@1a { 1329 reg = <0x1a 0x1>; 1330 }; 1331 logic_leakage: logic-leakage@1b { 1332 reg = <0x1b 0x1>; 1333 }; 1334 wafer_info: wafer-info@1c { 1335 reg = <0x1c 0x1>; 1336 }; 1337 }; 1338 1339 dmac_bus: dma-controller@ff6d0000 { 1340 compatible = "arm,pl330", "arm,primecell"; 1341 reg = <0x0 0xff6d0000 0x0 0x4000>; 1342 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 1343 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 1344 #dma-cells = <1>; 1345 arm,pl330-periph-burst; 1346 clocks = <&cru ACLK_DMAC0_PERILP>; 1347 clock-names = "apb_pclk"; 1348 }; 1349 1350 dmac_peri: dma-controller@ff6e0000 { 1351 compatible = "arm,pl330", "arm,primecell"; 1352 reg = <0x0 0xff6e0000 0x0 0x4000>; 1353 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 1354 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 1355 #dma-cells = <1>; 1356 arm,pl330-periph-burst; 1357 clocks = <&cru ACLK_DMAC1_PERILP>; 1358 clock-names = "apb_pclk"; 1359 }; 1360 1361 pmucru: pmu-clock-controller@ff750000 { 1362 compatible = "rockchip,rk3399-pmucru"; 1363 reg = <0x0 0xff750000 0x0 0x1000>; 1364 rockchip,grf = <&pmugrf>; 1365 #clock-cells = <1>; 1366 #reset-cells = <1>; 1367 assigned-clocks = <&pmucru PLL_PPLL>; 1368 assigned-clock-rates = <676000000>; 1369 }; 1370 1371 cru: clock-controller@ff760000 { 1372 compatible = "rockchip,rk3399-cru"; 1373 reg = <0x0 0xff760000 0x0 0x1000>; 1374 rockchip,grf = <&grf>; 1375 #clock-cells = <1>; 1376 #reset-cells = <1>; 1377 assigned-clocks = 1378 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1379 <&cru PLL_NPLL>, 1380 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1381 <&cru PCLK_PERIHP>, 1382 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1383 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1384 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1385 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1386 <&cru ACLK_GIC_PRE>, 1387 <&cru PCLK_DDR>; 1388 assigned-clock-rates = 1389 <594000000>, <800000000>, 1390 <1000000000>, 1391 <150000000>, <75000000>, 1392 <37500000>, 1393 <100000000>, <100000000>, 1394 <50000000>, <600000000>, 1395 <100000000>, <50000000>, 1396 <400000000>, <400000000>, 1397 <200000000>, 1398 <200000000>; 1399 }; 1400 1401 grf: syscon@ff770000 { 1402 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1403 reg = <0x0 0xff770000 0x0 0x10000>; 1404 #address-cells = <1>; 1405 #size-cells = <1>; 1406 1407 io_domains: io-domains { 1408 compatible = "rockchip,rk3399-io-voltage-domain"; 1409 status = "disabled"; 1410 }; 1411 1412 mipi_dphy_rx0: mipi-dphy-rx0 { 1413 compatible = "rockchip,rk3399-mipi-dphy-rx0"; 1414 clocks = <&cru SCLK_MIPIDPHY_REF>, 1415 <&cru SCLK_DPHY_RX0_CFG>, 1416 <&cru PCLK_VIO_GRF>; 1417 clock-names = "dphy-ref", "dphy-cfg", "grf"; 1418 power-domains = <&power RK3399_PD_VIO>; 1419 #phy-cells = <0>; 1420 status = "disabled"; 1421 }; 1422 1423 u2phy0: usb2phy@e450 { 1424 compatible = "rockchip,rk3399-usb2phy"; 1425 reg = <0xe450 0x10>; 1426 clocks = <&cru SCLK_USB2PHY0_REF>; 1427 clock-names = "phyclk"; 1428 #clock-cells = <0>; 1429 clock-output-names = "clk_usbphy0_480m"; 1430 status = "disabled"; 1431 1432 u2phy0_host: host-port { 1433 #phy-cells = <0>; 1434 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1435 interrupt-names = "linestate"; 1436 status = "disabled"; 1437 }; 1438 1439 u2phy0_otg: otg-port { 1440 #phy-cells = <0>; 1441 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1442 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1443 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1444 interrupt-names = "otg-bvalid", "otg-id", 1445 "linestate"; 1446 status = "disabled"; 1447 }; 1448 }; 1449 1450 u2phy1: usb2phy@e460 { 1451 compatible = "rockchip,rk3399-usb2phy"; 1452 reg = <0xe460 0x10>; 1453 clocks = <&cru SCLK_USB2PHY1_REF>; 1454 clock-names = "phyclk"; 1455 #clock-cells = <0>; 1456 clock-output-names = "clk_usbphy1_480m"; 1457 status = "disabled"; 1458 1459 u2phy1_host: host-port { 1460 #phy-cells = <0>; 1461 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1462 interrupt-names = "linestate"; 1463 status = "disabled"; 1464 }; 1465 1466 u2phy1_otg: otg-port { 1467 #phy-cells = <0>; 1468 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1469 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1470 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1471 interrupt-names = "otg-bvalid", "otg-id", 1472 "linestate"; 1473 status = "disabled"; 1474 }; 1475 }; 1476 1477 emmc_phy: phy@f780 { 1478 compatible = "rockchip,rk3399-emmc-phy"; 1479 reg = <0xf780 0x24>; 1480 clocks = <&sdhci>; 1481 clock-names = "emmcclk"; 1482 drive-impedance-ohm = <50>; 1483 #phy-cells = <0>; 1484 status = "disabled"; 1485 }; 1486 1487 pcie_phy: pcie-phy { 1488 compatible = "rockchip,rk3399-pcie-phy"; 1489 clocks = <&cru SCLK_PCIEPHY_REF>; 1490 clock-names = "refclk"; 1491 #phy-cells = <1>; 1492 resets = <&cru SRST_PCIEPHY>; 1493 reset-names = "phy"; 1494 status = "disabled"; 1495 }; 1496 }; 1497 1498 tcphy0: phy@ff7c0000 { 1499 compatible = "rockchip,rk3399-typec-phy"; 1500 reg = <0x0 0xff7c0000 0x0 0x40000>; 1501 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1502 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1503 clock-names = "tcpdcore", "tcpdphy-ref"; 1504 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1505 assigned-clock-rates = <50000000>; 1506 power-domains = <&power RK3399_PD_TCPD0>; 1507 resets = <&cru SRST_UPHY0>, 1508 <&cru SRST_UPHY0_PIPE_L00>, 1509 <&cru SRST_P_UPHY0_TCPHY>; 1510 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1511 rockchip,grf = <&grf>; 1512 status = "disabled"; 1513 1514 tcphy0_dp: dp-port { 1515 #phy-cells = <0>; 1516 }; 1517 1518 tcphy0_usb3: usb3-port { 1519 #phy-cells = <0>; 1520 }; 1521 }; 1522 1523 tcphy1: phy@ff800000 { 1524 compatible = "rockchip,rk3399-typec-phy"; 1525 reg = <0x0 0xff800000 0x0 0x40000>; 1526 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1527 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1528 clock-names = "tcpdcore", "tcpdphy-ref"; 1529 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1530 assigned-clock-rates = <50000000>; 1531 power-domains = <&power RK3399_PD_TCPD1>; 1532 resets = <&cru SRST_UPHY1>, 1533 <&cru SRST_UPHY1_PIPE_L00>, 1534 <&cru SRST_P_UPHY1_TCPHY>; 1535 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1536 rockchip,grf = <&grf>; 1537 status = "disabled"; 1538 1539 tcphy1_dp: dp-port { 1540 #phy-cells = <0>; 1541 }; 1542 1543 tcphy1_usb3: usb3-port { 1544 #phy-cells = <0>; 1545 }; 1546 }; 1547 1548 watchdog@ff848000 { 1549 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt"; 1550 reg = <0x0 0xff848000 0x0 0x100>; 1551 clocks = <&cru PCLK_WDT>; 1552 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1553 }; 1554 1555 rktimer: rktimer@ff850000 { 1556 compatible = "rockchip,rk3399-timer"; 1557 reg = <0x0 0xff850000 0x0 0x1000>; 1558 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1559 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1560 clock-names = "pclk", "timer"; 1561 }; 1562 1563 spdif: spdif@ff870000 { 1564 compatible = "rockchip,rk3399-spdif"; 1565 reg = <0x0 0xff870000 0x0 0x1000>; 1566 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1567 dmas = <&dmac_bus 7>; 1568 dma-names = "tx"; 1569 clock-names = "mclk", "hclk"; 1570 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1571 pinctrl-names = "default"; 1572 pinctrl-0 = <&spdif_bus>; 1573 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1574 #sound-dai-cells = <0>; 1575 status = "disabled"; 1576 }; 1577 1578 i2s0: i2s@ff880000 { 1579 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1580 reg = <0x0 0xff880000 0x0 0x1000>; 1581 rockchip,grf = <&grf>; 1582 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1583 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1584 dma-names = "tx", "rx"; 1585 clock-names = "i2s_clk", "i2s_hclk"; 1586 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1587 pinctrl-names = "default"; 1588 pinctrl-0 = <&i2s0_8ch_bus>; 1589 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1590 #sound-dai-cells = <0>; 1591 status = "disabled"; 1592 }; 1593 1594 i2s1: i2s@ff890000 { 1595 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1596 reg = <0x0 0xff890000 0x0 0x1000>; 1597 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1598 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1599 dma-names = "tx", "rx"; 1600 clock-names = "i2s_clk", "i2s_hclk"; 1601 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1602 pinctrl-names = "default"; 1603 pinctrl-0 = <&i2s1_2ch_bus>; 1604 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1605 #sound-dai-cells = <0>; 1606 status = "disabled"; 1607 }; 1608 1609 i2s2: i2s@ff8a0000 { 1610 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1611 reg = <0x0 0xff8a0000 0x0 0x1000>; 1612 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1613 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1614 dma-names = "tx", "rx"; 1615 clock-names = "i2s_clk", "i2s_hclk"; 1616 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1617 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1618 #sound-dai-cells = <0>; 1619 status = "disabled"; 1620 }; 1621 1622 vopl: vop@ff8f0000 { 1623 compatible = "rockchip,rk3399-vop-lit"; 1624 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1625 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1626 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1627 assigned-clock-rates = <400000000>, <100000000>; 1628 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1629 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1630 iommus = <&vopl_mmu>; 1631 power-domains = <&power RK3399_PD_VOPL>; 1632 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1633 reset-names = "axi", "ahb", "dclk"; 1634 status = "disabled"; 1635 1636 vopl_out: port { 1637 #address-cells = <1>; 1638 #size-cells = <0>; 1639 1640 vopl_out_mipi: endpoint@0 { 1641 reg = <0>; 1642 remote-endpoint = <&mipi_in_vopl>; 1643 }; 1644 1645 vopl_out_edp: endpoint@1 { 1646 reg = <1>; 1647 remote-endpoint = <&edp_in_vopl>; 1648 }; 1649 1650 vopl_out_hdmi: endpoint@2 { 1651 reg = <2>; 1652 remote-endpoint = <&hdmi_in_vopl>; 1653 }; 1654 1655 vopl_out_mipi1: endpoint@3 { 1656 reg = <3>; 1657 remote-endpoint = <&mipi1_in_vopl>; 1658 }; 1659 1660 vopl_out_dp: endpoint@4 { 1661 reg = <4>; 1662 remote-endpoint = <&dp_in_vopl>; 1663 }; 1664 }; 1665 }; 1666 1667 vopl_mmu: iommu@ff8f3f00 { 1668 compatible = "rockchip,iommu"; 1669 reg = <0x0 0xff8f3f00 0x0 0x100>; 1670 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1671 interrupt-names = "vopl_mmu"; 1672 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1673 clock-names = "aclk", "iface"; 1674 power-domains = <&power RK3399_PD_VOPL>; 1675 #iommu-cells = <0>; 1676 status = "disabled"; 1677 }; 1678 1679 vopb: vop@ff900000 { 1680 compatible = "rockchip,rk3399-vop-big"; 1681 reg = <0x0 0xff900000 0x0 0x3efc>; 1682 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1683 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1684 assigned-clock-rates = <400000000>, <100000000>; 1685 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1686 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1687 iommus = <&vopb_mmu>; 1688 power-domains = <&power RK3399_PD_VOPB>; 1689 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1690 reset-names = "axi", "ahb", "dclk"; 1691 status = "disabled"; 1692 1693 vopb_out: port { 1694 #address-cells = <1>; 1695 #size-cells = <0>; 1696 1697 vopb_out_edp: endpoint@0 { 1698 reg = <0>; 1699 remote-endpoint = <&edp_in_vopb>; 1700 }; 1701 1702 vopb_out_mipi: endpoint@1 { 1703 reg = <1>; 1704 remote-endpoint = <&mipi_in_vopb>; 1705 }; 1706 1707 vopb_out_hdmi: endpoint@2 { 1708 reg = <2>; 1709 remote-endpoint = <&hdmi_in_vopb>; 1710 }; 1711 1712 vopb_out_mipi1: endpoint@3 { 1713 reg = <3>; 1714 remote-endpoint = <&mipi1_in_vopb>; 1715 }; 1716 1717 vopb_out_dp: endpoint@4 { 1718 reg = <4>; 1719 remote-endpoint = <&dp_in_vopb>; 1720 }; 1721 }; 1722 }; 1723 1724 vopb_mmu: iommu@ff903f00 { 1725 compatible = "rockchip,iommu"; 1726 reg = <0x0 0xff903f00 0x0 0x100>; 1727 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1728 interrupt-names = "vopb_mmu"; 1729 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1730 clock-names = "aclk", "iface"; 1731 power-domains = <&power RK3399_PD_VOPB>; 1732 #iommu-cells = <0>; 1733 status = "disabled"; 1734 }; 1735 1736 isp0: isp0@ff910000 { 1737 compatible = "rockchip,rk3399-cif-isp"; 1738 reg = <0x0 0xff910000 0x0 0x4000>; 1739 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1740 clocks = <&cru SCLK_ISP0>, 1741 <&cru ACLK_ISP0_WRAPPER>, 1742 <&cru HCLK_ISP0_WRAPPER>; 1743 clock-names = "isp", "aclk", "hclk"; 1744 iommus = <&isp0_mmu>; 1745 phys = <&mipi_dphy_rx0>; 1746 phy-names = "dphy"; 1747 power-domains = <&power RK3399_PD_ISP0>; 1748 status = "disabled"; 1749 1750 ports { 1751 #address-cells = <1>; 1752 #size-cells = <0>; 1753 1754 port@0 { 1755 reg = <0>; 1756 #address-cells = <1>; 1757 #size-cells = <0>; 1758 }; 1759 }; 1760 }; 1761 1762 isp0_mmu: iommu@ff914000 { 1763 compatible = "rockchip,iommu"; 1764 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1765 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1766 interrupt-names = "isp0_mmu"; 1767 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; 1768 clock-names = "aclk", "iface"; 1769 #iommu-cells = <0>; 1770 power-domains = <&power RK3399_PD_ISP0>; 1771 rockchip,disable-mmu-reset; 1772 }; 1773 1774 isp1_mmu: iommu@ff924000 { 1775 compatible = "rockchip,iommu"; 1776 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1777 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1778 interrupt-names = "isp1_mmu"; 1779 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; 1780 clock-names = "aclk", "iface"; 1781 #iommu-cells = <0>; 1782 power-domains = <&power RK3399_PD_ISP1>; 1783 rockchip,disable-mmu-reset; 1784 }; 1785 1786 hdmi_sound: hdmi-sound { 1787 compatible = "simple-audio-card"; 1788 simple-audio-card,format = "i2s"; 1789 simple-audio-card,mclk-fs = <256>; 1790 simple-audio-card,name = "hdmi-sound"; 1791 status = "disabled"; 1792 1793 simple-audio-card,cpu { 1794 sound-dai = <&i2s2>; 1795 }; 1796 simple-audio-card,codec { 1797 sound-dai = <&hdmi>; 1798 }; 1799 }; 1800 1801 hdmi: hdmi@ff940000 { 1802 compatible = "rockchip,rk3399-dw-hdmi"; 1803 reg = <0x0 0xff940000 0x0 0x20000>; 1804 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1805 clocks = <&cru PCLK_HDMI_CTRL>, 1806 <&cru SCLK_HDMI_SFR>, 1807 <&cru SCLK_HDMI_CEC>, 1808 <&cru PCLK_VIO_GRF>, 1809 <&cru PLL_VPLL>; 1810 clock-names = "iahb", "isfr", "cec", "grf", "vpll"; 1811 power-domains = <&power RK3399_PD_HDCP>; 1812 reg-io-width = <4>; 1813 rockchip,grf = <&grf>; 1814 #sound-dai-cells = <0>; 1815 status = "disabled"; 1816 1817 ports { 1818 hdmi_in: port { 1819 #address-cells = <1>; 1820 #size-cells = <0>; 1821 1822 hdmi_in_vopb: endpoint@0 { 1823 reg = <0>; 1824 remote-endpoint = <&vopb_out_hdmi>; 1825 }; 1826 hdmi_in_vopl: endpoint@1 { 1827 reg = <1>; 1828 remote-endpoint = <&vopl_out_hdmi>; 1829 }; 1830 }; 1831 }; 1832 }; 1833 1834 mipi_dsi: mipi@ff960000 { 1835 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1836 reg = <0x0 0xff960000 0x0 0x8000>; 1837 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1838 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1839 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1840 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1841 power-domains = <&power RK3399_PD_VIO>; 1842 resets = <&cru SRST_P_MIPI_DSI0>; 1843 reset-names = "apb"; 1844 rockchip,grf = <&grf>; 1845 #address-cells = <1>; 1846 #size-cells = <0>; 1847 status = "disabled"; 1848 1849 ports { 1850 #address-cells = <1>; 1851 #size-cells = <0>; 1852 1853 mipi_in: port@0 { 1854 reg = <0>; 1855 #address-cells = <1>; 1856 #size-cells = <0>; 1857 1858 mipi_in_vopb: endpoint@0 { 1859 reg = <0>; 1860 remote-endpoint = <&vopb_out_mipi>; 1861 }; 1862 mipi_in_vopl: endpoint@1 { 1863 reg = <1>; 1864 remote-endpoint = <&vopl_out_mipi>; 1865 }; 1866 }; 1867 }; 1868 }; 1869 1870 mipi_dsi1: mipi@ff968000 { 1871 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1872 reg = <0x0 0xff968000 0x0 0x8000>; 1873 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 1874 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 1875 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 1876 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1877 power-domains = <&power RK3399_PD_VIO>; 1878 resets = <&cru SRST_P_MIPI_DSI1>; 1879 reset-names = "apb"; 1880 rockchip,grf = <&grf>; 1881 #address-cells = <1>; 1882 #size-cells = <0>; 1883 status = "disabled"; 1884 1885 ports { 1886 #address-cells = <1>; 1887 #size-cells = <0>; 1888 1889 mipi1_in: port@0 { 1890 reg = <0>; 1891 #address-cells = <1>; 1892 #size-cells = <0>; 1893 1894 mipi1_in_vopb: endpoint@0 { 1895 reg = <0>; 1896 remote-endpoint = <&vopb_out_mipi1>; 1897 }; 1898 1899 mipi1_in_vopl: endpoint@1 { 1900 reg = <1>; 1901 remote-endpoint = <&vopl_out_mipi1>; 1902 }; 1903 }; 1904 }; 1905 }; 1906 1907 edp: edp@ff970000 { 1908 compatible = "rockchip,rk3399-edp"; 1909 reg = <0x0 0xff970000 0x0 0x8000>; 1910 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1911 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 1912 clock-names = "dp", "pclk", "grf"; 1913 pinctrl-names = "default"; 1914 pinctrl-0 = <&edp_hpd>; 1915 power-domains = <&power RK3399_PD_EDP>; 1916 resets = <&cru SRST_P_EDP_CTRL>; 1917 reset-names = "dp"; 1918 rockchip,grf = <&grf>; 1919 status = "disabled"; 1920 1921 ports { 1922 #address-cells = <1>; 1923 #size-cells = <0>; 1924 edp_in: port@0 { 1925 reg = <0>; 1926 #address-cells = <1>; 1927 #size-cells = <0>; 1928 1929 edp_in_vopb: endpoint@0 { 1930 reg = <0>; 1931 remote-endpoint = <&vopb_out_edp>; 1932 }; 1933 1934 edp_in_vopl: endpoint@1 { 1935 reg = <1>; 1936 remote-endpoint = <&vopl_out_edp>; 1937 }; 1938 }; 1939 }; 1940 }; 1941 1942 gpu: gpu@ff9a0000 { 1943 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 1944 reg = <0x0 0xff9a0000 0x0 0x10000>; 1945 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1946 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>, 1947 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 1948 interrupt-names = "job", "mmu", "gpu"; 1949 clocks = <&cru ACLK_GPU>; 1950 #cooling-cells = <2>; 1951 power-domains = <&power RK3399_PD_GPU>; 1952 status = "disabled"; 1953 }; 1954 1955 pinctrl: pinctrl { 1956 compatible = "rockchip,rk3399-pinctrl"; 1957 rockchip,grf = <&grf>; 1958 rockchip,pmu = <&pmugrf>; 1959 #address-cells = <2>; 1960 #size-cells = <2>; 1961 ranges; 1962 1963 gpio0: gpio0@ff720000 { 1964 compatible = "rockchip,gpio-bank"; 1965 reg = <0x0 0xff720000 0x0 0x100>; 1966 clocks = <&pmucru PCLK_GPIO0_PMU>; 1967 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1968 1969 gpio-controller; 1970 #gpio-cells = <0x2>; 1971 1972 interrupt-controller; 1973 #interrupt-cells = <0x2>; 1974 }; 1975 1976 gpio1: gpio1@ff730000 { 1977 compatible = "rockchip,gpio-bank"; 1978 reg = <0x0 0xff730000 0x0 0x100>; 1979 clocks = <&pmucru PCLK_GPIO1_PMU>; 1980 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1981 1982 gpio-controller; 1983 #gpio-cells = <0x2>; 1984 1985 interrupt-controller; 1986 #interrupt-cells = <0x2>; 1987 }; 1988 1989 gpio2: gpio2@ff780000 { 1990 compatible = "rockchip,gpio-bank"; 1991 reg = <0x0 0xff780000 0x0 0x100>; 1992 clocks = <&cru PCLK_GPIO2>; 1993 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1994 1995 gpio-controller; 1996 #gpio-cells = <0x2>; 1997 1998 interrupt-controller; 1999 #interrupt-cells = <0x2>; 2000 }; 2001 2002 gpio3: gpio3@ff788000 { 2003 compatible = "rockchip,gpio-bank"; 2004 reg = <0x0 0xff788000 0x0 0x100>; 2005 clocks = <&cru PCLK_GPIO3>; 2006 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 2007 2008 gpio-controller; 2009 #gpio-cells = <0x2>; 2010 2011 interrupt-controller; 2012 #interrupt-cells = <0x2>; 2013 }; 2014 2015 gpio4: gpio4@ff790000 { 2016 compatible = "rockchip,gpio-bank"; 2017 reg = <0x0 0xff790000 0x0 0x100>; 2018 clocks = <&cru PCLK_GPIO4>; 2019 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 2020 2021 gpio-controller; 2022 #gpio-cells = <0x2>; 2023 2024 interrupt-controller; 2025 #interrupt-cells = <0x2>; 2026 }; 2027 2028 pcfg_pull_up: pcfg-pull-up { 2029 bias-pull-up; 2030 }; 2031 2032 pcfg_pull_down: pcfg-pull-down { 2033 bias-pull-down; 2034 }; 2035 2036 pcfg_pull_none: pcfg-pull-none { 2037 bias-disable; 2038 }; 2039 2040 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 2041 bias-disable; 2042 drive-strength = <12>; 2043 }; 2044 2045 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 2046 bias-disable; 2047 drive-strength = <13>; 2048 }; 2049 2050 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 2051 bias-disable; 2052 drive-strength = <18>; 2053 }; 2054 2055 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 2056 bias-disable; 2057 drive-strength = <20>; 2058 }; 2059 2060 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 2061 bias-pull-up; 2062 drive-strength = <2>; 2063 }; 2064 2065 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 2066 bias-pull-up; 2067 drive-strength = <8>; 2068 }; 2069 2070 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 2071 bias-pull-up; 2072 drive-strength = <18>; 2073 }; 2074 2075 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 2076 bias-pull-up; 2077 drive-strength = <20>; 2078 }; 2079 2080 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 2081 bias-pull-down; 2082 drive-strength = <4>; 2083 }; 2084 2085 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 2086 bias-pull-down; 2087 drive-strength = <8>; 2088 }; 2089 2090 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 2091 bias-pull-down; 2092 drive-strength = <12>; 2093 }; 2094 2095 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 2096 bias-pull-down; 2097 drive-strength = <18>; 2098 }; 2099 2100 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 2101 bias-pull-down; 2102 drive-strength = <20>; 2103 }; 2104 2105 pcfg_output_high: pcfg-output-high { 2106 output-high; 2107 }; 2108 2109 pcfg_output_low: pcfg-output-low { 2110 output-low; 2111 }; 2112 2113 clock { 2114 clk_32k: clk-32k { 2115 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 2116 }; 2117 }; 2118 2119 edp { 2120 edp_hpd: edp-hpd { 2121 rockchip,pins = 2122 <4 RK_PC7 2 &pcfg_pull_none>; 2123 }; 2124 }; 2125 2126 gmac { 2127 rgmii_pins: rgmii-pins { 2128 rockchip,pins = 2129 /* mac_txclk */ 2130 <3 RK_PC1 1 &pcfg_pull_none_13ma>, 2131 /* mac_rxclk */ 2132 <3 RK_PB6 1 &pcfg_pull_none>, 2133 /* mac_mdio */ 2134 <3 RK_PB5 1 &pcfg_pull_none>, 2135 /* mac_txen */ 2136 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2137 /* mac_clk */ 2138 <3 RK_PB3 1 &pcfg_pull_none>, 2139 /* mac_rxdv */ 2140 <3 RK_PB1 1 &pcfg_pull_none>, 2141 /* mac_mdc */ 2142 <3 RK_PB0 1 &pcfg_pull_none>, 2143 /* mac_rxd1 */ 2144 <3 RK_PA7 1 &pcfg_pull_none>, 2145 /* mac_rxd0 */ 2146 <3 RK_PA6 1 &pcfg_pull_none>, 2147 /* mac_txd1 */ 2148 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2149 /* mac_txd0 */ 2150 <3 RK_PA4 1 &pcfg_pull_none_13ma>, 2151 /* mac_rxd3 */ 2152 <3 RK_PA3 1 &pcfg_pull_none>, 2153 /* mac_rxd2 */ 2154 <3 RK_PA2 1 &pcfg_pull_none>, 2155 /* mac_txd3 */ 2156 <3 RK_PA1 1 &pcfg_pull_none_13ma>, 2157 /* mac_txd2 */ 2158 <3 RK_PA0 1 &pcfg_pull_none_13ma>; 2159 }; 2160 2161 rmii_pins: rmii-pins { 2162 rockchip,pins = 2163 /* mac_mdio */ 2164 <3 RK_PB5 1 &pcfg_pull_none>, 2165 /* mac_txen */ 2166 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2167 /* mac_clk */ 2168 <3 RK_PB3 1 &pcfg_pull_none>, 2169 /* mac_rxer */ 2170 <3 RK_PB2 1 &pcfg_pull_none>, 2171 /* mac_rxdv */ 2172 <3 RK_PB1 1 &pcfg_pull_none>, 2173 /* mac_mdc */ 2174 <3 RK_PB0 1 &pcfg_pull_none>, 2175 /* mac_rxd1 */ 2176 <3 RK_PA7 1 &pcfg_pull_none>, 2177 /* mac_rxd0 */ 2178 <3 RK_PA6 1 &pcfg_pull_none>, 2179 /* mac_txd1 */ 2180 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2181 /* mac_txd0 */ 2182 <3 RK_PA4 1 &pcfg_pull_none_13ma>; 2183 }; 2184 }; 2185 2186 i2c0 { 2187 i2c0_xfer: i2c0-xfer { 2188 rockchip,pins = 2189 <1 RK_PB7 2 &pcfg_pull_none>, 2190 <1 RK_PC0 2 &pcfg_pull_none>; 2191 }; 2192 }; 2193 2194 i2c1 { 2195 i2c1_xfer: i2c1-xfer { 2196 rockchip,pins = 2197 <4 RK_PA2 1 &pcfg_pull_none>, 2198 <4 RK_PA1 1 &pcfg_pull_none>; 2199 }; 2200 }; 2201 2202 i2c2 { 2203 i2c2_xfer: i2c2-xfer { 2204 rockchip,pins = 2205 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 2206 <2 RK_PA0 2 &pcfg_pull_none_12ma>; 2207 }; 2208 }; 2209 2210 i2c3 { 2211 i2c3_xfer: i2c3-xfer { 2212 rockchip,pins = 2213 <4 RK_PC1 1 &pcfg_pull_none>, 2214 <4 RK_PC0 1 &pcfg_pull_none>; 2215 }; 2216 }; 2217 2218 i2c4 { 2219 i2c4_xfer: i2c4-xfer { 2220 rockchip,pins = 2221 <1 RK_PB4 1 &pcfg_pull_none>, 2222 <1 RK_PB3 1 &pcfg_pull_none>; 2223 }; 2224 }; 2225 2226 i2c5 { 2227 i2c5_xfer: i2c5-xfer { 2228 rockchip,pins = 2229 <3 RK_PB3 2 &pcfg_pull_none>, 2230 <3 RK_PB2 2 &pcfg_pull_none>; 2231 }; 2232 }; 2233 2234 i2c6 { 2235 i2c6_xfer: i2c6-xfer { 2236 rockchip,pins = 2237 <2 RK_PB2 2 &pcfg_pull_none>, 2238 <2 RK_PB1 2 &pcfg_pull_none>; 2239 }; 2240 }; 2241 2242 i2c7 { 2243 i2c7_xfer: i2c7-xfer { 2244 rockchip,pins = 2245 <2 RK_PB0 2 &pcfg_pull_none>, 2246 <2 RK_PA7 2 &pcfg_pull_none>; 2247 }; 2248 }; 2249 2250 i2c8 { 2251 i2c8_xfer: i2c8-xfer { 2252 rockchip,pins = 2253 <1 RK_PC5 1 &pcfg_pull_none>, 2254 <1 RK_PC4 1 &pcfg_pull_none>; 2255 }; 2256 }; 2257 2258 i2s0 { 2259 i2s0_2ch_bus: i2s0-2ch-bus { 2260 rockchip,pins = 2261 <3 RK_PD0 1 &pcfg_pull_none>, 2262 <3 RK_PD1 1 &pcfg_pull_none>, 2263 <3 RK_PD2 1 &pcfg_pull_none>, 2264 <3 RK_PD3 1 &pcfg_pull_none>, 2265 <3 RK_PD7 1 &pcfg_pull_none>, 2266 <4 RK_PA0 1 &pcfg_pull_none>; 2267 }; 2268 2269 i2s0_8ch_bus: i2s0-8ch-bus { 2270 rockchip,pins = 2271 <3 RK_PD0 1 &pcfg_pull_none>, 2272 <3 RK_PD1 1 &pcfg_pull_none>, 2273 <3 RK_PD2 1 &pcfg_pull_none>, 2274 <3 RK_PD3 1 &pcfg_pull_none>, 2275 <3 RK_PD4 1 &pcfg_pull_none>, 2276 <3 RK_PD5 1 &pcfg_pull_none>, 2277 <3 RK_PD6 1 &pcfg_pull_none>, 2278 <3 RK_PD7 1 &pcfg_pull_none>, 2279 <4 RK_PA0 1 &pcfg_pull_none>; 2280 }; 2281 }; 2282 2283 i2s1 { 2284 i2s1_2ch_bus: i2s1-2ch-bus { 2285 rockchip,pins = 2286 <4 RK_PA3 1 &pcfg_pull_none>, 2287 <4 RK_PA4 1 &pcfg_pull_none>, 2288 <4 RK_PA5 1 &pcfg_pull_none>, 2289 <4 RK_PA6 1 &pcfg_pull_none>, 2290 <4 RK_PA7 1 &pcfg_pull_none>; 2291 }; 2292 }; 2293 2294 sdio0 { 2295 sdio0_bus1: sdio0-bus1 { 2296 rockchip,pins = 2297 <2 RK_PC4 1 &pcfg_pull_up>; 2298 }; 2299 2300 sdio0_bus4: sdio0-bus4 { 2301 rockchip,pins = 2302 <2 RK_PC4 1 &pcfg_pull_up>, 2303 <2 RK_PC5 1 &pcfg_pull_up>, 2304 <2 RK_PC6 1 &pcfg_pull_up>, 2305 <2 RK_PC7 1 &pcfg_pull_up>; 2306 }; 2307 2308 sdio0_cmd: sdio0-cmd { 2309 rockchip,pins = 2310 <2 RK_PD0 1 &pcfg_pull_up>; 2311 }; 2312 2313 sdio0_clk: sdio0-clk { 2314 rockchip,pins = 2315 <2 RK_PD1 1 &pcfg_pull_none>; 2316 }; 2317 2318 sdio0_cd: sdio0-cd { 2319 rockchip,pins = 2320 <2 RK_PD2 1 &pcfg_pull_up>; 2321 }; 2322 2323 sdio0_pwr: sdio0-pwr { 2324 rockchip,pins = 2325 <2 RK_PD3 1 &pcfg_pull_up>; 2326 }; 2327 2328 sdio0_bkpwr: sdio0-bkpwr { 2329 rockchip,pins = 2330 <2 RK_PD4 1 &pcfg_pull_up>; 2331 }; 2332 2333 sdio0_wp: sdio0-wp { 2334 rockchip,pins = 2335 <0 RK_PA3 1 &pcfg_pull_up>; 2336 }; 2337 2338 sdio0_int: sdio0-int { 2339 rockchip,pins = 2340 <0 RK_PA4 1 &pcfg_pull_up>; 2341 }; 2342 }; 2343 2344 sdmmc { 2345 sdmmc_bus1: sdmmc-bus1 { 2346 rockchip,pins = 2347 <4 RK_PB0 1 &pcfg_pull_up>; 2348 }; 2349 2350 sdmmc_bus4: sdmmc-bus4 { 2351 rockchip,pins = 2352 <4 RK_PB0 1 &pcfg_pull_up>, 2353 <4 RK_PB1 1 &pcfg_pull_up>, 2354 <4 RK_PB2 1 &pcfg_pull_up>, 2355 <4 RK_PB3 1 &pcfg_pull_up>; 2356 }; 2357 2358 sdmmc_clk: sdmmc-clk { 2359 rockchip,pins = 2360 <4 RK_PB4 1 &pcfg_pull_none>; 2361 }; 2362 2363 sdmmc_cmd: sdmmc-cmd { 2364 rockchip,pins = 2365 <4 RK_PB5 1 &pcfg_pull_up>; 2366 }; 2367 2368 sdmmc_cd: sdmmc-cd { 2369 rockchip,pins = 2370 <0 RK_PA7 1 &pcfg_pull_up>; 2371 }; 2372 2373 sdmmc_wp: sdmmc-wp { 2374 rockchip,pins = 2375 <0 RK_PB0 1 &pcfg_pull_up>; 2376 }; 2377 }; 2378 2379 suspend { 2380 ap_pwroff: ap-pwroff { 2381 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; 2382 }; 2383 2384 ddrio_pwroff: ddrio-pwroff { 2385 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 2386 }; 2387 }; 2388 2389 spdif { 2390 spdif_bus: spdif-bus { 2391 rockchip,pins = 2392 <4 RK_PC5 1 &pcfg_pull_none>; 2393 }; 2394 2395 spdif_bus_1: spdif-bus-1 { 2396 rockchip,pins = 2397 <3 RK_PC0 3 &pcfg_pull_none>; 2398 }; 2399 }; 2400 2401 spi0 { 2402 spi0_clk: spi0-clk { 2403 rockchip,pins = 2404 <3 RK_PA6 2 &pcfg_pull_up>; 2405 }; 2406 spi0_cs0: spi0-cs0 { 2407 rockchip,pins = 2408 <3 RK_PA7 2 &pcfg_pull_up>; 2409 }; 2410 spi0_cs1: spi0-cs1 { 2411 rockchip,pins = 2412 <3 RK_PB0 2 &pcfg_pull_up>; 2413 }; 2414 spi0_tx: spi0-tx { 2415 rockchip,pins = 2416 <3 RK_PA5 2 &pcfg_pull_up>; 2417 }; 2418 spi0_rx: spi0-rx { 2419 rockchip,pins = 2420 <3 RK_PA4 2 &pcfg_pull_up>; 2421 }; 2422 }; 2423 2424 spi1 { 2425 spi1_clk: spi1-clk { 2426 rockchip,pins = 2427 <1 RK_PB1 2 &pcfg_pull_up>; 2428 }; 2429 spi1_cs0: spi1-cs0 { 2430 rockchip,pins = 2431 <1 RK_PB2 2 &pcfg_pull_up>; 2432 }; 2433 spi1_rx: spi1-rx { 2434 rockchip,pins = 2435 <1 RK_PA7 2 &pcfg_pull_up>; 2436 }; 2437 spi1_tx: spi1-tx { 2438 rockchip,pins = 2439 <1 RK_PB0 2 &pcfg_pull_up>; 2440 }; 2441 }; 2442 2443 spi2 { 2444 spi2_clk: spi2-clk { 2445 rockchip,pins = 2446 <2 RK_PB3 1 &pcfg_pull_up>; 2447 }; 2448 spi2_cs0: spi2-cs0 { 2449 rockchip,pins = 2450 <2 RK_PB4 1 &pcfg_pull_up>; 2451 }; 2452 spi2_rx: spi2-rx { 2453 rockchip,pins = 2454 <2 RK_PB1 1 &pcfg_pull_up>; 2455 }; 2456 spi2_tx: spi2-tx { 2457 rockchip,pins = 2458 <2 RK_PB2 1 &pcfg_pull_up>; 2459 }; 2460 }; 2461 2462 spi3 { 2463 spi3_clk: spi3-clk { 2464 rockchip,pins = 2465 <1 RK_PC1 1 &pcfg_pull_up>; 2466 }; 2467 spi3_cs0: spi3-cs0 { 2468 rockchip,pins = 2469 <1 RK_PC2 1 &pcfg_pull_up>; 2470 }; 2471 spi3_rx: spi3-rx { 2472 rockchip,pins = 2473 <1 RK_PB7 1 &pcfg_pull_up>; 2474 }; 2475 spi3_tx: spi3-tx { 2476 rockchip,pins = 2477 <1 RK_PC0 1 &pcfg_pull_up>; 2478 }; 2479 }; 2480 2481 spi4 { 2482 spi4_clk: spi4-clk { 2483 rockchip,pins = 2484 <3 RK_PA2 2 &pcfg_pull_up>; 2485 }; 2486 spi4_cs0: spi4-cs0 { 2487 rockchip,pins = 2488 <3 RK_PA3 2 &pcfg_pull_up>; 2489 }; 2490 spi4_rx: spi4-rx { 2491 rockchip,pins = 2492 <3 RK_PA0 2 &pcfg_pull_up>; 2493 }; 2494 spi4_tx: spi4-tx { 2495 rockchip,pins = 2496 <3 RK_PA1 2 &pcfg_pull_up>; 2497 }; 2498 }; 2499 2500 spi5 { 2501 spi5_clk: spi5-clk { 2502 rockchip,pins = 2503 <2 RK_PC6 2 &pcfg_pull_up>; 2504 }; 2505 spi5_cs0: spi5-cs0 { 2506 rockchip,pins = 2507 <2 RK_PC7 2 &pcfg_pull_up>; 2508 }; 2509 spi5_rx: spi5-rx { 2510 rockchip,pins = 2511 <2 RK_PC4 2 &pcfg_pull_up>; 2512 }; 2513 spi5_tx: spi5-tx { 2514 rockchip,pins = 2515 <2 RK_PC5 2 &pcfg_pull_up>; 2516 }; 2517 }; 2518 2519 testclk { 2520 test_clkout0: test-clkout0 { 2521 rockchip,pins = 2522 <0 RK_PA0 1 &pcfg_pull_none>; 2523 }; 2524 2525 test_clkout1: test-clkout1 { 2526 rockchip,pins = 2527 <2 RK_PD1 2 &pcfg_pull_none>; 2528 }; 2529 2530 test_clkout2: test-clkout2 { 2531 rockchip,pins = 2532 <0 RK_PB0 3 &pcfg_pull_none>; 2533 }; 2534 }; 2535 2536 tsadc { 2537 otp_pin: otp-pin { 2538 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2539 }; 2540 2541 otp_out: otp-out { 2542 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 2543 }; 2544 }; 2545 2546 uart0 { 2547 uart0_xfer: uart0-xfer { 2548 rockchip,pins = 2549 <2 RK_PC0 1 &pcfg_pull_up>, 2550 <2 RK_PC1 1 &pcfg_pull_none>; 2551 }; 2552 2553 uart0_cts: uart0-cts { 2554 rockchip,pins = 2555 <2 RK_PC2 1 &pcfg_pull_none>; 2556 }; 2557 2558 uart0_rts: uart0-rts { 2559 rockchip,pins = 2560 <2 RK_PC3 1 &pcfg_pull_none>; 2561 }; 2562 }; 2563 2564 uart1 { 2565 uart1_xfer: uart1-xfer { 2566 rockchip,pins = 2567 <3 RK_PB4 2 &pcfg_pull_up>, 2568 <3 RK_PB5 2 &pcfg_pull_none>; 2569 }; 2570 }; 2571 2572 uart2a { 2573 uart2a_xfer: uart2a-xfer { 2574 rockchip,pins = 2575 <4 RK_PB0 2 &pcfg_pull_up>, 2576 <4 RK_PB1 2 &pcfg_pull_none>; 2577 }; 2578 }; 2579 2580 uart2b { 2581 uart2b_xfer: uart2b-xfer { 2582 rockchip,pins = 2583 <4 RK_PC0 2 &pcfg_pull_up>, 2584 <4 RK_PC1 2 &pcfg_pull_none>; 2585 }; 2586 }; 2587 2588 uart2c { 2589 uart2c_xfer: uart2c-xfer { 2590 rockchip,pins = 2591 <4 RK_PC3 1 &pcfg_pull_up>, 2592 <4 RK_PC4 1 &pcfg_pull_none>; 2593 }; 2594 }; 2595 2596 uart3 { 2597 uart3_xfer: uart3-xfer { 2598 rockchip,pins = 2599 <3 RK_PB6 2 &pcfg_pull_up>, 2600 <3 RK_PB7 2 &pcfg_pull_none>; 2601 }; 2602 2603 uart3_cts: uart3-cts { 2604 rockchip,pins = 2605 <3 RK_PC0 2 &pcfg_pull_none>; 2606 }; 2607 2608 uart3_rts: uart3-rts { 2609 rockchip,pins = 2610 <3 RK_PC1 2 &pcfg_pull_none>; 2611 }; 2612 }; 2613 2614 uart4 { 2615 uart4_xfer: uart4-xfer { 2616 rockchip,pins = 2617 <1 RK_PA7 1 &pcfg_pull_up>, 2618 <1 RK_PB0 1 &pcfg_pull_none>; 2619 }; 2620 }; 2621 2622 uarthdcp { 2623 uarthdcp_xfer: uarthdcp-xfer { 2624 rockchip,pins = 2625 <4 RK_PC5 2 &pcfg_pull_up>, 2626 <4 RK_PC6 2 &pcfg_pull_none>; 2627 }; 2628 }; 2629 2630 pwm0 { 2631 pwm0_pin: pwm0-pin { 2632 rockchip,pins = 2633 <4 RK_PC2 1 &pcfg_pull_none>; 2634 }; 2635 2636 pwm0_pin_pull_down: pwm0-pin-pull-down { 2637 rockchip,pins = 2638 <4 RK_PC2 1 &pcfg_pull_down>; 2639 }; 2640 2641 vop0_pwm_pin: vop0-pwm-pin { 2642 rockchip,pins = 2643 <4 RK_PC2 2 &pcfg_pull_none>; 2644 }; 2645 2646 vop1_pwm_pin: vop1-pwm-pin { 2647 rockchip,pins = 2648 <4 RK_PC2 3 &pcfg_pull_none>; 2649 }; 2650 }; 2651 2652 pwm1 { 2653 pwm1_pin: pwm1-pin { 2654 rockchip,pins = 2655 <4 RK_PC6 1 &pcfg_pull_none>; 2656 }; 2657 2658 pwm1_pin_pull_down: pwm1-pin-pull-down { 2659 rockchip,pins = 2660 <4 RK_PC6 1 &pcfg_pull_down>; 2661 }; 2662 }; 2663 2664 pwm2 { 2665 pwm2_pin: pwm2-pin { 2666 rockchip,pins = 2667 <1 RK_PC3 1 &pcfg_pull_none>; 2668 }; 2669 2670 pwm2_pin_pull_down: pwm2-pin-pull-down { 2671 rockchip,pins = 2672 <1 RK_PC3 1 &pcfg_pull_down>; 2673 }; 2674 }; 2675 2676 pwm3a { 2677 pwm3a_pin: pwm3a-pin { 2678 rockchip,pins = 2679 <0 RK_PA6 1 &pcfg_pull_none>; 2680 }; 2681 }; 2682 2683 pwm3b { 2684 pwm3b_pin: pwm3b-pin { 2685 rockchip,pins = 2686 <1 RK_PB6 1 &pcfg_pull_none>; 2687 }; 2688 }; 2689 2690 hdmi { 2691 hdmi_i2c_xfer: hdmi-i2c-xfer { 2692 rockchip,pins = 2693 <4 RK_PC1 3 &pcfg_pull_none>, 2694 <4 RK_PC0 3 &pcfg_pull_none>; 2695 }; 2696 2697 hdmi_cec: hdmi-cec { 2698 rockchip,pins = 2699 <4 RK_PC7 1 &pcfg_pull_none>; 2700 }; 2701 }; 2702 2703 pcie { 2704 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2705 rockchip,pins = 2706 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2707 }; 2708 2709 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2710 rockchip,pins = 2711 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2712 }; 2713 }; 2714 2715 }; 2716}; 2717