1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy-am654-serdes.h> 8 9&cbass_main { 10 msmc_ram: sram@70000000 { 11 compatible = "mmio-sram"; 12 reg = <0x0 0x70000000 0x0 0x200000>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 ranges = <0x0 0x0 0x70000000 0x200000>; 16 17 atf-sram@0 { 18 reg = <0x0 0x20000>; 19 }; 20 21 sysfw-sram@f0000 { 22 reg = <0xf0000 0x10000>; 23 }; 24 25 l3cache-sram@100000 { 26 reg = <0x100000 0x100000>; 27 }; 28 }; 29 30 gic500: interrupt-controller@1800000 { 31 compatible = "arm,gic-v3"; 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 #interrupt-cells = <3>; 36 interrupt-controller; 37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 38 <0x00 0x01880000 0x00 0x90000>, /* GICR */ 39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 42 /* 43 * vcpumntirq: 44 * virtual CPU interface maintenance interrupt 45 */ 46 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 47 48 gic_its: msi-controller@1820000 { 49 compatible = "arm,gic-v3-its"; 50 reg = <0x00 0x01820000 0x00 0x10000>; 51 socionext,synquacer-pre-its = <0x1000000 0x400000>; 52 msi-controller; 53 #msi-cells = <1>; 54 }; 55 }; 56 57 serdes0: serdes@900000 { 58 compatible = "ti,phy-am654-serdes"; 59 reg = <0x0 0x900000 0x0 0x2000>; 60 reg-names = "serdes"; 61 #phy-cells = <2>; 62 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 63 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; 64 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; 65 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; 66 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; 67 ti,serdes-clk = <&serdes0_clk>; 68 #clock-cells = <1>; 69 mux-controls = <&serdes_mux 0>; 70 }; 71 72 serdes1: serdes@910000 { 73 compatible = "ti,phy-am654-serdes"; 74 reg = <0x0 0x910000 0x0 0x2000>; 75 reg-names = "serdes"; 76 #phy-cells = <2>; 77 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 78 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; 79 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; 80 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; 81 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; 82 ti,serdes-clk = <&serdes1_clk>; 83 #clock-cells = <1>; 84 mux-controls = <&serdes_mux 1>; 85 }; 86 87 main_uart0: serial@2800000 { 88 compatible = "ti,am654-uart"; 89 reg = <0x00 0x02800000 0x00 0x100>; 90 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 91 clock-frequency = <48000000>; 92 current-speed = <115200>; 93 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 94 }; 95 96 main_uart1: serial@2810000 { 97 compatible = "ti,am654-uart"; 98 reg = <0x00 0x02810000 0x00 0x100>; 99 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 100 clock-frequency = <48000000>; 101 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 102 }; 103 104 main_uart2: serial@2820000 { 105 compatible = "ti,am654-uart"; 106 reg = <0x00 0x02820000 0x00 0x100>; 107 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 108 clock-frequency = <48000000>; 109 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 110 }; 111 112 crypto: crypto@4e00000 { 113 compatible = "ti,am654-sa2ul"; 114 reg = <0x0 0x4e00000 0x0 0x1200>; 115 power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>; 116 #address-cells = <2>; 117 #size-cells = <2>; 118 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 119 120 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 121 <&main_udmap 0x4001>; 122 dma-names = "tx", "rx1", "rx2"; 123 124 rng: rng@4e10000 { 125 compatible = "inside-secure,safexcel-eip76"; 126 reg = <0x0 0x4e10000 0x0 0x7d>; 127 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 128 clocks = <&k3_clks 136 1>; 129 }; 130 }; 131 132 main_pmx0: pinctrl@11c000 { 133 compatible = "pinctrl-single"; 134 reg = <0x0 0x11c000 0x0 0x2e4>; 135 #pinctrl-cells = <1>; 136 pinctrl-single,register-width = <32>; 137 pinctrl-single,function-mask = <0xffffffff>; 138 }; 139 140 main_pmx1: pinctrl@11c2e8 { 141 compatible = "pinctrl-single"; 142 reg = <0x0 0x11c2e8 0x0 0x24>; 143 #pinctrl-cells = <1>; 144 pinctrl-single,register-width = <32>; 145 pinctrl-single,function-mask = <0xffffffff>; 146 }; 147 148 main_i2c0: i2c@2000000 { 149 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 150 reg = <0x0 0x2000000 0x0 0x100>; 151 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 152 #address-cells = <1>; 153 #size-cells = <0>; 154 clock-names = "fck"; 155 clocks = <&k3_clks 110 1>; 156 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 157 }; 158 159 main_i2c1: i2c@2010000 { 160 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 161 reg = <0x0 0x2010000 0x0 0x100>; 162 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 clock-names = "fck"; 166 clocks = <&k3_clks 111 1>; 167 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 168 }; 169 170 main_i2c2: i2c@2020000 { 171 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 172 reg = <0x0 0x2020000 0x0 0x100>; 173 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 clock-names = "fck"; 177 clocks = <&k3_clks 112 1>; 178 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 179 }; 180 181 main_i2c3: i2c@2030000 { 182 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 183 reg = <0x0 0x2030000 0x0 0x100>; 184 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 clock-names = "fck"; 188 clocks = <&k3_clks 113 1>; 189 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 190 }; 191 192 ecap0: pwm@3100000 { 193 compatible = "ti,am654-ecap", "ti,am3352-ecap"; 194 #pwm-cells = <3>; 195 reg = <0x0 0x03100000 0x0 0x60>; 196 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 197 clocks = <&k3_clks 39 0>; 198 clock-names = "fck"; 199 }; 200 201 main_spi0: spi@2100000 { 202 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 203 reg = <0x0 0x2100000 0x0 0x400>; 204 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&k3_clks 137 1>; 206 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 210 dma-names = "tx0", "rx0"; 211 }; 212 213 main_spi1: spi@2110000 { 214 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 215 reg = <0x0 0x2110000 0x0 0x400>; 216 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&k3_clks 138 1>; 218 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 assigned-clocks = <&k3_clks 137 1>; 222 assigned-clock-rates = <48000000>; 223 }; 224 225 main_spi2: spi@2120000 { 226 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 227 reg = <0x0 0x2120000 0x0 0x400>; 228 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&k3_clks 139 1>; 230 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 }; 234 235 main_spi3: spi@2130000 { 236 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 237 reg = <0x0 0x2130000 0x0 0x400>; 238 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&k3_clks 140 1>; 240 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 }; 244 245 main_spi4: spi@2140000 { 246 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 247 reg = <0x0 0x2140000 0x0 0x400>; 248 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&k3_clks 141 1>; 250 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 }; 254 255 sdhci0: mmc@4f80000 { 256 compatible = "ti,am654-sdhci-5.1"; 257 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; 258 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 259 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; 260 clock-names = "clk_ahb", "clk_xin"; 261 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 262 mmc-ddr-1_8v; 263 mmc-hs200-1_8v; 264 ti,otap-del-sel-legacy = <0x0>; 265 ti,otap-del-sel-mmc-hs = <0x0>; 266 ti,otap-del-sel-sd-hs = <0x0>; 267 ti,otap-del-sel-sdr12 = <0x0>; 268 ti,otap-del-sel-sdr25 = <0x0>; 269 ti,otap-del-sel-sdr50 = <0x8>; 270 ti,otap-del-sel-sdr104 = <0x7>; 271 ti,otap-del-sel-ddr50 = <0x5>; 272 ti,otap-del-sel-ddr52 = <0x5>; 273 ti,otap-del-sel-hs200 = <0x5>; 274 ti,otap-del-sel-hs400 = <0x0>; 275 ti,trm-icp = <0x8>; 276 dma-coherent; 277 }; 278 279 sdhci1: mmc@4fa0000 { 280 compatible = "ti,am654-sdhci-5.1"; 281 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; 282 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; 283 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>; 284 clock-names = "clk_ahb", "clk_xin"; 285 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 286 ti,otap-del-sel-legacy = <0x0>; 287 ti,otap-del-sel-mmc-hs = <0x0>; 288 ti,otap-del-sel-sd-hs = <0x0>; 289 ti,otap-del-sel-sdr12 = <0x0>; 290 ti,otap-del-sel-sdr25 = <0x0>; 291 ti,otap-del-sel-sdr50 = <0x8>; 292 ti,otap-del-sel-sdr104 = <0x7>; 293 ti,otap-del-sel-ddr50 = <0x4>; 294 ti,otap-del-sel-ddr52 = <0x4>; 295 ti,otap-del-sel-hs200 = <0x7>; 296 ti,clkbuf-sel = <0x7>; 297 ti,otap-del-sel = <0x2>; 298 ti,trm-icp = <0x8>; 299 dma-coherent; 300 }; 301 302 scm_conf: scm-conf@100000 { 303 compatible = "syscon", "simple-mfd"; 304 reg = <0 0x00100000 0 0x1c000>; 305 #address-cells = <1>; 306 #size-cells = <1>; 307 ranges = <0x0 0x0 0x00100000 0x1c000>; 308 309 pcie0_mode: pcie-mode@4060 { 310 compatible = "syscon"; 311 reg = <0x00004060 0x4>; 312 }; 313 314 pcie1_mode: pcie-mode@4070 { 315 compatible = "syscon"; 316 reg = <0x00004070 0x4>; 317 }; 318 319 pcie_devid: pcie-devid@210 { 320 compatible = "syscon"; 321 reg = <0x00000210 0x4>; 322 }; 323 324 serdes0_clk: clock@4080 { 325 compatible = "syscon"; 326 reg = <0x00004080 0x4>; 327 }; 328 329 serdes1_clk: clock@4090 { 330 compatible = "syscon"; 331 reg = <0x00004090 0x4>; 332 }; 333 334 serdes_mux: mux-controller { 335 compatible = "mmio-mux"; 336 #mux-control-cells = <1>; 337 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ 338 <0x4090 0x3>; /* SERDES1 lane select */ 339 }; 340 341 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { 342 compatible = "syscon"; 343 reg = <0x0000041e0 0x14>; 344 }; 345 346 ehrpwm_tbclk: clock@4140 { 347 compatible = "ti,am654-ehrpwm-tbclk", "syscon"; 348 reg = <0x4140 0x18>; 349 #clock-cells = <1>; 350 }; 351 }; 352 353 dwc3_0: dwc3@4000000 { 354 compatible = "ti,am654-dwc3"; 355 reg = <0x0 0x4000000 0x0 0x4000>; 356 #address-cells = <1>; 357 #size-cells = <1>; 358 ranges = <0x0 0x0 0x4000000 0x20000>; 359 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 360 dma-coherent; 361 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 362 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 363 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 364 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 365 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ 366 367 usb0: usb@10000 { 368 compatible = "snps,dwc3"; 369 reg = <0x10000 0x10000>; 370 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 373 interrupt-names = "peripheral", 374 "host", 375 "otg"; 376 maximum-speed = "high-speed"; 377 dr_mode = "otg"; 378 phys = <&usb0_phy>; 379 phy-names = "usb2-phy"; 380 snps,dis_u3_susphy_quirk; 381 }; 382 }; 383 384 usb0_phy: phy@4100000 { 385 compatible = "ti,am654-usb2", "ti,omap-usb2"; 386 reg = <0x0 0x4100000 0x0 0x54>; 387 syscon-phy-power = <&scm_conf 0x4000>; 388 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; 389 clock-names = "wkupclk", "refclk"; 390 #phy-cells = <0>; 391 }; 392 393 dwc3_1: dwc3@4020000 { 394 compatible = "ti,am654-dwc3"; 395 reg = <0x0 0x4020000 0x0 0x4000>; 396 #address-cells = <1>; 397 #size-cells = <1>; 398 ranges = <0x0 0x0 0x4020000 0x20000>; 399 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 400 dma-coherent; 401 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 402 clocks = <&k3_clks 152 2>; 403 assigned-clocks = <&k3_clks 152 2>; 404 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 405 406 usb1: usb@10000 { 407 compatible = "snps,dwc3"; 408 reg = <0x10000 0x10000>; 409 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 412 interrupt-names = "peripheral", 413 "host", 414 "otg"; 415 maximum-speed = "high-speed"; 416 dr_mode = "otg"; 417 phys = <&usb1_phy>; 418 phy-names = "usb2-phy"; 419 }; 420 }; 421 422 usb1_phy: phy@4110000 { 423 compatible = "ti,am654-usb2", "ti,omap-usb2"; 424 reg = <0x0 0x4110000 0x0 0x54>; 425 syscon-phy-power = <&scm_conf 0x4020>; 426 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; 427 clock-names = "wkupclk", "refclk"; 428 #phy-cells = <0>; 429 }; 430 431 intr_main_gpio: interrupt-controller@a00000 { 432 compatible = "ti,sci-intr"; 433 reg = <0x0 0x00a00000 0x0 0x400>; 434 ti,intr-trigger-type = <1>; 435 interrupt-controller; 436 interrupt-parent = <&gic500>; 437 #interrupt-cells = <1>; 438 ti,sci = <&dmsc>; 439 ti,sci-dev-id = <100>; 440 ti,interrupt-ranges = <0 392 32>; 441 }; 442 443 main_navss: bus@30800000 { 444 compatible = "simple-mfd"; 445 #address-cells = <2>; 446 #size-cells = <2>; 447 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>; 448 dma-coherent; 449 dma-ranges; 450 451 ti,sci-dev-id = <118>; 452 453 intr_main_navss: interrupt-controller@310e0000 { 454 compatible = "ti,sci-intr"; 455 reg = <0x0 0x310e0000 0x0 0x2000>; 456 ti,intr-trigger-type = <4>; 457 interrupt-controller; 458 interrupt-parent = <&gic500>; 459 #interrupt-cells = <1>; 460 ti,sci = <&dmsc>; 461 ti,sci-dev-id = <182>; 462 ti,interrupt-ranges = <0 64 64>, 463 <64 448 64>; 464 }; 465 466 inta_main_udmass: interrupt-controller@33d00000 { 467 compatible = "ti,sci-inta"; 468 reg = <0x0 0x33d00000 0x0 0x100000>; 469 interrupt-controller; 470 interrupt-parent = <&intr_main_navss>; 471 msi-controller; 472 #interrupt-cells = <0>; 473 ti,sci = <&dmsc>; 474 ti,sci-dev-id = <179>; 475 ti,interrupt-ranges = <0 0 256>; 476 }; 477 478 secure_proxy_main: mailbox@32c00000 { 479 compatible = "ti,am654-secure-proxy"; 480 #mbox-cells = <1>; 481 reg-names = "target_data", "rt", "scfg"; 482 reg = <0x00 0x32c00000 0x00 0x100000>, 483 <0x00 0x32400000 0x00 0x100000>, 484 <0x00 0x32800000 0x00 0x100000>; 485 interrupt-names = "rx_011"; 486 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 487 }; 488 489 hwspinlock: spinlock@30e00000 { 490 compatible = "ti,am654-hwspinlock"; 491 reg = <0x00 0x30e00000 0x00 0x1000>; 492 #hwlock-cells = <1>; 493 }; 494 495 mailbox0_cluster0: mailbox@31f80000 { 496 compatible = "ti,am654-mailbox"; 497 reg = <0x00 0x31f80000 0x00 0x200>; 498 #mbox-cells = <1>; 499 ti,mbox-num-users = <4>; 500 ti,mbox-num-fifos = <16>; 501 interrupt-parent = <&intr_main_navss>; 502 }; 503 504 mailbox0_cluster1: mailbox@31f81000 { 505 compatible = "ti,am654-mailbox"; 506 reg = <0x00 0x31f81000 0x00 0x200>; 507 #mbox-cells = <1>; 508 ti,mbox-num-users = <4>; 509 ti,mbox-num-fifos = <16>; 510 interrupt-parent = <&intr_main_navss>; 511 }; 512 513 mailbox0_cluster2: mailbox@31f82000 { 514 compatible = "ti,am654-mailbox"; 515 reg = <0x00 0x31f82000 0x00 0x200>; 516 #mbox-cells = <1>; 517 ti,mbox-num-users = <4>; 518 ti,mbox-num-fifos = <16>; 519 interrupt-parent = <&intr_main_navss>; 520 }; 521 522 mailbox0_cluster3: mailbox@31f83000 { 523 compatible = "ti,am654-mailbox"; 524 reg = <0x00 0x31f83000 0x00 0x200>; 525 #mbox-cells = <1>; 526 ti,mbox-num-users = <4>; 527 ti,mbox-num-fifos = <16>; 528 interrupt-parent = <&intr_main_navss>; 529 }; 530 531 mailbox0_cluster4: mailbox@31f84000 { 532 compatible = "ti,am654-mailbox"; 533 reg = <0x00 0x31f84000 0x00 0x200>; 534 #mbox-cells = <1>; 535 ti,mbox-num-users = <4>; 536 ti,mbox-num-fifos = <16>; 537 interrupt-parent = <&intr_main_navss>; 538 }; 539 540 mailbox0_cluster5: mailbox@31f85000 { 541 compatible = "ti,am654-mailbox"; 542 reg = <0x00 0x31f85000 0x00 0x200>; 543 #mbox-cells = <1>; 544 ti,mbox-num-users = <4>; 545 ti,mbox-num-fifos = <16>; 546 interrupt-parent = <&intr_main_navss>; 547 }; 548 549 mailbox0_cluster6: mailbox@31f86000 { 550 compatible = "ti,am654-mailbox"; 551 reg = <0x00 0x31f86000 0x00 0x200>; 552 #mbox-cells = <1>; 553 ti,mbox-num-users = <4>; 554 ti,mbox-num-fifos = <16>; 555 interrupt-parent = <&intr_main_navss>; 556 }; 557 558 mailbox0_cluster7: mailbox@31f87000 { 559 compatible = "ti,am654-mailbox"; 560 reg = <0x00 0x31f87000 0x00 0x200>; 561 #mbox-cells = <1>; 562 ti,mbox-num-users = <4>; 563 ti,mbox-num-fifos = <16>; 564 interrupt-parent = <&intr_main_navss>; 565 }; 566 567 mailbox0_cluster8: mailbox@31f88000 { 568 compatible = "ti,am654-mailbox"; 569 reg = <0x00 0x31f88000 0x00 0x200>; 570 #mbox-cells = <1>; 571 ti,mbox-num-users = <4>; 572 ti,mbox-num-fifos = <16>; 573 interrupt-parent = <&intr_main_navss>; 574 }; 575 576 mailbox0_cluster9: mailbox@31f89000 { 577 compatible = "ti,am654-mailbox"; 578 reg = <0x00 0x31f89000 0x00 0x200>; 579 #mbox-cells = <1>; 580 ti,mbox-num-users = <4>; 581 ti,mbox-num-fifos = <16>; 582 interrupt-parent = <&intr_main_navss>; 583 }; 584 585 mailbox0_cluster10: mailbox@31f8a000 { 586 compatible = "ti,am654-mailbox"; 587 reg = <0x00 0x31f8a000 0x00 0x200>; 588 #mbox-cells = <1>; 589 ti,mbox-num-users = <4>; 590 ti,mbox-num-fifos = <16>; 591 interrupt-parent = <&intr_main_navss>; 592 }; 593 594 mailbox0_cluster11: mailbox@31f8b000 { 595 compatible = "ti,am654-mailbox"; 596 reg = <0x00 0x31f8b000 0x00 0x200>; 597 #mbox-cells = <1>; 598 ti,mbox-num-users = <4>; 599 ti,mbox-num-fifos = <16>; 600 interrupt-parent = <&intr_main_navss>; 601 }; 602 603 ringacc: ringacc@3c000000 { 604 compatible = "ti,am654-navss-ringacc"; 605 reg = <0x0 0x3c000000 0x0 0x400000>, 606 <0x0 0x38000000 0x0 0x400000>, 607 <0x0 0x31120000 0x0 0x100>, 608 <0x0 0x33000000 0x0 0x40000>; 609 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 610 ti,num-rings = <818>; 611 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 612 ti,sci = <&dmsc>; 613 ti,sci-dev-id = <187>; 614 msi-parent = <&inta_main_udmass>; 615 }; 616 617 main_udmap: dma-controller@31150000 { 618 compatible = "ti,am654-navss-main-udmap"; 619 reg = <0x0 0x31150000 0x0 0x100>, 620 <0x0 0x34000000 0x0 0x100000>, 621 <0x0 0x35000000 0x0 0x100000>; 622 reg-names = "gcfg", "rchanrt", "tchanrt"; 623 msi-parent = <&inta_main_udmass>; 624 #dma-cells = <1>; 625 626 ti,sci = <&dmsc>; 627 ti,sci-dev-id = <188>; 628 ti,ringacc = <&ringacc>; 629 630 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ 631 <0xd>; /* TX_CHAN */ 632 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ 633 <0xa>; /* RX_CHAN */ 634 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ 635 }; 636 637 cpts@310d0000 { 638 compatible = "ti,am65-cpts"; 639 reg = <0x0 0x310d0000 0x0 0x400>; 640 reg-names = "cpts"; 641 clocks = <&main_cpts_mux>; 642 clock-names = "cpts"; 643 interrupts-extended = <&intr_main_navss 391>; 644 interrupt-names = "cpts"; 645 ti,cpts-periodic-outputs = <6>; 646 ti,cpts-ext-ts-inputs = <8>; 647 648 main_cpts_mux: refclk-mux { 649 #clock-cells = <0>; 650 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, 651 <&k3_clks 118 6>, <&k3_clks 118 3>, 652 <&k3_clks 118 8>, <&k3_clks 118 14>, 653 <&k3_clks 120 3>, <&k3_clks 121 3>; 654 assigned-clocks = <&main_cpts_mux>; 655 assigned-clock-parents = <&k3_clks 118 5>; 656 }; 657 }; 658 }; 659 660 main_gpio0: gpio@600000 { 661 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 662 reg = <0x0 0x600000 0x0 0x100>; 663 gpio-controller; 664 #gpio-cells = <2>; 665 interrupt-parent = <&intr_main_gpio>; 666 interrupts = <192>, <193>, <194>, <195>, <196>, <197>; 667 interrupt-controller; 668 #interrupt-cells = <2>; 669 ti,ngpio = <96>; 670 ti,davinci-gpio-unbanked = <0>; 671 clocks = <&k3_clks 57 0>; 672 clock-names = "gpio"; 673 }; 674 675 main_gpio1: gpio@601000 { 676 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 677 reg = <0x0 0x601000 0x0 0x100>; 678 gpio-controller; 679 #gpio-cells = <2>; 680 interrupt-parent = <&intr_main_gpio>; 681 interrupts = <200>, <201>, <202>, <203>, <204>, <205>; 682 interrupt-controller; 683 #interrupt-cells = <2>; 684 ti,ngpio = <90>; 685 ti,davinci-gpio-unbanked = <0>; 686 clocks = <&k3_clks 58 0>; 687 clock-names = "gpio"; 688 }; 689 690 pcie0_rc: pcie@5500000 { 691 compatible = "ti,am654-pcie-rc"; 692 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; 693 reg-names = "app", "dbics", "config", "atu"; 694 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 695 #address-cells = <3>; 696 #size-cells = <2>; 697 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000 698 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; 699 ti,syscon-pcie-id = <&pcie_devid>; 700 ti,syscon-pcie-mode = <&pcie0_mode>; 701 bus-range = <0x0 0xff>; 702 num-viewport = <16>; 703 max-link-speed = <2>; 704 dma-coherent; 705 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 706 msi-map = <0x0 &gic_its 0x0 0x10000>; 707 device_type = "pci"; 708 }; 709 710 pcie0_ep: pcie-ep@5500000 { 711 compatible = "ti,am654-pcie-ep"; 712 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; 713 reg-names = "app", "dbics", "addr_space", "atu"; 714 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 715 ti,syscon-pcie-mode = <&pcie0_mode>; 716 num-ib-windows = <16>; 717 num-ob-windows = <16>; 718 max-link-speed = <2>; 719 dma-coherent; 720 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 721 }; 722 723 pcie1_rc: pcie@5600000 { 724 compatible = "ti,am654-pcie-rc"; 725 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; 726 reg-names = "app", "dbics", "config", "atu"; 727 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 728 #address-cells = <3>; 729 #size-cells = <2>; 730 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000 731 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; 732 ti,syscon-pcie-id = <&pcie_devid>; 733 ti,syscon-pcie-mode = <&pcie1_mode>; 734 bus-range = <0x0 0xff>; 735 num-viewport = <16>; 736 max-link-speed = <2>; 737 dma-coherent; 738 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 739 msi-map = <0x0 &gic_its 0x10000 0x10000>; 740 device_type = "pci"; 741 }; 742 743 pcie1_ep: pcie-ep@5600000 { 744 compatible = "ti,am654-pcie-ep"; 745 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; 746 reg-names = "app", "dbics", "addr_space", "atu"; 747 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 748 ti,syscon-pcie-mode = <&pcie1_mode>; 749 num-ib-windows = <16>; 750 num-ob-windows = <16>; 751 max-link-speed = <2>; 752 dma-coherent; 753 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 754 }; 755 756 mcasp0: mcasp@2b00000 { 757 compatible = "ti,am33xx-mcasp-audio"; 758 reg = <0x0 0x02b00000 0x0 0x2000>, 759 <0x0 0x02b08000 0x0 0x1000>; 760 reg-names = "mpu","dat"; 761 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 763 interrupt-names = "tx", "rx"; 764 765 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 766 dma-names = "tx", "rx"; 767 768 clocks = <&k3_clks 104 0>; 769 clock-names = "fck"; 770 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 771 }; 772 773 mcasp1: mcasp@2b10000 { 774 compatible = "ti,am33xx-mcasp-audio"; 775 reg = <0x0 0x02b10000 0x0 0x2000>, 776 <0x0 0x02b18000 0x0 0x1000>; 777 reg-names = "mpu","dat"; 778 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 780 interrupt-names = "tx", "rx"; 781 782 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 783 dma-names = "tx", "rx"; 784 785 clocks = <&k3_clks 105 0>; 786 clock-names = "fck"; 787 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 788 }; 789 790 mcasp2: mcasp@2b20000 { 791 compatible = "ti,am33xx-mcasp-audio"; 792 reg = <0x0 0x02b20000 0x0 0x2000>, 793 <0x0 0x02b28000 0x0 0x1000>; 794 reg-names = "mpu","dat"; 795 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 797 interrupt-names = "tx", "rx"; 798 799 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 800 dma-names = "tx", "rx"; 801 802 clocks = <&k3_clks 106 0>; 803 clock-names = "fck"; 804 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 805 }; 806 807 cal: cal@6f03000 { 808 compatible = "ti,am654-cal"; 809 reg = <0x0 0x06f03000 0x0 0x400>, 810 <0x0 0x06f03800 0x0 0x40>; 811 reg-names = "cal_top", 812 "cal_rx_core0"; 813 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 814 ti,camerrx-control = <&scm_conf 0x40c0>; 815 clock-names = "fck"; 816 clocks = <&k3_clks 2 0>; 817 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>; 818 819 ports { 820 #address-cells = <1>; 821 #size-cells = <0>; 822 823 csi2_0: port@0 { 824 reg = <0>; 825 }; 826 }; 827 }; 828 829 dss: dss@4a00000 { 830 compatible = "ti,am65x-dss"; 831 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ 832 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ 833 <0x0 0x04a06000 0x0 0x1000>, /* vid */ 834 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ 835 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ 836 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ 837 <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ 838 reg-names = "common", "vidl1", "vid", 839 "ovr1", "ovr2", "vp1", "vp2"; 840 841 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; 842 843 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 844 845 clocks = <&k3_clks 67 1>, 846 <&k3_clks 216 1>, 847 <&k3_clks 67 2>; 848 clock-names = "fck", "vp1", "vp2"; 849 850 /* 851 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via 852 * DIV1. See "Figure 12-3365. DSS Integration" 853 * in AM65x TRM for details. 854 */ 855 assigned-clocks = <&k3_clks 67 2>; 856 assigned-clock-parents = <&k3_clks 67 5>; 857 858 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 859 860 dma-coherent; 861 862 dss_ports: ports { 863 #address-cells = <1>; 864 #size-cells = <0>; 865 }; 866 }; 867 868 ehrpwm0: pwm@3000000 { 869 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 870 #pwm-cells = <3>; 871 reg = <0x0 0x3000000 0x0 0x100>; 872 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 873 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; 874 clock-names = "tbclk", "fck"; 875 }; 876 877 ehrpwm1: pwm@3010000 { 878 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 879 #pwm-cells = <3>; 880 reg = <0x0 0x3010000 0x0 0x100>; 881 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 882 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; 883 clock-names = "tbclk", "fck"; 884 }; 885 886 ehrpwm2: pwm@3020000 { 887 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 888 #pwm-cells = <3>; 889 reg = <0x0 0x3020000 0x0 0x100>; 890 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 891 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; 892 clock-names = "tbclk", "fck"; 893 }; 894 895 ehrpwm3: pwm@3030000 { 896 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 897 #pwm-cells = <3>; 898 reg = <0x0 0x3030000 0x0 0x100>; 899 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 900 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; 901 clock-names = "tbclk", "fck"; 902 }; 903 904 ehrpwm4: pwm@3040000 { 905 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 906 #pwm-cells = <3>; 907 reg = <0x0 0x3040000 0x0 0x100>; 908 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 909 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; 910 clock-names = "tbclk", "fck"; 911 }; 912 913 ehrpwm5: pwm@3050000 { 914 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 915 #pwm-cells = <3>; 916 reg = <0x0 0x3050000 0x0 0x100>; 917 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 918 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; 919 clock-names = "tbclk", "fck"; 920 }; 921 922 icssg0: icssg@b000000 { 923 compatible = "ti,am654-icssg"; 924 reg = <0x00 0xb000000 0x00 0x80000>; 925 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 926 #address-cells = <1>; 927 #size-cells = <1>; 928 ranges = <0x0 0x00 0xb000000 0x80000>; 929 930 icssg0_mem: memories@0 { 931 reg = <0x0 0x2000>, 932 <0x2000 0x2000>, 933 <0x10000 0x10000>; 934 reg-names = "dram0", "dram1", 935 "shrdram2"; 936 }; 937 938 icssg0_cfg: cfg@26000 { 939 compatible = "ti,pruss-cfg", "syscon"; 940 reg = <0x26000 0x200>; 941 #address-cells = <1>; 942 #size-cells = <1>; 943 ranges = <0x0 0x26000 0x2000>; 944 945 clocks { 946 #address-cells = <1>; 947 #size-cells = <0>; 948 949 icssg0_coreclk_mux: coreclk-mux@3c { 950 reg = <0x3c>; 951 #clock-cells = <0>; 952 clocks = <&k3_clks 62 19>, /* icssg0_core_clk */ 953 <&k3_clks 62 3>; /* icssg0_iclk */ 954 assigned-clocks = <&icssg0_coreclk_mux>; 955 assigned-clock-parents = <&k3_clks 62 3>; 956 }; 957 958 icssg0_iepclk_mux: iepclk-mux@30 { 959 reg = <0x30>; 960 #clock-cells = <0>; 961 clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */ 962 <&icssg0_coreclk_mux>; /* core_clk */ 963 assigned-clocks = <&icssg0_iepclk_mux>; 964 assigned-clock-parents = <&icssg0_coreclk_mux>; 965 }; 966 }; 967 }; 968 969 icssg0_mii_rt: mii-rt@32000 { 970 compatible = "ti,pruss-mii", "syscon"; 971 reg = <0x32000 0x100>; 972 }; 973 974 icssg0_mii_g_rt: mii-g-rt@33000 { 975 compatible = "ti,pruss-mii-g", "syscon"; 976 reg = <0x33000 0x1000>; 977 }; 978 979 icssg0_intc: interrupt-controller@20000 { 980 compatible = "ti,icssg-intc"; 981 reg = <0x20000 0x2000>; 982 interrupt-controller; 983 #interrupt-cells = <3>; 984 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 992 interrupt-names = "host_intr0", "host_intr1", 993 "host_intr2", "host_intr3", 994 "host_intr4", "host_intr5", 995 "host_intr6", "host_intr7"; 996 }; 997 998 pru0_0: pru@34000 { 999 compatible = "ti,am654-pru"; 1000 reg = <0x34000 0x4000>, 1001 <0x22000 0x100>, 1002 <0x22400 0x100>; 1003 reg-names = "iram", "control", "debug"; 1004 firmware-name = "am65x-pru0_0-fw"; 1005 }; 1006 1007 rtu0_0: rtu@4000 { 1008 compatible = "ti,am654-rtu"; 1009 reg = <0x4000 0x2000>, 1010 <0x23000 0x100>, 1011 <0x23400 0x100>; 1012 reg-names = "iram", "control", "debug"; 1013 firmware-name = "am65x-rtu0_0-fw"; 1014 }; 1015 1016 tx_pru0_0: txpru@a000 { 1017 compatible = "ti,am654-tx-pru"; 1018 reg = <0xa000 0x1800>, 1019 <0x25000 0x100>, 1020 <0x25400 0x100>; 1021 reg-names = "iram", "control", "debug"; 1022 firmware-name = "am65x-txpru0_0-fw"; 1023 }; 1024 1025 pru0_1: pru@38000 { 1026 compatible = "ti,am654-pru"; 1027 reg = <0x38000 0x4000>, 1028 <0x24000 0x100>, 1029 <0x24400 0x100>; 1030 reg-names = "iram", "control", "debug"; 1031 firmware-name = "am65x-pru0_1-fw"; 1032 }; 1033 1034 rtu0_1: rtu@6000 { 1035 compatible = "ti,am654-rtu"; 1036 reg = <0x6000 0x2000>, 1037 <0x23800 0x100>, 1038 <0x23c00 0x100>; 1039 reg-names = "iram", "control", "debug"; 1040 firmware-name = "am65x-rtu0_1-fw"; 1041 }; 1042 1043 tx_pru0_1: txpru@c000 { 1044 compatible = "ti,am654-tx-pru"; 1045 reg = <0xc000 0x1800>, 1046 <0x25800 0x100>, 1047 <0x25c00 0x100>; 1048 reg-names = "iram", "control", "debug"; 1049 firmware-name = "am65x-txpru0_1-fw"; 1050 }; 1051 1052 icssg0_mdio: mdio@32400 { 1053 compatible = "ti,davinci_mdio"; 1054 reg = <0x32400 0x100>; 1055 clocks = <&k3_clks 62 3>; 1056 clock-names = "fck"; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 bus_freq = <1000000>; 1060 }; 1061 }; 1062 1063 icssg1: icssg@b100000 { 1064 compatible = "ti,am654-icssg"; 1065 reg = <0x00 0xb100000 0x00 0x80000>; 1066 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1067 #address-cells = <1>; 1068 #size-cells = <1>; 1069 ranges = <0x0 0x00 0xb100000 0x80000>; 1070 1071 icssg1_mem: memories@0 { 1072 reg = <0x0 0x2000>, 1073 <0x2000 0x2000>, 1074 <0x10000 0x10000>; 1075 reg-names = "dram0", "dram1", 1076 "shrdram2"; 1077 }; 1078 1079 icssg1_cfg: cfg@26000 { 1080 compatible = "ti,pruss-cfg", "syscon"; 1081 reg = <0x26000 0x200>; 1082 #address-cells = <1>; 1083 #size-cells = <1>; 1084 ranges = <0x0 0x26000 0x2000>; 1085 1086 clocks { 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 1090 icssg1_coreclk_mux: coreclk-mux@3c { 1091 reg = <0x3c>; 1092 #clock-cells = <0>; 1093 clocks = <&k3_clks 63 19>, /* icssg1_core_clk */ 1094 <&k3_clks 63 3>; /* icssg1_iclk */ 1095 assigned-clocks = <&icssg1_coreclk_mux>; 1096 assigned-clock-parents = <&k3_clks 63 3>; 1097 }; 1098 1099 icssg1_iepclk_mux: iepclk-mux@30 { 1100 reg = <0x30>; 1101 #clock-cells = <0>; 1102 clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */ 1103 <&icssg1_coreclk_mux>; /* core_clk */ 1104 assigned-clocks = <&icssg1_iepclk_mux>; 1105 assigned-clock-parents = <&icssg1_coreclk_mux>; 1106 }; 1107 }; 1108 }; 1109 1110 icssg1_mii_rt: mii-rt@32000 { 1111 compatible = "ti,pruss-mii", "syscon"; 1112 reg = <0x32000 0x100>; 1113 }; 1114 1115 icssg1_mii_g_rt: mii-g-rt@33000 { 1116 compatible = "ti,pruss-mii-g", "syscon"; 1117 reg = <0x33000 0x1000>; 1118 }; 1119 1120 icssg1_intc: interrupt-controller@20000 { 1121 compatible = "ti,icssg-intc"; 1122 reg = <0x20000 0x2000>; 1123 interrupt-controller; 1124 #interrupt-cells = <3>; 1125 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1133 interrupt-names = "host_intr0", "host_intr1", 1134 "host_intr2", "host_intr3", 1135 "host_intr4", "host_intr5", 1136 "host_intr6", "host_intr7"; 1137 }; 1138 1139 pru1_0: pru@34000 { 1140 compatible = "ti,am654-pru"; 1141 reg = <0x34000 0x4000>, 1142 <0x22000 0x100>, 1143 <0x22400 0x100>; 1144 reg-names = "iram", "control", "debug"; 1145 firmware-name = "am65x-pru1_0-fw"; 1146 }; 1147 1148 rtu1_0: rtu@4000 { 1149 compatible = "ti,am654-rtu"; 1150 reg = <0x4000 0x2000>, 1151 <0x23000 0x100>, 1152 <0x23400 0x100>; 1153 reg-names = "iram", "control", "debug"; 1154 firmware-name = "am65x-rtu1_0-fw"; 1155 }; 1156 1157 tx_pru1_0: txpru@a000 { 1158 compatible = "ti,am654-tx-pru"; 1159 reg = <0xa000 0x1800>, 1160 <0x25000 0x100>, 1161 <0x25400 0x100>; 1162 reg-names = "iram", "control", "debug"; 1163 firmware-name = "am65x-txpru1_0-fw"; 1164 }; 1165 1166 pru1_1: pru@38000 { 1167 compatible = "ti,am654-pru"; 1168 reg = <0x38000 0x4000>, 1169 <0x24000 0x100>, 1170 <0x24400 0x100>; 1171 reg-names = "iram", "control", "debug"; 1172 firmware-name = "am65x-pru1_1-fw"; 1173 }; 1174 1175 rtu1_1: rtu@6000 { 1176 compatible = "ti,am654-rtu"; 1177 reg = <0x6000 0x2000>, 1178 <0x23800 0x100>, 1179 <0x23c00 0x100>; 1180 reg-names = "iram", "control", "debug"; 1181 firmware-name = "am65x-rtu1_1-fw"; 1182 }; 1183 1184 tx_pru1_1: txpru@c000 { 1185 compatible = "ti,am654-tx-pru"; 1186 reg = <0xc000 0x1800>, 1187 <0x25800 0x100>, 1188 <0x25c00 0x100>; 1189 reg-names = "iram", "control", "debug"; 1190 firmware-name = "am65x-txpru1_1-fw"; 1191 }; 1192 1193 icssg1_mdio: mdio@32400 { 1194 compatible = "ti,davinci_mdio"; 1195 reg = <0x32400 0x100>; 1196 clocks = <&k3_clks 63 3>; 1197 clock-names = "fck"; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 bus_freq = <1000000>; 1201 }; 1202 }; 1203 1204 icssg2: icssg@b200000 { 1205 compatible = "ti,am654-icssg"; 1206 reg = <0x00 0xb200000 0x00 0x80000>; 1207 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1208 #address-cells = <1>; 1209 #size-cells = <1>; 1210 ranges = <0x0 0x00 0xb200000 0x80000>; 1211 1212 icssg2_mem: memories@0 { 1213 reg = <0x0 0x2000>, 1214 <0x2000 0x2000>, 1215 <0x10000 0x10000>; 1216 reg-names = "dram0", "dram1", 1217 "shrdram2"; 1218 }; 1219 1220 icssg2_cfg: cfg@26000 { 1221 compatible = "ti,pruss-cfg", "syscon"; 1222 reg = <0x26000 0x200>; 1223 #address-cells = <1>; 1224 #size-cells = <1>; 1225 ranges = <0x0 0x26000 0x2000>; 1226 1227 clocks { 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 1231 icssg2_coreclk_mux: coreclk-mux@3c { 1232 reg = <0x3c>; 1233 #clock-cells = <0>; 1234 clocks = <&k3_clks 64 19>, /* icssg1_core_clk */ 1235 <&k3_clks 64 3>; /* icssg1_iclk */ 1236 assigned-clocks = <&icssg2_coreclk_mux>; 1237 assigned-clock-parents = <&k3_clks 64 3>; 1238 }; 1239 1240 icssg2_iepclk_mux: iepclk-mux@30 { 1241 reg = <0x30>; 1242 #clock-cells = <0>; 1243 clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */ 1244 <&icssg2_coreclk_mux>; /* core_clk */ 1245 assigned-clocks = <&icssg2_iepclk_mux>; 1246 assigned-clock-parents = <&icssg2_coreclk_mux>; 1247 }; 1248 }; 1249 }; 1250 1251 icssg2_mii_rt: mii-rt@32000 { 1252 compatible = "ti,pruss-mii", "syscon"; 1253 reg = <0x32000 0x100>; 1254 }; 1255 1256 icssg2_mii_g_rt: mii-g-rt@33000 { 1257 compatible = "ti,pruss-mii-g", "syscon"; 1258 reg = <0x33000 0x1000>; 1259 }; 1260 1261 icssg2_intc: interrupt-controller@20000 { 1262 compatible = "ti,icssg-intc"; 1263 reg = <0x20000 0x2000>; 1264 interrupt-controller; 1265 #interrupt-cells = <3>; 1266 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 1274 interrupt-names = "host_intr0", "host_intr1", 1275 "host_intr2", "host_intr3", 1276 "host_intr4", "host_intr5", 1277 "host_intr6", "host_intr7"; 1278 }; 1279 1280 pru2_0: pru@34000 { 1281 compatible = "ti,am654-pru"; 1282 reg = <0x34000 0x4000>, 1283 <0x22000 0x100>, 1284 <0x22400 0x100>; 1285 reg-names = "iram", "control", "debug"; 1286 firmware-name = "am65x-pru2_0-fw"; 1287 }; 1288 1289 rtu2_0: rtu@4000 { 1290 compatible = "ti,am654-rtu"; 1291 reg = <0x4000 0x2000>, 1292 <0x23000 0x100>, 1293 <0x23400 0x100>; 1294 reg-names = "iram", "control", "debug"; 1295 firmware-name = "am65x-rtu2_0-fw"; 1296 }; 1297 1298 tx_pru2_0: txpru@a000 { 1299 compatible = "ti,am654-tx-pru"; 1300 reg = <0xa000 0x1800>, 1301 <0x25000 0x100>, 1302 <0x25400 0x100>; 1303 reg-names = "iram", "control", "debug"; 1304 firmware-name = "am65x-txpru2_0-fw"; 1305 }; 1306 1307 pru2_1: pru@38000 { 1308 compatible = "ti,am654-pru"; 1309 reg = <0x38000 0x4000>, 1310 <0x24000 0x100>, 1311 <0x24400 0x100>; 1312 reg-names = "iram", "control", "debug"; 1313 firmware-name = "am65x-pru2_1-fw"; 1314 }; 1315 1316 rtu2_1: rtu@6000 { 1317 compatible = "ti,am654-rtu"; 1318 reg = <0x6000 0x2000>, 1319 <0x23800 0x100>, 1320 <0x23c00 0x100>; 1321 reg-names = "iram", "control", "debug"; 1322 firmware-name = "am65x-rtu2_1-fw"; 1323 }; 1324 1325 tx_pru2_1: txpru@c000 { 1326 compatible = "ti,am654-tx-pru"; 1327 reg = <0xc000 0x1800>, 1328 <0x25800 0x100>, 1329 <0x25c00 0x100>; 1330 reg-names = "iram", "control", "debug"; 1331 firmware-name = "am65x-txpru2_1-fw"; 1332 }; 1333 1334 icssg2_mdio: mdio@32400 { 1335 compatible = "ti,davinci_mdio"; 1336 reg = <0x32400 0x100>; 1337 clocks = <&k3_clks 64 3>; 1338 clock-names = "fck"; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 bus_freq = <1000000>; 1342 }; 1343 }; 1344}; 1345