1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/ { 9 serdes_refclk: serdes-refclk { 10 #clock-cells = <0>; 11 compatible = "fixed-clock"; 12 }; 13}; 14 15&cbass_main { 16 msmc_ram: sram@70000000 { 17 compatible = "mmio-sram"; 18 reg = <0x00 0x70000000 0x00 0x100000>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x00 0x00 0x70000000 0x100000>; 22 23 atf-sram@0 { 24 reg = <0x00 0x20000>; 25 }; 26 }; 27 28 scm_conf: scm-conf@100000 { 29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 30 reg = <0x00 0x00100000 0x00 0x1c000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x00 0x00 0x00100000 0x1c000>; 34 35 serdes_ln_ctrl: mux-controller@4080 { 36 compatible = "mmio-mux"; 37 #mux-control-cells = <1>; 38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 40 }; 41 42 usb_serdes_mux: mux-controller@4000 { 43 compatible = "mmio-mux"; 44 #mux-control-cells = <1>; 45 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 46 }; 47 }; 48 49 gic500: interrupt-controller@1800000 { 50 compatible = "arm,gic-v3"; 51 #address-cells = <2>; 52 #size-cells = <2>; 53 ranges; 54 #interrupt-cells = <3>; 55 interrupt-controller; 56 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 57 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 58 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 59 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 60 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 61 62 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 63 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 64 65 gic_its: msi-controller@1820000 { 66 compatible = "arm,gic-v3-its"; 67 reg = <0x00 0x01820000 0x00 0x10000>; 68 socionext,synquacer-pre-its = <0x1000000 0x400000>; 69 msi-controller; 70 #msi-cells = <1>; 71 }; 72 }; 73 74 main_gpio_intr: interrupt-controller@a00000 { 75 compatible = "ti,sci-intr"; 76 reg = <0x00 0x00a00000 0x00 0x800>; 77 ti,intr-trigger-type = <1>; 78 interrupt-controller; 79 interrupt-parent = <&gic500>; 80 #interrupt-cells = <1>; 81 ti,sci = <&dmsc>; 82 ti,sci-dev-id = <131>; 83 ti,interrupt-ranges = <8 392 56>; 84 }; 85 86 main_navss: bus@30000000 { 87 compatible = "simple-mfd"; 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 91 ti,sci-dev-id = <199>; 92 dma-coherent; 93 dma-ranges; 94 95 main_navss_intr: interrupt-controller@310e0000 { 96 compatible = "ti,sci-intr"; 97 reg = <0x00 0x310e0000 0x00 0x4000>; 98 ti,intr-trigger-type = <4>; 99 interrupt-controller; 100 interrupt-parent = <&gic500>; 101 #interrupt-cells = <1>; 102 ti,sci = <&dmsc>; 103 ti,sci-dev-id = <213>; 104 ti,interrupt-ranges = <0 64 64>, 105 <64 448 64>, 106 <128 672 64>; 107 }; 108 109 main_udmass_inta: msi-controller@33d00000 { 110 compatible = "ti,sci-inta"; 111 reg = <0x00 0x33d00000 0x00 0x100000>; 112 interrupt-controller; 113 #interrupt-cells = <0>; 114 interrupt-parent = <&main_navss_intr>; 115 msi-controller; 116 ti,sci = <&dmsc>; 117 ti,sci-dev-id = <209>; 118 ti,interrupt-ranges = <0 0 256>; 119 }; 120 121 secure_proxy_main: mailbox@32c00000 { 122 compatible = "ti,am654-secure-proxy"; 123 #mbox-cells = <1>; 124 reg-names = "target_data", "rt", "scfg"; 125 reg = <0x00 0x32c00000 0x00 0x100000>, 126 <0x00 0x32400000 0x00 0x100000>, 127 <0x00 0x32800000 0x00 0x100000>; 128 interrupt-names = "rx_011"; 129 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 130 }; 131 132 hwspinlock: spinlock@30e00000 { 133 compatible = "ti,am654-hwspinlock"; 134 reg = <0x00 0x30e00000 0x00 0x1000>; 135 #hwlock-cells = <1>; 136 }; 137 138 mailbox0_cluster0: mailbox@31f80000 { 139 compatible = "ti,am654-mailbox"; 140 reg = <0x00 0x31f80000 0x00 0x200>; 141 #mbox-cells = <1>; 142 ti,mbox-num-users = <4>; 143 ti,mbox-num-fifos = <16>; 144 interrupt-parent = <&main_navss_intr>; 145 }; 146 147 mailbox0_cluster1: mailbox@31f81000 { 148 compatible = "ti,am654-mailbox"; 149 reg = <0x00 0x31f81000 0x00 0x200>; 150 #mbox-cells = <1>; 151 ti,mbox-num-users = <4>; 152 ti,mbox-num-fifos = <16>; 153 interrupt-parent = <&main_navss_intr>; 154 }; 155 156 mailbox0_cluster2: mailbox@31f82000 { 157 compatible = "ti,am654-mailbox"; 158 reg = <0x00 0x31f82000 0x00 0x200>; 159 #mbox-cells = <1>; 160 ti,mbox-num-users = <4>; 161 ti,mbox-num-fifos = <16>; 162 interrupt-parent = <&main_navss_intr>; 163 }; 164 165 mailbox0_cluster3: mailbox@31f83000 { 166 compatible = "ti,am654-mailbox"; 167 reg = <0x00 0x31f83000 0x00 0x200>; 168 #mbox-cells = <1>; 169 ti,mbox-num-users = <4>; 170 ti,mbox-num-fifos = <16>; 171 interrupt-parent = <&main_navss_intr>; 172 }; 173 174 mailbox0_cluster4: mailbox@31f84000 { 175 compatible = "ti,am654-mailbox"; 176 reg = <0x00 0x31f84000 0x00 0x200>; 177 #mbox-cells = <1>; 178 ti,mbox-num-users = <4>; 179 ti,mbox-num-fifos = <16>; 180 interrupt-parent = <&main_navss_intr>; 181 }; 182 183 mailbox0_cluster5: mailbox@31f85000 { 184 compatible = "ti,am654-mailbox"; 185 reg = <0x00 0x31f85000 0x00 0x200>; 186 #mbox-cells = <1>; 187 ti,mbox-num-users = <4>; 188 ti,mbox-num-fifos = <16>; 189 interrupt-parent = <&main_navss_intr>; 190 }; 191 192 mailbox0_cluster6: mailbox@31f86000 { 193 compatible = "ti,am654-mailbox"; 194 reg = <0x00 0x31f86000 0x00 0x200>; 195 #mbox-cells = <1>; 196 ti,mbox-num-users = <4>; 197 ti,mbox-num-fifos = <16>; 198 interrupt-parent = <&main_navss_intr>; 199 }; 200 201 mailbox0_cluster7: mailbox@31f87000 { 202 compatible = "ti,am654-mailbox"; 203 reg = <0x00 0x31f87000 0x00 0x200>; 204 #mbox-cells = <1>; 205 ti,mbox-num-users = <4>; 206 ti,mbox-num-fifos = <16>; 207 interrupt-parent = <&main_navss_intr>; 208 }; 209 210 mailbox0_cluster8: mailbox@31f88000 { 211 compatible = "ti,am654-mailbox"; 212 reg = <0x00 0x31f88000 0x00 0x200>; 213 #mbox-cells = <1>; 214 ti,mbox-num-users = <4>; 215 ti,mbox-num-fifos = <16>; 216 interrupt-parent = <&main_navss_intr>; 217 }; 218 219 mailbox0_cluster9: mailbox@31f89000 { 220 compatible = "ti,am654-mailbox"; 221 reg = <0x00 0x31f89000 0x00 0x200>; 222 #mbox-cells = <1>; 223 ti,mbox-num-users = <4>; 224 ti,mbox-num-fifos = <16>; 225 interrupt-parent = <&main_navss_intr>; 226 }; 227 228 mailbox0_cluster10: mailbox@31f8a000 { 229 compatible = "ti,am654-mailbox"; 230 reg = <0x00 0x31f8a000 0x00 0x200>; 231 #mbox-cells = <1>; 232 ti,mbox-num-users = <4>; 233 ti,mbox-num-fifos = <16>; 234 interrupt-parent = <&main_navss_intr>; 235 }; 236 237 mailbox0_cluster11: mailbox@31f8b000 { 238 compatible = "ti,am654-mailbox"; 239 reg = <0x00 0x31f8b000 0x00 0x200>; 240 #mbox-cells = <1>; 241 ti,mbox-num-users = <4>; 242 ti,mbox-num-fifos = <16>; 243 interrupt-parent = <&main_navss_intr>; 244 }; 245 246 main_ringacc: ringacc@3c000000 { 247 compatible = "ti,am654-navss-ringacc"; 248 reg = <0x00 0x3c000000 0x00 0x400000>, 249 <0x00 0x38000000 0x00 0x400000>, 250 <0x00 0x31120000 0x00 0x100>, 251 <0x00 0x33000000 0x00 0x40000>; 252 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 253 ti,num-rings = <1024>; 254 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 255 ti,sci = <&dmsc>; 256 ti,sci-dev-id = <211>; 257 msi-parent = <&main_udmass_inta>; 258 }; 259 260 main_udmap: dma-controller@31150000 { 261 compatible = "ti,j721e-navss-main-udmap"; 262 reg = <0x00 0x31150000 0x00 0x100>, 263 <0x00 0x34000000 0x00 0x100000>, 264 <0x00 0x35000000 0x00 0x100000>; 265 reg-names = "gcfg", "rchanrt", "tchanrt"; 266 msi-parent = <&main_udmass_inta>; 267 #dma-cells = <1>; 268 269 ti,sci = <&dmsc>; 270 ti,sci-dev-id = <212>; 271 ti,ringacc = <&main_ringacc>; 272 273 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 274 <0x0f>, /* TX_HCHAN */ 275 <0x10>; /* TX_UHCHAN */ 276 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 277 <0x0b>, /* RX_HCHAN */ 278 <0x0c>; /* RX_UHCHAN */ 279 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 280 }; 281 282 cpts@310d0000 { 283 compatible = "ti,j721e-cpts"; 284 reg = <0x00 0x310d0000 0x00 0x400>; 285 reg-names = "cpts"; 286 clocks = <&k3_clks 201 1>; 287 clock-names = "cpts"; 288 interrupts-extended = <&main_navss_intr 391>; 289 interrupt-names = "cpts"; 290 ti,cpts-periodic-outputs = <6>; 291 ti,cpts-ext-ts-inputs = <8>; 292 }; 293 }; 294 295 main_pmx0: pinctrl@11c000 { 296 compatible = "pinctrl-single"; 297 /* Proxy 0 addressing */ 298 reg = <0x00 0x11c000 0x00 0x10c>; 299 #pinctrl-cells = <1>; 300 pinctrl-single,register-width = <32>; 301 pinctrl-single,function-mask = <0xffffffff>; 302 }; 303 304 main_pmx1: pinctrl@11c11c { 305 compatible = "pinctrl-single"; 306 /* Proxy 0 addressing */ 307 reg = <0x00 0x11c11c 0x00 0xc>; 308 #pinctrl-cells = <1>; 309 pinctrl-single,register-width = <32>; 310 pinctrl-single,function-mask = <0xffffffff>; 311 }; 312 313 main_uart0: serial@2800000 { 314 compatible = "ti,j721e-uart", "ti,am654-uart"; 315 reg = <0x00 0x02800000 0x00 0x100>; 316 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 317 clock-frequency = <48000000>; 318 current-speed = <115200>; 319 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 320 clocks = <&k3_clks 146 2>; 321 clock-names = "fclk"; 322 }; 323 324 main_uart1: serial@2810000 { 325 compatible = "ti,j721e-uart", "ti,am654-uart"; 326 reg = <0x00 0x02810000 0x00 0x100>; 327 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 328 clock-frequency = <48000000>; 329 current-speed = <115200>; 330 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 331 clocks = <&k3_clks 278 2>; 332 clock-names = "fclk"; 333 }; 334 335 main_uart2: serial@2820000 { 336 compatible = "ti,j721e-uart", "ti,am654-uart"; 337 reg = <0x00 0x02820000 0x00 0x100>; 338 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 339 clock-frequency = <48000000>; 340 current-speed = <115200>; 341 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 342 clocks = <&k3_clks 279 2>; 343 clock-names = "fclk"; 344 }; 345 346 main_uart3: serial@2830000 { 347 compatible = "ti,j721e-uart", "ti,am654-uart"; 348 reg = <0x00 0x02830000 0x00 0x100>; 349 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 350 clock-frequency = <48000000>; 351 current-speed = <115200>; 352 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 353 clocks = <&k3_clks 280 2>; 354 clock-names = "fclk"; 355 }; 356 357 main_uart4: serial@2840000 { 358 compatible = "ti,j721e-uart", "ti,am654-uart"; 359 reg = <0x00 0x02840000 0x00 0x100>; 360 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 361 clock-frequency = <48000000>; 362 current-speed = <115200>; 363 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 364 clocks = <&k3_clks 281 2>; 365 clock-names = "fclk"; 366 }; 367 368 main_uart5: serial@2850000 { 369 compatible = "ti,j721e-uart", "ti,am654-uart"; 370 reg = <0x00 0x02850000 0x00 0x100>; 371 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 372 clock-frequency = <48000000>; 373 current-speed = <115200>; 374 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 375 clocks = <&k3_clks 282 2>; 376 clock-names = "fclk"; 377 }; 378 379 main_uart6: serial@2860000 { 380 compatible = "ti,j721e-uart", "ti,am654-uart"; 381 reg = <0x00 0x02860000 0x00 0x100>; 382 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 383 clock-frequency = <48000000>; 384 current-speed = <115200>; 385 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 386 clocks = <&k3_clks 283 2>; 387 clock-names = "fclk"; 388 }; 389 390 main_uart7: serial@2870000 { 391 compatible = "ti,j721e-uart", "ti,am654-uart"; 392 reg = <0x00 0x02870000 0x00 0x100>; 393 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 394 clock-frequency = <48000000>; 395 current-speed = <115200>; 396 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 397 clocks = <&k3_clks 284 2>; 398 clock-names = "fclk"; 399 }; 400 401 main_uart8: serial@2880000 { 402 compatible = "ti,j721e-uart", "ti,am654-uart"; 403 reg = <0x00 0x02880000 0x00 0x100>; 404 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 405 clock-frequency = <48000000>; 406 current-speed = <115200>; 407 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 408 clocks = <&k3_clks 285 2>; 409 clock-names = "fclk"; 410 }; 411 412 main_uart9: serial@2890000 { 413 compatible = "ti,j721e-uart", "ti,am654-uart"; 414 reg = <0x00 0x02890000 0x00 0x100>; 415 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 416 clock-frequency = <48000000>; 417 current-speed = <115200>; 418 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 419 clocks = <&k3_clks 286 2>; 420 clock-names = "fclk"; 421 }; 422 423 main_i2c0: i2c@2000000 { 424 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 425 reg = <0x00 0x2000000 0x00 0x100>; 426 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 clock-names = "fck"; 430 clocks = <&k3_clks 187 1>; 431 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 432 }; 433 434 main_i2c1: i2c@2010000 { 435 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 436 reg = <0x00 0x2010000 0x00 0x100>; 437 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 clock-names = "fck"; 441 clocks = <&k3_clks 188 1>; 442 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 443 }; 444 445 main_i2c2: i2c@2020000 { 446 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 447 reg = <0x00 0x2020000 0x00 0x100>; 448 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 clock-names = "fck"; 452 clocks = <&k3_clks 189 1>; 453 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 454 }; 455 456 main_i2c3: i2c@2030000 { 457 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 458 reg = <0x00 0x2030000 0x00 0x100>; 459 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 clock-names = "fck"; 463 clocks = <&k3_clks 190 1>; 464 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 465 }; 466 467 main_i2c4: i2c@2040000 { 468 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 469 reg = <0x00 0x2040000 0x00 0x100>; 470 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 clock-names = "fck"; 474 clocks = <&k3_clks 191 1>; 475 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 476 }; 477 478 main_i2c5: i2c@2050000 { 479 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 480 reg = <0x00 0x2050000 0x00 0x100>; 481 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 clock-names = "fck"; 485 clocks = <&k3_clks 192 1>; 486 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 487 }; 488 489 main_i2c6: i2c@2060000 { 490 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 491 reg = <0x00 0x2060000 0x00 0x100>; 492 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 clock-names = "fck"; 496 clocks = <&k3_clks 193 1>; 497 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 498 }; 499 500 main_sdhci0: mmc@4f80000 { 501 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 502 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 503 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 504 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 505 clock-names = "clk_ahb", "clk_xin"; 506 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; 507 ti,otap-del-sel-legacy = <0x0>; 508 ti,otap-del-sel-mmc-hs = <0x0>; 509 ti,otap-del-sel-ddr52 = <0x6>; 510 ti,otap-del-sel-hs200 = <0x8>; 511 ti,otap-del-sel-hs400 = <0x5>; 512 ti,itap-del-sel-legacy = <0x10>; 513 ti,itap-del-sel-mmc-hs = <0xa>; 514 ti,strobe-sel = <0x77>; 515 ti,clkbuf-sel = <0x7>; 516 ti,trm-icp = <0x8>; 517 bus-width = <8>; 518 mmc-ddr-1_8v; 519 mmc-hs200-1_8v; 520 mmc-hs400-1_8v; 521 dma-coherent; 522 }; 523 524 main_sdhci1: mmc@4fb0000 { 525 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 526 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 527 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 528 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 529 clock-names = "clk_ahb", "clk_xin"; 530 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; 531 ti,otap-del-sel-legacy = <0x0>; 532 ti,otap-del-sel-sd-hs = <0x0>; 533 ti,otap-del-sel-sdr12 = <0xf>; 534 ti,otap-del-sel-sdr25 = <0xf>; 535 ti,otap-del-sel-sdr50 = <0xc>; 536 ti,otap-del-sel-sdr104 = <0x5>; 537 ti,otap-del-sel-ddr50 = <0xc>; 538 ti,itap-del-sel-legacy = <0x0>; 539 ti,itap-del-sel-sd-hs = <0x0>; 540 ti,itap-del-sel-sdr12 = <0x0>; 541 ti,itap-del-sel-sdr25 = <0x0>; 542 ti,clkbuf-sel = <0x7>; 543 ti,trm-icp = <0x8>; 544 dma-coherent; 545 }; 546 547 serdes_wiz0: wiz@5060000 { 548 compatible = "ti,j721e-wiz-10g"; 549 #address-cells = <1>; 550 #size-cells = <1>; 551 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 552 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; 553 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 554 num-lanes = <4>; 555 #reset-cells = <1>; 556 ranges = <0x5060000 0x0 0x5060000 0x10000>; 557 558 assigned-clocks = <&k3_clks 292 85>; 559 assigned-clock-parents = <&k3_clks 292 89>; 560 561 wiz0_pll0_refclk: pll0-refclk { 562 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 563 clock-output-names = "wiz0_pll0_refclk"; 564 #clock-cells = <0>; 565 assigned-clocks = <&wiz0_pll0_refclk>; 566 assigned-clock-parents = <&k3_clks 292 85>; 567 }; 568 569 wiz0_pll1_refclk: pll1-refclk { 570 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 571 clock-output-names = "wiz0_pll1_refclk"; 572 #clock-cells = <0>; 573 assigned-clocks = <&wiz0_pll1_refclk>; 574 assigned-clock-parents = <&k3_clks 292 85>; 575 }; 576 577 wiz0_refclk_dig: refclk-dig { 578 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 579 clock-output-names = "wiz0_refclk_dig"; 580 #clock-cells = <0>; 581 assigned-clocks = <&wiz0_refclk_dig>; 582 assigned-clock-parents = <&k3_clks 292 85>; 583 }; 584 585 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 586 clocks = <&wiz0_refclk_dig>; 587 #clock-cells = <0>; 588 }; 589 590 serdes0: serdes@5060000 { 591 compatible = "ti,j721e-serdes-10g"; 592 reg = <0x05060000 0x00010000>; 593 reg-names = "torrent_phy"; 594 resets = <&serdes_wiz0 0>; 595 reset-names = "torrent_reset"; 596 clocks = <&wiz0_pll0_refclk>; 597 clock-names = "refclk"; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 }; 601 }; 602 603 pcie1_rc: pcie@2910000 { 604 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 605 reg = <0x00 0x02910000 0x00 0x1000>, 606 <0x00 0x02917000 0x00 0x400>, 607 <0x00 0x0d800000 0x00 0x00800000>, 608 <0x00 0x18000000 0x00 0x00001000>; 609 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 610 interrupt-names = "link_state"; 611 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 612 device_type = "pci"; 613 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 614 max-link-speed = <3>; 615 num-lanes = <4>; 616 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 617 clocks = <&k3_clks 240 6>; 618 clock-names = "fck"; 619 #address-cells = <3>; 620 #size-cells = <2>; 621 bus-range = <0x0 0xff>; 622 cdns,no-bar-match-nbits = <64>; 623 vendor-id = <0x104c>; 624 device-id = <0xb00f>; 625 msi-map = <0x0 &gic_its 0x0 0x10000>; 626 dma-coherent; 627 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 628 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 629 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 630 }; 631 632 pcie1_ep: pcie-ep@2910000 { 633 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; 634 reg = <0x00 0x02910000 0x00 0x1000>, 635 <0x00 0x02917000 0x00 0x400>, 636 <0x00 0x0d800000 0x00 0x00800000>, 637 <0x00 0x18000000 0x00 0x08000000>; 638 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 639 interrupt-names = "link_state"; 640 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 641 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 642 max-link-speed = <3>; 643 num-lanes = <4>; 644 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 645 clocks = <&k3_clks 240 6>; 646 clock-names = "fck"; 647 max-functions = /bits/ 8 <6>; 648 dma-coherent; 649 }; 650 651 usbss0: cdns-usb@4104000 { 652 compatible = "ti,j721e-usb"; 653 reg = <0x00 0x4104000 0x00 0x100>; 654 dma-coherent; 655 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 656 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 657 clock-names = "ref", "lpm"; 658 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 659 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 660 #address-cells = <2>; 661 #size-cells = <2>; 662 ranges; 663 664 usb0: usb@6000000 { 665 compatible = "cdns,usb3"; 666 reg = <0x00 0x6000000 0x00 0x10000>, 667 <0x00 0x6010000 0x00 0x10000>, 668 <0x00 0x6020000 0x00 0x10000>; 669 reg-names = "otg", "xhci", "dev"; 670 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 671 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 672 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 673 interrupt-names = "host", 674 "peripheral", 675 "otg"; 676 maximum-speed = "super-speed"; 677 dr_mode = "otg"; 678 cdns,phyrst-a-enable; 679 }; 680 }; 681 682 main_gpio0: gpio@600000 { 683 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 684 reg = <0x00 0x00600000 0x00 0x100>; 685 gpio-controller; 686 #gpio-cells = <2>; 687 interrupt-parent = <&main_gpio_intr>; 688 interrupts = <145>, <146>, <147>, <148>, 689 <149>; 690 interrupt-controller; 691 #interrupt-cells = <2>; 692 ti,ngpio = <69>; 693 ti,davinci-gpio-unbanked = <0>; 694 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 695 clocks = <&k3_clks 105 0>; 696 clock-names = "gpio"; 697 }; 698 699 main_gpio2: gpio@610000 { 700 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 701 reg = <0x00 0x00610000 0x00 0x100>; 702 gpio-controller; 703 #gpio-cells = <2>; 704 interrupt-parent = <&main_gpio_intr>; 705 interrupts = <154>, <155>, <156>, <157>, 706 <158>; 707 interrupt-controller; 708 #interrupt-cells = <2>; 709 ti,ngpio = <69>; 710 ti,davinci-gpio-unbanked = <0>; 711 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 712 clocks = <&k3_clks 107 0>; 713 clock-names = "gpio"; 714 }; 715 716 main_gpio4: gpio@620000 { 717 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 718 reg = <0x00 0x00620000 0x00 0x100>; 719 gpio-controller; 720 #gpio-cells = <2>; 721 interrupt-parent = <&main_gpio_intr>; 722 interrupts = <163>, <164>, <165>, <166>, 723 <167>; 724 interrupt-controller; 725 #interrupt-cells = <2>; 726 ti,ngpio = <69>; 727 ti,davinci-gpio-unbanked = <0>; 728 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 729 clocks = <&k3_clks 109 0>; 730 clock-names = "gpio"; 731 }; 732 733 main_gpio6: gpio@630000 { 734 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 735 reg = <0x00 0x00630000 0x00 0x100>; 736 gpio-controller; 737 #gpio-cells = <2>; 738 interrupt-parent = <&main_gpio_intr>; 739 interrupts = <172>, <173>, <174>, <175>, 740 <176>; 741 interrupt-controller; 742 #interrupt-cells = <2>; 743 ti,ngpio = <69>; 744 ti,davinci-gpio-unbanked = <0>; 745 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 746 clocks = <&k3_clks 111 0>; 747 clock-names = "gpio"; 748 }; 749 750 main_r5fss0: r5fss@5c00000 { 751 compatible = "ti,j7200-r5fss"; 752 ti,cluster-mode = <1>; 753 #address-cells = <1>; 754 #size-cells = <1>; 755 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 756 <0x5d00000 0x00 0x5d00000 0x20000>; 757 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 758 759 main_r5fss0_core0: r5f@5c00000 { 760 compatible = "ti,j7200-r5f"; 761 reg = <0x5c00000 0x00010000>, 762 <0x5c10000 0x00010000>; 763 reg-names = "atcm", "btcm"; 764 ti,sci = <&dmsc>; 765 ti,sci-dev-id = <245>; 766 ti,sci-proc-ids = <0x06 0xff>; 767 resets = <&k3_reset 245 1>; 768 firmware-name = "j7200-main-r5f0_0-fw"; 769 ti,atcm-enable = <1>; 770 ti,btcm-enable = <1>; 771 ti,loczrama = <1>; 772 }; 773 774 main_r5fss0_core1: r5f@5d00000 { 775 compatible = "ti,j7200-r5f"; 776 reg = <0x5d00000 0x00008000>, 777 <0x5d10000 0x00008000>; 778 reg-names = "atcm", "btcm"; 779 ti,sci = <&dmsc>; 780 ti,sci-dev-id = <246>; 781 ti,sci-proc-ids = <0x07 0xff>; 782 resets = <&k3_reset 246 1>; 783 firmware-name = "j7200-main-r5f0_1-fw"; 784 ti,atcm-enable = <1>; 785 ti,btcm-enable = <1>; 786 ti,loczrama = <1>; 787 }; 788 }; 789}; 790