1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j721e-som-p0.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/phy/phy-cadence.h> 13 14/ { 15 chosen { 16 stdout-path = "serial2:115200n8"; 17 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 18 }; 19 20 gpio_keys: gpio-keys { 21 compatible = "gpio-keys"; 22 autorepeat; 23 pinctrl-names = "default"; 24 pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>; 25 26 sw10: sw10 { 27 label = "GPIO Key USER1"; 28 linux,code = <BTN_0>; 29 gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>; 30 }; 31 32 sw11: sw11 { 33 label = "GPIO Key USER2"; 34 linux,code = <BTN_1>; 35 gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>; 36 }; 37 }; 38 39 evm_12v0: fixedregulator-evm12v0 { 40 /* main supply */ 41 compatible = "regulator-fixed"; 42 regulator-name = "evm_12v0"; 43 regulator-min-microvolt = <12000000>; 44 regulator-max-microvolt = <12000000>; 45 regulator-always-on; 46 regulator-boot-on; 47 }; 48 49 vsys_3v3: fixedregulator-vsys3v3 { 50 /* Output of LMS140 */ 51 compatible = "regulator-fixed"; 52 regulator-name = "vsys_3v3"; 53 regulator-min-microvolt = <3300000>; 54 regulator-max-microvolt = <3300000>; 55 vin-supply = <&evm_12v0>; 56 regulator-always-on; 57 regulator-boot-on; 58 }; 59 60 vsys_5v0: fixedregulator-vsys5v0 { 61 /* Output of LM5140 */ 62 compatible = "regulator-fixed"; 63 regulator-name = "vsys_5v0"; 64 regulator-min-microvolt = <5000000>; 65 regulator-max-microvolt = <5000000>; 66 vin-supply = <&evm_12v0>; 67 regulator-always-on; 68 regulator-boot-on; 69 }; 70 71 vdd_mmc1: fixedregulator-sd { 72 compatible = "regulator-fixed"; 73 regulator-name = "vdd_mmc1"; 74 regulator-min-microvolt = <3300000>; 75 regulator-max-microvolt = <3300000>; 76 regulator-boot-on; 77 enable-active-high; 78 vin-supply = <&vsys_3v3>; 79 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 80 }; 81 82 vdd_sd_dv_alt: gpio-regulator-TLV71033 { 83 compatible = "regulator-gpio"; 84 pinctrl-names = "default"; 85 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; 86 regulator-name = "tlv71033"; 87 regulator-min-microvolt = <1800000>; 88 regulator-max-microvolt = <3300000>; 89 regulator-boot-on; 90 vin-supply = <&vsys_5v0>; 91 gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; 92 states = <1800000 0x0>, 93 <3300000 0x1>; 94 }; 95 96 sound0: sound@0 { 97 compatible = "ti,j721e-cpb-audio"; 98 model = "j721e-cpb"; 99 100 ti,cpb-mcasp = <&mcasp10>; 101 ti,cpb-codec = <&pcm3168a_1>; 102 103 clocks = <&k3_clks 184 1>, 104 <&k3_clks 184 2>, <&k3_clks 184 4>, 105 <&k3_clks 157 371>, 106 <&k3_clks 157 400>, <&k3_clks 157 401>; 107 clock-names = "cpb-mcasp-auxclk", 108 "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100", 109 "cpb-codec-scki", 110 "cpb-codec-scki-48000", "cpb-codec-scki-44100"; 111 }; 112}; 113 114&main_pmx0 { 115 sw10_button_pins_default: sw10-button-pins-default { 116 pinctrl-single,pins = < 117 J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ 118 >; 119 }; 120 121 main_mmc1_pins_default: main-mmc1-pins-default { 122 pinctrl-single,pins = < 123 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ 124 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ 125 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 126 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ 127 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 128 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ 129 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ 130 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ 131 J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ 132 >; 133 }; 134 135 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { 136 pinctrl-single,pins = < 137 J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ 138 >; 139 }; 140 141 main_usbss0_pins_default: main-usbss0-pins-default { 142 pinctrl-single,pins = < 143 J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ 144 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ 145 >; 146 }; 147 148 main_usbss1_pins_default: main-usbss1-pins-default { 149 pinctrl-single,pins = < 150 J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ 151 >; 152 }; 153 154 main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { 155 pinctrl-single,pins = < 156 J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ 157 >; 158 }; 159 160 main_i2c0_pins_default: main-i2c0-pins-default { 161 pinctrl-single,pins = < 162 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ 163 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ 164 >; 165 }; 166 167 main_i2c1_pins_default: main-i2c1-pins-default { 168 pinctrl-single,pins = < 169 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ 170 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ 171 >; 172 }; 173 174 main_i2c3_pins_default: main-i2c3-pins-default { 175 pinctrl-single,pins = < 176 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ 177 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ 178 >; 179 }; 180 181 main_i2c6_pins_default: main-i2c6-pins-default { 182 pinctrl-single,pins = < 183 J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ 184 J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ 185 >; 186 }; 187 188 mcasp10_pins_default: mcasp10-pins-default { 189 pinctrl-single,pins = < 190 J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ 191 J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ 192 J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */ 193 J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */ 194 J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */ 195 J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */ 196 J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */ 197 J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */ 198 J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */ 199 >; 200 }; 201 202 audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default { 203 pinctrl-single,pins = < 204 J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ 205 >; 206 }; 207}; 208 209&wkup_pmx0 { 210 sw11_button_pins_default: sw11-button-pins-default { 211 pinctrl-single,pins = < 212 J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ 213 >; 214 }; 215 216 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { 217 pinctrl-single,pins = < 218 J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ 219 J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ 220 J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */ 221 J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */ 222 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */ 223 J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */ 224 J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */ 225 J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */ 226 >; 227 }; 228 229 mcu_cpsw_pins_default: mcu-cpsw-pins-default { 230 pinctrl-single,pins = < 231 J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ 232 J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ 233 J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ 234 J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ 235 J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ 236 J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ 237 J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ 238 J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ 239 J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ 240 J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ 241 J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ 242 J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ 243 >; 244 }; 245 246 mcu_mdio_pins_default: mcu-mdio1-pins-default { 247 pinctrl-single,pins = < 248 J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ 249 J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ 250 >; 251 }; 252}; 253 254&wkup_uart0 { 255 /* Wakeup UART is used by System firmware */ 256 status = "reserved"; 257}; 258 259&main_uart0 { 260 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 261}; 262 263&main_uart3 { 264 /* UART not brought out */ 265 status = "disabled"; 266}; 267 268&main_uart5 { 269 /* UART not brought out */ 270 status = "disabled"; 271}; 272 273&main_uart6 { 274 /* UART not brought out */ 275 status = "disabled"; 276}; 277 278&main_uart7 { 279 /* UART not brought out */ 280 status = "disabled"; 281}; 282 283&main_uart8 { 284 /* UART not brought out */ 285 status = "disabled"; 286}; 287 288&main_uart9 { 289 /* UART not brought out */ 290 status = "disabled"; 291}; 292 293&main_gpio2 { 294 status = "disabled"; 295}; 296 297&main_gpio3 { 298 status = "disabled"; 299}; 300 301&main_gpio4 { 302 status = "disabled"; 303}; 304 305&main_gpio5 { 306 status = "disabled"; 307}; 308 309&main_gpio6 { 310 status = "disabled"; 311}; 312 313&main_gpio7 { 314 status = "disabled"; 315}; 316 317&wkup_gpio1 { 318 status = "disabled"; 319}; 320 321&main_sdhci0 { 322 /* eMMC */ 323 non-removable; 324 ti,driver-strength-ohm = <50>; 325 disable-wp; 326}; 327 328&main_sdhci1 { 329 /* SD/MMC */ 330 vmmc-supply = <&vdd_mmc1>; 331 vqmmc-supply = <&vdd_sd_dv_alt>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&main_mmc1_pins_default>; 334 ti,driver-strength-ohm = <50>; 335 disable-wp; 336}; 337 338&main_sdhci2 { 339 /* Unused */ 340 status = "disabled"; 341}; 342 343&usb_serdes_mux { 344 idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ 345}; 346 347&serdes_ln_ctrl { 348 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 349 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 350 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 351 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 352 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 353 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 354}; 355 356&serdes_wiz3 { 357 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; 358 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ 359}; 360 361&serdes3 { 362 serdes3_usb_link: phy@0 { 363 reg = <0>; 364 cdns,num-lanes = <2>; 365 #phy-cells = <0>; 366 cdns,phy-type = <PHY_TYPE_USB3>; 367 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; 368 }; 369}; 370 371&usbss0 { 372 pinctrl-names = "default"; 373 pinctrl-0 = <&main_usbss0_pins_default>; 374 ti,vbus-divider; 375}; 376 377&usb0 { 378 dr_mode = "otg"; 379 maximum-speed = "super-speed"; 380 phys = <&serdes3_usb_link>; 381 phy-names = "cdns3,usb3-phy"; 382}; 383 384&usbss1 { 385 pinctrl-names = "default"; 386 pinctrl-0 = <&main_usbss1_pins_default>; 387 ti,usb2-only; 388}; 389 390&usb1 { 391 dr_mode = "host"; 392 maximum-speed = "high-speed"; 393}; 394 395&ospi1 { 396 pinctrl-names = "default"; 397 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 398 399 flash@0{ 400 compatible = "jedec,spi-nor"; 401 reg = <0x0>; 402 spi-tx-bus-width = <1>; 403 spi-rx-bus-width = <4>; 404 spi-max-frequency = <40000000>; 405 cdns,tshsl-ns = <60>; 406 cdns,tsd2d-ns = <60>; 407 cdns,tchsh-ns = <60>; 408 cdns,tslch-ns = <60>; 409 cdns,read-delay = <2>; 410 #address-cells = <1>; 411 #size-cells = <1>; 412 }; 413}; 414 415&tscadc0 { 416 adc { 417 ti,adc-channels = <0 1 2 3 4 5 6 7>; 418 }; 419}; 420 421&tscadc1 { 422 adc { 423 ti,adc-channels = <0 1 2 3 4 5 6 7>; 424 }; 425}; 426 427&main_i2c0 { 428 pinctrl-names = "default"; 429 pinctrl-0 = <&main_i2c0_pins_default>; 430 clock-frequency = <400000>; 431 432 exp1: gpio@20 { 433 compatible = "ti,tca6416"; 434 reg = <0x20>; 435 gpio-controller; 436 #gpio-cells = <2>; 437 }; 438 439 exp2: gpio@22 { 440 compatible = "ti,tca6424"; 441 reg = <0x22>; 442 gpio-controller; 443 #gpio-cells = <2>; 444 445 p09-hog { 446 /* P11 - MCASP/TRACE_MUX_S0 */ 447 gpio-hog; 448 gpios = <9 GPIO_ACTIVE_HIGH>; 449 output-low; 450 line-name = "MCASP/TRACE_MUX_S0"; 451 }; 452 453 p10-hog { 454 /* P12 - MCASP/TRACE_MUX_S1 */ 455 gpio-hog; 456 gpios = <10 GPIO_ACTIVE_HIGH>; 457 output-high; 458 line-name = "MCASP/TRACE_MUX_S1"; 459 }; 460 }; 461}; 462 463&main_i2c1 { 464 pinctrl-names = "default"; 465 pinctrl-0 = <&main_i2c1_pins_default>; 466 clock-frequency = <400000>; 467 468 exp4: gpio@20 { 469 compatible = "ti,tca6408"; 470 reg = <0x20>; 471 gpio-controller; 472 #gpio-cells = <2>; 473 pinctrl-names = "default"; 474 pinctrl-0 = <&main_i2c1_exp4_pins_default>; 475 interrupt-parent = <&main_gpio1>; 476 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 477 interrupt-controller; 478 #interrupt-cells = <2>; 479 }; 480}; 481 482&k3_clks { 483 /* Confiure AUDIO_EXT_REFCLK2 pin as output */ 484 pinctrl-names = "default"; 485 pinctrl-0 = <&audi_ext_refclk2_pins_default>; 486}; 487 488&main_i2c3 { 489 pinctrl-names = "default"; 490 pinctrl-0 = <&main_i2c3_pins_default>; 491 clock-frequency = <400000>; 492 493 exp3: gpio@20 { 494 compatible = "ti,tca6408"; 495 reg = <0x20>; 496 gpio-controller; 497 #gpio-cells = <2>; 498 }; 499 500 pcm3168a_1: audio-codec@44 { 501 compatible = "ti,pcm3168a"; 502 reg = <0x44>; 503 504 #sound-dai-cells = <1>; 505 506 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; 507 508 /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */ 509 clocks = <&k3_clks 157 371>; 510 clock-names = "scki"; 511 512 /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */ 513 assigned-clocks = <&k3_clks 157 371>; 514 assigned-clock-parents = <&k3_clks 157 400>; 515 assigned-clock-rates = <24576000>; /* for 48KHz */ 516 517 VDD1-supply = <&vsys_3v3>; 518 VDD2-supply = <&vsys_3v3>; 519 VCCAD1-supply = <&vsys_5v0>; 520 VCCAD2-supply = <&vsys_5v0>; 521 VCCDA1-supply = <&vsys_5v0>; 522 VCCDA2-supply = <&vsys_5v0>; 523 }; 524}; 525 526&main_i2c6 { 527 pinctrl-names = "default"; 528 pinctrl-0 = <&main_i2c6_pins_default>; 529 clock-frequency = <400000>; 530 531 exp5: gpio@20 { 532 compatible = "ti,tca6408"; 533 reg = <0x20>; 534 gpio-controller; 535 #gpio-cells = <2>; 536 }; 537}; 538 539&mcu_cpsw { 540 pinctrl-names = "default"; 541 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; 542}; 543 544&davinci_mdio { 545 phy0: ethernet-phy@0 { 546 reg = <0>; 547 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 548 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 549 }; 550}; 551 552&cpsw_port1 { 553 phy-mode = "rgmii-rxid"; 554 phy-handle = <&phy0>; 555}; 556 557&dss { 558 /* 559 * These clock assignments are chosen to enable the following outputs: 560 * 561 * VP0 - DisplayPort SST 562 * VP1 - DPI0 563 * VP2 - DSI 564 * VP3 - DPI1 565 */ 566 567 assigned-clocks = <&k3_clks 152 1>, 568 <&k3_clks 152 4>, 569 <&k3_clks 152 9>, 570 <&k3_clks 152 13>; 571 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ 572 <&k3_clks 152 6>, /* PLL19_HSDIV0 */ 573 <&k3_clks 152 11>, /* PLL18_HSDIV0 */ 574 <&k3_clks 152 18>; /* PLL23_HSDIV0 */ 575}; 576 577&mcasp0 { 578 status = "disabled"; 579}; 580 581&mcasp1 { 582 status = "disabled"; 583}; 584 585&mcasp2 { 586 status = "disabled"; 587}; 588 589&mcasp3 { 590 status = "disabled"; 591}; 592 593&mcasp4 { 594 status = "disabled"; 595}; 596 597&mcasp5 { 598 status = "disabled"; 599}; 600 601&mcasp6 { 602 status = "disabled"; 603}; 604 605&mcasp7 { 606 status = "disabled"; 607}; 608 609&mcasp8 { 610 status = "disabled"; 611}; 612 613&mcasp9 { 614 status = "disabled"; 615}; 616 617&mcasp10 { 618 #sound-dai-cells = <0>; 619 620 pinctrl-names = "default"; 621 pinctrl-0 = <&mcasp10_pins_default>; 622 623 op-mode = <0>; /* MCASP_IIS_MODE */ 624 tdm-slots = <2>; 625 auxclk-fs-ratio = <256>; 626 627 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 628 1 1 1 1 629 2 2 2 0 630 >; 631 tx-num-evt = <0>; 632 rx-num-evt = <0>; 633}; 634 635&mcasp11 { 636 status = "disabled"; 637}; 638 639&cmn_refclk1 { 640 clock-frequency = <100000000>; 641}; 642 643&wiz0_pll1_refclk { 644 assigned-clocks = <&wiz0_pll1_refclk>; 645 assigned-clock-parents = <&cmn_refclk1>; 646}; 647 648&wiz0_refclk_dig { 649 assigned-clocks = <&wiz0_refclk_dig>; 650 assigned-clock-parents = <&cmn_refclk1>; 651}; 652 653&wiz1_pll1_refclk { 654 assigned-clocks = <&wiz1_pll1_refclk>; 655 assigned-clock-parents = <&cmn_refclk1>; 656}; 657 658&wiz1_refclk_dig { 659 assigned-clocks = <&wiz1_refclk_dig>; 660 assigned-clock-parents = <&cmn_refclk1>; 661}; 662 663&wiz2_pll1_refclk { 664 assigned-clocks = <&wiz2_pll1_refclk>; 665 assigned-clock-parents = <&cmn_refclk1>; 666}; 667 668&wiz2_refclk_dig { 669 assigned-clocks = <&wiz2_refclk_dig>; 670 assigned-clock-parents = <&cmn_refclk1>; 671}; 672 673&serdes0 { 674 assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; 675 assigned-clock-parents = <&wiz0_pll1_refclk>; 676 677 serdes0_pcie_link: phy@0 { 678 reg = <0>; 679 cdns,num-lanes = <1>; 680 #phy-cells = <0>; 681 cdns,phy-type = <PHY_TYPE_PCIE>; 682 resets = <&serdes_wiz0 1>; 683 }; 684}; 685 686&serdes1 { 687 assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>; 688 assigned-clock-parents = <&wiz1_pll1_refclk>; 689 690 serdes1_pcie_link: phy@0 { 691 reg = <0>; 692 cdns,num-lanes = <2>; 693 #phy-cells = <0>; 694 cdns,phy-type = <PHY_TYPE_PCIE>; 695 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; 696 }; 697}; 698 699&serdes2 { 700 assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>; 701 assigned-clock-parents = <&wiz2_pll1_refclk>; 702 703 serdes2_pcie_link: phy@0 { 704 reg = <0>; 705 cdns,num-lanes = <2>; 706 #phy-cells = <0>; 707 cdns,phy-type = <PHY_TYPE_PCIE>; 708 resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; 709 }; 710}; 711 712&pcie0_rc { 713 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 714 phys = <&serdes0_pcie_link>; 715 phy-names = "pcie-phy"; 716 num-lanes = <1>; 717}; 718 719&pcie1_rc { 720 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 721 phys = <&serdes1_pcie_link>; 722 phy-names = "pcie-phy"; 723 num-lanes = <2>; 724}; 725 726&pcie2_rc { 727 reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; 728 phys = <&serdes2_pcie_link>; 729 phy-names = "pcie-phy"; 730 num-lanes = <2>; 731}; 732 733&pcie0_ep { 734 phys = <&serdes0_pcie_link>; 735 phy-names = "pcie-phy"; 736 num-lanes = <1>; 737 status = "disabled"; 738}; 739 740&pcie1_ep { 741 phys = <&serdes1_pcie_link>; 742 phy-names = "pcie-phy"; 743 num-lanes = <2>; 744 status = "disabled"; 745}; 746 747&pcie2_ep { 748 phys = <&serdes2_pcie_link>; 749 phy-names = "pcie-phy"; 750 num-lanes = <2>; 751 status = "disabled"; 752}; 753 754&pcie3_rc { 755 status = "disabled"; 756}; 757 758&pcie3_ep { 759 status = "disabled"; 760}; 761 762&dss { 763 status = "disabled"; 764}; 765 766&icssg0_mdio { 767 status = "disabled"; 768}; 769 770&icssg1_mdio { 771 status = "disabled"; 772}; 773