1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * PowerNV setup code.
4 *
5 * Copyright 2011 IBM Corp.
6 */
7
8 #undef DEBUG
9
10 #include <linux/cpu.h>
11 #include <linux/errno.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/tty.h>
15 #include <linux/reboot.h>
16 #include <linux/init.h>
17 #include <linux/console.h>
18 #include <linux/delay.h>
19 #include <linux/irq.h>
20 #include <linux/seq_file.h>
21 #include <linux/of.h>
22 #include <linux/of_fdt.h>
23 #include <linux/interrupt.h>
24 #include <linux/bug.h>
25 #include <linux/pci.h>
26 #include <linux/cpufreq.h>
27 #include <linux/memblock.h>
28
29 #include <asm/machdep.h>
30 #include <asm/firmware.h>
31 #include <asm/xics.h>
32 #include <asm/xive.h>
33 #include <asm/opal.h>
34 #include <asm/kexec.h>
35 #include <asm/smp.h>
36 #include <asm/tm.h>
37 #include <asm/setup.h>
38 #include <asm/security_features.h>
39
40 #include "powernv.h"
41
42
fw_feature_is(const char * state,const char * name,struct device_node * fw_features)43 static bool fw_feature_is(const char *state, const char *name,
44 struct device_node *fw_features)
45 {
46 struct device_node *np;
47 bool rc = false;
48
49 np = of_get_child_by_name(fw_features, name);
50 if (np) {
51 rc = of_property_read_bool(np, state);
52 of_node_put(np);
53 }
54
55 return rc;
56 }
57
init_fw_feat_flags(struct device_node * np)58 static void init_fw_feat_flags(struct device_node *np)
59 {
60 if (fw_feature_is("enabled", "inst-spec-barrier-ori31,31,0", np))
61 security_ftr_set(SEC_FTR_SPEC_BAR_ORI31);
62
63 if (fw_feature_is("enabled", "fw-bcctrl-serialized", np))
64 security_ftr_set(SEC_FTR_BCCTRL_SERIALISED);
65
66 if (fw_feature_is("enabled", "inst-l1d-flush-ori30,30,0", np))
67 security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30);
68
69 if (fw_feature_is("enabled", "inst-l1d-flush-trig2", np))
70 security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2);
71
72 if (fw_feature_is("enabled", "fw-l1d-thread-split", np))
73 security_ftr_set(SEC_FTR_L1D_THREAD_PRIV);
74
75 if (fw_feature_is("enabled", "fw-count-cache-disabled", np))
76 security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED);
77
78 if (fw_feature_is("enabled", "fw-count-cache-flush-bcctr2,0,0", np))
79 security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST);
80
81 if (fw_feature_is("enabled", "needs-count-cache-flush-on-context-switch", np))
82 security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE);
83
84 /*
85 * The features below are enabled by default, so we instead look to see
86 * if firmware has *disabled* them, and clear them if so.
87 */
88 if (fw_feature_is("disabled", "speculation-policy-favor-security", np))
89 security_ftr_clear(SEC_FTR_FAVOUR_SECURITY);
90
91 if (fw_feature_is("disabled", "needs-l1d-flush-msr-pr-0-to-1", np))
92 security_ftr_clear(SEC_FTR_L1D_FLUSH_PR);
93
94 if (fw_feature_is("disabled", "needs-l1d-flush-msr-hv-1-to-0", np))
95 security_ftr_clear(SEC_FTR_L1D_FLUSH_HV);
96
97 if (fw_feature_is("disabled", "needs-spec-barrier-for-bound-checks", np))
98 security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR);
99 }
100
pnv_setup_security_mitigations(void)101 static void pnv_setup_security_mitigations(void)
102 {
103 struct device_node *np, *fw_features;
104 enum l1d_flush_type type;
105 bool enable;
106
107 /* Default to fallback in case fw-features are not available */
108 type = L1D_FLUSH_FALLBACK;
109
110 np = of_find_node_by_name(NULL, "ibm,opal");
111 fw_features = of_get_child_by_name(np, "fw-features");
112 of_node_put(np);
113
114 if (fw_features) {
115 init_fw_feat_flags(fw_features);
116 of_node_put(fw_features);
117
118 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2))
119 type = L1D_FLUSH_MTTRIG;
120
121 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30))
122 type = L1D_FLUSH_ORI;
123 }
124
125 /*
126 * If we are non-Power9 bare metal, we don't need to flush on kernel
127 * entry or after user access: they fix a P9 specific vulnerability.
128 */
129 if (!pvr_version_is(PVR_POWER9)) {
130 security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY);
131 security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS);
132 }
133
134 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \
135 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR) || \
136 security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV));
137
138 setup_rfi_flush(type, enable);
139 setup_count_cache_flush();
140
141 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
142 security_ftr_enabled(SEC_FTR_L1D_FLUSH_ENTRY);
143 setup_entry_flush(enable);
144
145 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
146 security_ftr_enabled(SEC_FTR_L1D_FLUSH_UACCESS);
147 setup_uaccess_flush(enable);
148
149 setup_stf_barrier();
150 }
151
pnv_check_guarded_cores(void)152 static void __init pnv_check_guarded_cores(void)
153 {
154 struct device_node *dn;
155 int bad_count = 0;
156
157 for_each_node_by_type(dn, "cpu") {
158 if (of_property_match_string(dn, "status", "bad") >= 0)
159 bad_count++;
160 }
161
162 if (bad_count) {
163 printk(" _ _______________\n");
164 pr_cont(" | | / \\\n");
165 pr_cont(" | | | WARNING! |\n");
166 pr_cont(" | | | |\n");
167 pr_cont(" | | | It looks like |\n");
168 pr_cont(" |_| | you have %*d |\n", 3, bad_count);
169 pr_cont(" _ | guarded cores |\n");
170 pr_cont(" (_) \\_______________/\n");
171 }
172 }
173
pnv_setup_arch(void)174 static void __init pnv_setup_arch(void)
175 {
176 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
177
178 pnv_setup_security_mitigations();
179
180 /* Initialize SMP */
181 pnv_smp_init();
182
183 /* Setup RTC and NVRAM callbacks */
184 if (firmware_has_feature(FW_FEATURE_OPAL))
185 opal_nvram_init();
186
187 /* Enable NAP mode */
188 powersave_nap = 1;
189
190 pnv_check_guarded_cores();
191
192 /* XXX PMCS */
193
194 pnv_rng_init();
195 }
196
pnv_init(void)197 static void __init pnv_init(void)
198 {
199 /*
200 * Initialize the LPC bus now so that legacy serial
201 * ports can be found on it
202 */
203 opal_lpc_init();
204
205 #ifdef CONFIG_HVC_OPAL
206 if (firmware_has_feature(FW_FEATURE_OPAL))
207 hvc_opal_init_early();
208 else
209 #endif
210 add_preferred_console("hvc", 0, NULL);
211
212 if (!radix_enabled()) {
213 size_t size = sizeof(struct slb_entry) * mmu_slb_size;
214 int i;
215
216 /* Allocate per cpu area to save old slb contents during MCE */
217 for_each_possible_cpu(i) {
218 paca_ptrs[i]->mce_faulty_slbs =
219 memblock_alloc_node(size,
220 __alignof__(struct slb_entry),
221 cpu_to_node(i));
222 }
223 }
224 }
225
pnv_init_IRQ(void)226 static void __init pnv_init_IRQ(void)
227 {
228 /* Try using a XIVE if available, otherwise use a XICS */
229 if (!xive_native_init())
230 xics_init();
231
232 WARN_ON(!ppc_md.get_irq);
233 }
234
pnv_show_cpuinfo(struct seq_file * m)235 static void pnv_show_cpuinfo(struct seq_file *m)
236 {
237 struct device_node *root;
238 const char *model = "";
239
240 root = of_find_node_by_path("/");
241 if (root)
242 model = of_get_property(root, "model", NULL);
243 seq_printf(m, "machine\t\t: PowerNV %s\n", model);
244 if (firmware_has_feature(FW_FEATURE_OPAL))
245 seq_printf(m, "firmware\t: OPAL\n");
246 else
247 seq_printf(m, "firmware\t: BML\n");
248 of_node_put(root);
249 if (radix_enabled())
250 seq_printf(m, "MMU\t\t: Radix\n");
251 else
252 seq_printf(m, "MMU\t\t: Hash\n");
253 }
254
pnv_prepare_going_down(void)255 static void pnv_prepare_going_down(void)
256 {
257 /*
258 * Disable all notifiers from OPAL, we can't
259 * service interrupts anymore anyway
260 */
261 opal_event_shutdown();
262
263 /* Print flash update message if one is scheduled. */
264 opal_flash_update_print_message();
265
266 smp_send_stop();
267
268 hard_irq_disable();
269 }
270
pnv_restart(char * cmd)271 static void __noreturn pnv_restart(char *cmd)
272 {
273 long rc;
274
275 pnv_prepare_going_down();
276
277 do {
278 if (!cmd || !strlen(cmd))
279 rc = opal_cec_reboot();
280 else if (strcmp(cmd, "full") == 0)
281 rc = opal_cec_reboot2(OPAL_REBOOT_FULL_IPL, NULL);
282 else if (strcmp(cmd, "mpipl") == 0)
283 rc = opal_cec_reboot2(OPAL_REBOOT_MPIPL, NULL);
284 else if (strcmp(cmd, "error") == 0)
285 rc = opal_cec_reboot2(OPAL_REBOOT_PLATFORM_ERROR, NULL);
286 else if (strcmp(cmd, "fast") == 0)
287 rc = opal_cec_reboot2(OPAL_REBOOT_FAST, NULL);
288 else
289 rc = OPAL_UNSUPPORTED;
290
291 if (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
292 /* Opal is busy wait for some time and retry */
293 opal_poll_events(NULL);
294 mdelay(10);
295
296 } else if (cmd && rc) {
297 /* Unknown error while issuing reboot */
298 if (rc == OPAL_UNSUPPORTED)
299 pr_err("Unsupported '%s' reboot.\n", cmd);
300 else
301 pr_err("Unable to issue '%s' reboot. Err=%ld\n",
302 cmd, rc);
303 pr_info("Forcing a cec-reboot\n");
304 cmd = NULL;
305 rc = OPAL_BUSY;
306
307 } else if (rc != OPAL_SUCCESS) {
308 /* Unknown error while issuing cec-reboot */
309 pr_err("Unable to reboot. Err=%ld\n", rc);
310 }
311
312 } while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT);
313
314 for (;;)
315 opal_poll_events(NULL);
316 }
317
pnv_power_off(void)318 static void __noreturn pnv_power_off(void)
319 {
320 long rc = OPAL_BUSY;
321
322 pnv_prepare_going_down();
323
324 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
325 rc = opal_cec_power_down(0);
326 if (rc == OPAL_BUSY_EVENT)
327 opal_poll_events(NULL);
328 else
329 mdelay(10);
330 }
331 for (;;)
332 opal_poll_events(NULL);
333 }
334
pnv_halt(void)335 static void __noreturn pnv_halt(void)
336 {
337 pnv_power_off();
338 }
339
pnv_progress(char * s,unsigned short hex)340 static void pnv_progress(char *s, unsigned short hex)
341 {
342 }
343
pnv_shutdown(void)344 static void pnv_shutdown(void)
345 {
346 /* Let the PCI code clear up IODA tables */
347 pnv_pci_shutdown();
348
349 /*
350 * Stop OPAL activity: Unregister all OPAL interrupts so they
351 * don't fire up while we kexec and make sure all potentially
352 * DMA'ing ops are complete (such as dump retrieval).
353 */
354 opal_shutdown();
355 }
356
357 #ifdef CONFIG_KEXEC_CORE
pnv_kexec_wait_secondaries_down(void)358 static void pnv_kexec_wait_secondaries_down(void)
359 {
360 int my_cpu, i, notified = -1;
361
362 my_cpu = get_cpu();
363
364 for_each_online_cpu(i) {
365 uint8_t status;
366 int64_t rc, timeout = 1000;
367
368 if (i == my_cpu)
369 continue;
370
371 for (;;) {
372 rc = opal_query_cpu_status(get_hard_smp_processor_id(i),
373 &status);
374 if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED)
375 break;
376 barrier();
377 if (i != notified) {
378 printk(KERN_INFO "kexec: waiting for cpu %d "
379 "(physical %d) to enter OPAL\n",
380 i, paca_ptrs[i]->hw_cpu_id);
381 notified = i;
382 }
383
384 /*
385 * On crash secondaries might be unreachable or hung,
386 * so timeout if we've waited too long
387 * */
388 mdelay(1);
389 if (timeout-- == 0) {
390 printk(KERN_ERR "kexec: timed out waiting for "
391 "cpu %d (physical %d) to enter OPAL\n",
392 i, paca_ptrs[i]->hw_cpu_id);
393 break;
394 }
395 }
396 }
397 }
398
pnv_kexec_cpu_down(int crash_shutdown,int secondary)399 static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
400 {
401 u64 reinit_flags;
402
403 if (xive_enabled())
404 xive_teardown_cpu();
405 else
406 xics_kexec_teardown_cpu(secondary);
407
408 /* On OPAL, we return all CPUs to firmware */
409 if (!firmware_has_feature(FW_FEATURE_OPAL))
410 return;
411
412 if (secondary) {
413 /* Return secondary CPUs to firmware on OPAL v3 */
414 mb();
415 get_paca()->kexec_state = KEXEC_STATE_REAL_MODE;
416 mb();
417
418 /* Return the CPU to OPAL */
419 opal_return_cpu();
420 } else {
421 /* Primary waits for the secondaries to have reached OPAL */
422 pnv_kexec_wait_secondaries_down();
423
424 /* Switch XIVE back to emulation mode */
425 if (xive_enabled())
426 xive_shutdown();
427
428 /*
429 * We might be running as little-endian - now that interrupts
430 * are disabled, reset the HILE bit to big-endian so we don't
431 * take interrupts in the wrong endian later
432 *
433 * We reinit to enable both radix and hash on P9 to ensure
434 * the mode used by the next kernel is always supported.
435 */
436 reinit_flags = OPAL_REINIT_CPUS_HILE_BE;
437 if (cpu_has_feature(CPU_FTR_ARCH_300))
438 reinit_flags |= OPAL_REINIT_CPUS_MMU_RADIX |
439 OPAL_REINIT_CPUS_MMU_HASH;
440 opal_reinit_cpus(reinit_flags);
441 }
442 }
443 #endif /* CONFIG_KEXEC_CORE */
444
445 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
pnv_memory_block_size(void)446 static unsigned long pnv_memory_block_size(void)
447 {
448 /*
449 * We map the kernel linear region with 1GB large pages on radix. For
450 * memory hot unplug to work our memory block size must be at least
451 * this size.
452 */
453 if (radix_enabled())
454 return radix_mem_block_size;
455 else
456 return 256UL * 1024 * 1024;
457 }
458 #endif
459
pnv_setup_machdep_opal(void)460 static void __init pnv_setup_machdep_opal(void)
461 {
462 ppc_md.get_boot_time = opal_get_boot_time;
463 ppc_md.restart = pnv_restart;
464 pm_power_off = pnv_power_off;
465 ppc_md.halt = pnv_halt;
466 /* ppc_md.system_reset_exception gets filled in by pnv_smp_init() */
467 ppc_md.machine_check_exception = opal_machine_check;
468 ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;
469 if (opal_check_token(OPAL_HANDLE_HMI2))
470 ppc_md.hmi_exception_early = opal_hmi_exception_early2;
471 else
472 ppc_md.hmi_exception_early = opal_hmi_exception_early;
473 ppc_md.handle_hmi_exception = opal_handle_hmi_exception;
474 }
475
pnv_probe(void)476 static int __init pnv_probe(void)
477 {
478 if (!of_machine_is_compatible("ibm,powernv"))
479 return 0;
480
481 if (firmware_has_feature(FW_FEATURE_OPAL))
482 pnv_setup_machdep_opal();
483
484 pr_debug("PowerNV detected !\n");
485
486 pnv_init();
487
488 return 1;
489 }
490
491 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
pnv_tm_init(void)492 void __init pnv_tm_init(void)
493 {
494 if (!firmware_has_feature(FW_FEATURE_OPAL) ||
495 !pvr_version_is(PVR_POWER9) ||
496 early_cpu_has_feature(CPU_FTR_TM))
497 return;
498
499 if (opal_reinit_cpus(OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) != OPAL_SUCCESS)
500 return;
501
502 pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n");
503 cur_cpu_spec->cpu_features |= CPU_FTR_TM;
504 /* Make sure "normal" HTM is off (it should be) */
505 cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_HTM;
506 /* Turn on no suspend mode, and HTM no SC */
507 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NO_SUSPEND | \
508 PPC_FEATURE2_HTM_NOSC;
509 tm_suspend_disabled = true;
510 }
511 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
512
513 /*
514 * Returns the cpu frequency for 'cpu' in Hz. This is used by
515 * /proc/cpuinfo
516 */
pnv_get_proc_freq(unsigned int cpu)517 static unsigned long pnv_get_proc_freq(unsigned int cpu)
518 {
519 unsigned long ret_freq;
520
521 ret_freq = cpufreq_get(cpu) * 1000ul;
522
523 /*
524 * If the backend cpufreq driver does not exist,
525 * then fallback to old way of reporting the clockrate.
526 */
527 if (!ret_freq)
528 ret_freq = ppc_proc_freq;
529 return ret_freq;
530 }
531
pnv_machine_check_early(struct pt_regs * regs)532 static long pnv_machine_check_early(struct pt_regs *regs)
533 {
534 long handled = 0;
535
536 if (cur_cpu_spec && cur_cpu_spec->machine_check_early)
537 handled = cur_cpu_spec->machine_check_early(regs);
538
539 return handled;
540 }
541
define_machine(powernv)542 define_machine(powernv) {
543 .name = "PowerNV",
544 .probe = pnv_probe,
545 .setup_arch = pnv_setup_arch,
546 .init_IRQ = pnv_init_IRQ,
547 .show_cpuinfo = pnv_show_cpuinfo,
548 .get_proc_freq = pnv_get_proc_freq,
549 .discover_phbs = pnv_pci_init,
550 .progress = pnv_progress,
551 .machine_shutdown = pnv_shutdown,
552 .power_save = NULL,
553 .calibrate_decr = generic_calibrate_decr,
554 .machine_check_early = pnv_machine_check_early,
555 #ifdef CONFIG_KEXEC_CORE
556 .kexec_cpu_down = pnv_kexec_cpu_down,
557 #endif
558 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
559 .memory_block_size = pnv_memory_block_size,
560 #endif
561 };
562