1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ICS backend for OPAL managed interrupts.
4 *
5 * Copyright 2011 IBM Corp.
6 */
7
8 #undef DEBUG
9
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/irq.h>
13 #include <linux/smp.h>
14 #include <linux/interrupt.h>
15 #include <linux/init.h>
16 #include <linux/cpu.h>
17 #include <linux/of.h>
18 #include <linux/spinlock.h>
19 #include <linux/msi.h>
20
21 #include <asm/prom.h>
22 #include <asm/smp.h>
23 #include <asm/machdep.h>
24 #include <asm/irq.h>
25 #include <asm/errno.h>
26 #include <asm/xics.h>
27 #include <asm/opal.h>
28 #include <asm/firmware.h>
29
ics_opal_mangle_server(int server)30 static int ics_opal_mangle_server(int server)
31 {
32 /* No link for now */
33 return server << 2;
34 }
35
ics_opal_unmangle_server(int server)36 static int ics_opal_unmangle_server(int server)
37 {
38 /* No link for now */
39 return server >> 2;
40 }
41
ics_opal_unmask_irq(struct irq_data * d)42 static void ics_opal_unmask_irq(struct irq_data *d)
43 {
44 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
45 int64_t rc;
46 int server;
47
48 pr_devel("ics-hal: unmask virq %d [hw 0x%x]\n", d->irq, hw_irq);
49
50 if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
51 return;
52
53 server = xics_get_irq_server(d->irq, irq_data_get_affinity_mask(d), 0);
54 server = ics_opal_mangle_server(server);
55
56 rc = opal_set_xive(hw_irq, server, DEFAULT_PRIORITY);
57 if (rc != OPAL_SUCCESS)
58 pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
59 " error %lld\n",
60 __func__, d->irq, hw_irq, server, rc);
61 }
62
ics_opal_startup(struct irq_data * d)63 static unsigned int ics_opal_startup(struct irq_data *d)
64 {
65 ics_opal_unmask_irq(d);
66 return 0;
67 }
68
ics_opal_mask_real_irq(unsigned int hw_irq)69 static void ics_opal_mask_real_irq(unsigned int hw_irq)
70 {
71 int server = ics_opal_mangle_server(xics_default_server);
72 int64_t rc;
73
74 if (hw_irq == XICS_IPI)
75 return;
76
77 /* Have to set XIVE to 0xff to be able to remove a slot */
78 rc = opal_set_xive(hw_irq, server, 0xff);
79 if (rc != OPAL_SUCCESS)
80 pr_err("%s: opal_set_xive(0xff) irq=%u returned %lld\n",
81 __func__, hw_irq, rc);
82 }
83
ics_opal_mask_irq(struct irq_data * d)84 static void ics_opal_mask_irq(struct irq_data *d)
85 {
86 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
87
88 pr_devel("ics-hal: mask virq %d [hw 0x%x]\n", d->irq, hw_irq);
89
90 if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
91 return;
92 ics_opal_mask_real_irq(hw_irq);
93 }
94
ics_opal_set_affinity(struct irq_data * d,const struct cpumask * cpumask,bool force)95 static int ics_opal_set_affinity(struct irq_data *d,
96 const struct cpumask *cpumask,
97 bool force)
98 {
99 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
100 __be16 oserver;
101 int16_t server;
102 int8_t priority;
103 int64_t rc;
104 int wanted_server;
105
106 if (hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS)
107 return -1;
108
109 rc = opal_get_xive(hw_irq, &oserver, &priority);
110 if (rc != OPAL_SUCCESS) {
111 pr_err("%s: opal_get_xive(irq=%d [hw 0x%x]) error %lld\n",
112 __func__, d->irq, hw_irq, rc);
113 return -1;
114 }
115 server = be16_to_cpu(oserver);
116
117 wanted_server = xics_get_irq_server(d->irq, cpumask, 1);
118 if (wanted_server < 0) {
119 pr_warn("%s: No online cpus in the mask %*pb for irq %d\n",
120 __func__, cpumask_pr_args(cpumask), d->irq);
121 return -1;
122 }
123 server = ics_opal_mangle_server(wanted_server);
124
125 pr_debug("ics-hal: set-affinity irq %d [hw 0x%x] server: 0x%x/0x%x\n",
126 d->irq, hw_irq, wanted_server, server);
127
128 rc = opal_set_xive(hw_irq, server, priority);
129 if (rc != OPAL_SUCCESS) {
130 pr_err("%s: opal_set_xive(irq=%d [hw 0x%x] server=%x)"
131 " error %lld\n",
132 __func__, d->irq, hw_irq, server, rc);
133 return -1;
134 }
135 return IRQ_SET_MASK_OK;
136 }
137
138 static struct irq_chip ics_opal_irq_chip = {
139 .name = "OPAL ICS",
140 .irq_startup = ics_opal_startup,
141 .irq_mask = ics_opal_mask_irq,
142 .irq_unmask = ics_opal_unmask_irq,
143 .irq_eoi = NULL, /* Patched at init time */
144 .irq_set_affinity = ics_opal_set_affinity,
145 .irq_set_type = xics_set_irq_type,
146 .irq_retrigger = xics_retrigger,
147 };
148
ics_opal_host_match(struct ics * ics,struct device_node * node)149 static int ics_opal_host_match(struct ics *ics, struct device_node *node)
150 {
151 return 1;
152 }
153
ics_opal_check(struct ics * ics,unsigned int hw_irq)154 static int ics_opal_check(struct ics *ics, unsigned int hw_irq)
155 {
156 int64_t rc;
157 __be16 server;
158 int8_t priority;
159
160 if (WARN_ON(hw_irq == XICS_IPI || hw_irq == XICS_IRQ_SPURIOUS))
161 return -EINVAL;
162
163 /* Check if HAL knows about this interrupt */
164 rc = opal_get_xive(hw_irq, &server, &priority);
165 if (rc != OPAL_SUCCESS)
166 return -ENXIO;
167
168 return 0;
169 }
170
ics_opal_mask_unknown(struct ics * ics,unsigned long vec)171 static void ics_opal_mask_unknown(struct ics *ics, unsigned long vec)
172 {
173 int64_t rc;
174 __be16 server;
175 int8_t priority;
176
177 /* Check if HAL knows about this interrupt */
178 rc = opal_get_xive(vec, &server, &priority);
179 if (rc != OPAL_SUCCESS)
180 return;
181
182 ics_opal_mask_real_irq(vec);
183 }
184
ics_opal_get_server(struct ics * ics,unsigned long vec)185 static long ics_opal_get_server(struct ics *ics, unsigned long vec)
186 {
187 int64_t rc;
188 __be16 server;
189 int8_t priority;
190
191 /* Check if HAL knows about this interrupt */
192 rc = opal_get_xive(vec, &server, &priority);
193 if (rc != OPAL_SUCCESS)
194 return -1;
195 return ics_opal_unmangle_server(be16_to_cpu(server));
196 }
197
198 /* Only one global & state struct ics */
199 static struct ics ics_hal = {
200 .check = ics_opal_check,
201 .mask_unknown = ics_opal_mask_unknown,
202 .get_server = ics_opal_get_server,
203 .host_match = ics_opal_host_match,
204 .chip = &ics_opal_irq_chip,
205 };
206
ics_opal_init(void)207 int __init ics_opal_init(void)
208 {
209 if (!firmware_has_feature(FW_FEATURE_OPAL))
210 return -ENODEV;
211
212 /* We need to patch our irq chip's EOI to point to the
213 * right ICP
214 */
215 ics_opal_irq_chip.irq_eoi = icp_ops->eoi;
216
217 /* Register ourselves */
218 xics_register_ics(&ics_hal);
219
220 pr_info("ICS OPAL backend registered\n");
221
222 return 0;
223 }
224