1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020 Microchip Technology Inc */ 3 4/dts-v1/; 5 6#include "microchip-mpfs.dtsi" 7 8/* Clock frequency (in Hz) of the rtcclk */ 9#define RTCCLK_FREQ 1000000 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 model = "Microchip PolarFire-SoC Icicle Kit"; 15 compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; 16 17 aliases { 18 ethernet0 = &emac1; 19 serial0 = &serial0; 20 serial1 = &serial1; 21 serial2 = &serial2; 22 serial3 = &serial3; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 cpus { 30 timebase-frequency = <RTCCLK_FREQ>; 31 }; 32 33 memory@80000000 { 34 device_type = "memory"; 35 reg = <0x0 0x80000000 0x0 0x40000000>; 36 clocks = <&clkcfg 26>; 37 }; 38 39 soc { 40 }; 41}; 42 43&serial0 { 44 status = "okay"; 45}; 46 47&serial1 { 48 status = "okay"; 49}; 50 51&serial2 { 52 status = "okay"; 53}; 54 55&serial3 { 56 status = "okay"; 57}; 58 59&mmc { 60 status = "okay"; 61 62 bus-width = <4>; 63 disable-wp; 64 cap-sd-highspeed; 65 card-detect-delay = <200>; 66 sd-uhs-sdr12; 67 sd-uhs-sdr25; 68 sd-uhs-sdr50; 69 sd-uhs-sdr104; 70}; 71 72&emac0 { 73 phy-mode = "sgmii"; 74 phy-handle = <&phy0>; 75 phy0: ethernet-phy@8 { 76 reg = <8>; 77 ti,fifo-depth = <0x01>; 78 }; 79}; 80 81&emac1 { 82 status = "okay"; 83 phy-mode = "sgmii"; 84 phy-handle = <&phy1>; 85 phy1: ethernet-phy@9 { 86 reg = <9>; 87 ti,fifo-depth = <0x01>; 88 }; 89}; 90