1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020 Microchip Technology Inc */ 3 4/dts-v1/; 5 6/ { 7 #address-cells = <2>; 8 #size-cells = <2>; 9 model = "Microchip PolarFire SoC"; 10 compatible = "microchip,mpfs"; 11 12 cpus { 13 #address-cells = <1>; 14 #size-cells = <0>; 15 16 cpu@0 { 17 clock-frequency = <0>; 18 compatible = "sifive,e51", "sifive,rocket0", "riscv"; 19 device_type = "cpu"; 20 i-cache-block-size = <64>; 21 i-cache-sets = <128>; 22 i-cache-size = <16384>; 23 reg = <0>; 24 riscv,isa = "rv64imac"; 25 status = "disabled"; 26 27 cpu0_intc: interrupt-controller { 28 #interrupt-cells = <1>; 29 compatible = "riscv,cpu-intc"; 30 interrupt-controller; 31 }; 32 }; 33 34 cpu@1 { 35 clock-frequency = <0>; 36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 37 d-cache-block-size = <64>; 38 d-cache-sets = <64>; 39 d-cache-size = <32768>; 40 d-tlb-sets = <1>; 41 d-tlb-size = <32>; 42 device_type = "cpu"; 43 i-cache-block-size = <64>; 44 i-cache-sets = <64>; 45 i-cache-size = <32768>; 46 i-tlb-sets = <1>; 47 i-tlb-size = <32>; 48 mmu-type = "riscv,sv39"; 49 reg = <1>; 50 riscv,isa = "rv64imafdc"; 51 tlb-split; 52 status = "okay"; 53 54 cpu1_intc: interrupt-controller { 55 #interrupt-cells = <1>; 56 compatible = "riscv,cpu-intc"; 57 interrupt-controller; 58 }; 59 }; 60 61 cpu@2 { 62 clock-frequency = <0>; 63 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 64 d-cache-block-size = <64>; 65 d-cache-sets = <64>; 66 d-cache-size = <32768>; 67 d-tlb-sets = <1>; 68 d-tlb-size = <32>; 69 device_type = "cpu"; 70 i-cache-block-size = <64>; 71 i-cache-sets = <64>; 72 i-cache-size = <32768>; 73 i-tlb-sets = <1>; 74 i-tlb-size = <32>; 75 mmu-type = "riscv,sv39"; 76 reg = <2>; 77 riscv,isa = "rv64imafdc"; 78 tlb-split; 79 status = "okay"; 80 81 cpu2_intc: interrupt-controller { 82 #interrupt-cells = <1>; 83 compatible = "riscv,cpu-intc"; 84 interrupt-controller; 85 }; 86 }; 87 88 cpu@3 { 89 clock-frequency = <0>; 90 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 91 d-cache-block-size = <64>; 92 d-cache-sets = <64>; 93 d-cache-size = <32768>; 94 d-tlb-sets = <1>; 95 d-tlb-size = <32>; 96 device_type = "cpu"; 97 i-cache-block-size = <64>; 98 i-cache-sets = <64>; 99 i-cache-size = <32768>; 100 i-tlb-sets = <1>; 101 i-tlb-size = <32>; 102 mmu-type = "riscv,sv39"; 103 reg = <3>; 104 riscv,isa = "rv64imafdc"; 105 tlb-split; 106 status = "okay"; 107 108 cpu3_intc: interrupt-controller { 109 #interrupt-cells = <1>; 110 compatible = "riscv,cpu-intc"; 111 interrupt-controller; 112 }; 113 }; 114 115 cpu@4 { 116 clock-frequency = <0>; 117 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 118 d-cache-block-size = <64>; 119 d-cache-sets = <64>; 120 d-cache-size = <32768>; 121 d-tlb-sets = <1>; 122 d-tlb-size = <32>; 123 device_type = "cpu"; 124 i-cache-block-size = <64>; 125 i-cache-sets = <64>; 126 i-cache-size = <32768>; 127 i-tlb-sets = <1>; 128 i-tlb-size = <32>; 129 mmu-type = "riscv,sv39"; 130 reg = <4>; 131 riscv,isa = "rv64imafdc"; 132 tlb-split; 133 status = "okay"; 134 cpu4_intc: interrupt-controller { 135 #interrupt-cells = <1>; 136 compatible = "riscv,cpu-intc"; 137 interrupt-controller; 138 }; 139 }; 140 }; 141 142 soc { 143 #address-cells = <2>; 144 #size-cells = <2>; 145 compatible = "simple-bus"; 146 ranges; 147 148 cache-controller@2010000 { 149 compatible = "sifive,fu540-c000-ccache", "cache"; 150 cache-block-size = <64>; 151 cache-level = <2>; 152 cache-sets = <1024>; 153 cache-size = <2097152>; 154 cache-unified; 155 interrupt-parent = <&plic>; 156 interrupts = <1 2 3>; 157 reg = <0x0 0x2010000 0x0 0x1000>; 158 }; 159 160 clint@2000000 { 161 compatible = "sifive,clint0"; 162 reg = <0x0 0x2000000 0x0 0xC000>; 163 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 164 &cpu1_intc 3 &cpu1_intc 7 165 &cpu2_intc 3 &cpu2_intc 7 166 &cpu3_intc 3 &cpu3_intc 7 167 &cpu4_intc 3 &cpu4_intc 7>; 168 }; 169 170 plic: interrupt-controller@c000000 { 171 #interrupt-cells = <1>; 172 compatible = "sifive,plic-1.0.0"; 173 reg = <0x0 0xc000000 0x0 0x4000000>; 174 riscv,ndev = <186>; 175 interrupt-controller; 176 interrupts-extended = <&cpu0_intc 11 177 &cpu1_intc 11 &cpu1_intc 9 178 &cpu2_intc 11 &cpu2_intc 9 179 &cpu3_intc 11 &cpu3_intc 9 180 &cpu4_intc 11 &cpu4_intc 9>; 181 }; 182 183 dma@3000000 { 184 compatible = "sifive,fu540-c000-pdma"; 185 reg = <0x0 0x3000000 0x0 0x8000>; 186 interrupt-parent = <&plic>; 187 interrupts = <23 24 25 26 27 28 29 30>; 188 #dma-cells = <1>; 189 }; 190 191 refclk: refclk { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <600000000>; 195 clock-output-names = "msspllclk"; 196 }; 197 198 clkcfg: clkcfg@20002000 { 199 compatible = "microchip,mpfs-clkcfg"; 200 reg = <0x0 0x20002000 0x0 0x1000>; 201 reg-names = "mss_sysreg"; 202 clocks = <&refclk>; 203 #clock-cells = <1>; 204 clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ 205 "mac0", "mac1", "mmc", "timer", /* 4-7 */ 206 "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ 207 "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ 208 "i2c1", "can0", "can1", "usb", /* 16-19 */ 209 "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ 210 "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ 211 "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ 212 }; 213 214 serial0: serial@20000000 { 215 compatible = "ns16550a"; 216 reg = <0x0 0x20000000 0x0 0x400>; 217 reg-io-width = <4>; 218 reg-shift = <2>; 219 interrupt-parent = <&plic>; 220 interrupts = <90>; 221 current-speed = <115200>; 222 clocks = <&clkcfg 8>; 223 status = "disabled"; 224 }; 225 226 serial1: serial@20100000 { 227 compatible = "ns16550a"; 228 reg = <0x0 0x20100000 0x0 0x400>; 229 reg-io-width = <4>; 230 reg-shift = <2>; 231 interrupt-parent = <&plic>; 232 interrupts = <91>; 233 current-speed = <115200>; 234 clocks = <&clkcfg 9>; 235 status = "disabled"; 236 }; 237 238 serial2: serial@20102000 { 239 compatible = "ns16550a"; 240 reg = <0x0 0x20102000 0x0 0x400>; 241 reg-io-width = <4>; 242 reg-shift = <2>; 243 interrupt-parent = <&plic>; 244 interrupts = <92>; 245 current-speed = <115200>; 246 clocks = <&clkcfg 10>; 247 status = "disabled"; 248 }; 249 250 serial3: serial@20104000 { 251 compatible = "ns16550a"; 252 reg = <0x0 0x20104000 0x0 0x400>; 253 reg-io-width = <4>; 254 reg-shift = <2>; 255 interrupt-parent = <&plic>; 256 interrupts = <93>; 257 current-speed = <115200>; 258 clocks = <&clkcfg 11>; 259 status = "disabled"; 260 }; 261 262 /* Common node entry for emmc/sd */ 263 mmc: mmc@20008000 { 264 compatible = "cdns,sd4hc"; 265 reg = <0x0 0x20008000 0x0 0x1000>; 266 interrupt-parent = <&plic>; 267 interrupts = <88 89>; 268 pinctrl-names = "default"; 269 clocks = <&clkcfg 6>; 270 max-frequency = <200000000>; 271 status = "disabled"; 272 }; 273 274 emac0: ethernet@20110000 { 275 compatible = "cdns,macb"; 276 reg = <0x0 0x20110000 0x0 0x2000>; 277 interrupt-parent = <&plic>; 278 interrupts = <64 65 66 67>; 279 local-mac-address = [00 00 00 00 00 00]; 280 clocks = <&clkcfg 4>, <&clkcfg 2>; 281 clock-names = "pclk", "hclk"; 282 status = "disabled"; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 }; 286 287 emac1: ethernet@20112000 { 288 compatible = "cdns,macb"; 289 reg = <0x0 0x20112000 0x0 0x2000>; 290 interrupt-parent = <&plic>; 291 interrupts = <70 71 72 73>; 292 local-mac-address = [00 00 00 00 00 00]; 293 clocks = <&clkcfg 5>, <&clkcfg 2>; 294 status = "disabled"; 295 clock-names = "pclk", "hclk"; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 }; 299 300 }; 301}; 302