1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020 Intel Corporation
4 * Author: Johannes Berg <johannes@sipsolutions.net>
5 */
6 #include <linux/module.h>
7 #include <linux/pci.h>
8 #include <linux/virtio.h>
9 #include <linux/virtio_config.h>
10 #include <linux/logic_iomem.h>
11 #include <linux/irqdomain.h>
12 #include <linux/virtio_pcidev.h>
13 #include <linux/virtio-uml.h>
14 #include <linux/delay.h>
15 #include <linux/msi.h>
16 #include <asm/unaligned.h>
17 #include <irq_kern.h>
18
19 #define MAX_DEVICES 8
20 #define MAX_MSI_VECTORS 32
21 #define CFG_SPACE_SIZE 4096
22
23 /* for MSI-X we have a 32-bit payload */
24 #define MAX_IRQ_MSG_SIZE (sizeof(struct virtio_pcidev_msg) + sizeof(u32))
25 #define NUM_IRQ_MSGS 10
26
27 #define HANDLE_NO_FREE(ptr) ((void *)((unsigned long)(ptr) | 1))
28 #define HANDLE_IS_NO_FREE(ptr) ((unsigned long)(ptr) & 1)
29
30 struct um_pci_device {
31 struct virtio_device *vdev;
32
33 /* for now just standard BARs */
34 u8 resptr[PCI_STD_NUM_BARS];
35
36 struct virtqueue *cmd_vq, *irq_vq;
37
38 #define UM_PCI_STAT_WAITING 0
39 unsigned long status;
40
41 int irq;
42 };
43
44 struct um_pci_device_reg {
45 struct um_pci_device *dev;
46 void __iomem *iomem;
47 };
48
49 static struct pci_host_bridge *bridge;
50 static DEFINE_MUTEX(um_pci_mtx);
51 static struct um_pci_device_reg um_pci_devices[MAX_DEVICES];
52 static struct fwnode_handle *um_pci_fwnode;
53 static struct irq_domain *um_pci_inner_domain;
54 static struct irq_domain *um_pci_msi_domain;
55 static unsigned long um_pci_msi_used[BITS_TO_LONGS(MAX_MSI_VECTORS)];
56
57 #define UM_VIRT_PCI_MAXDELAY 40000
58
59 struct um_pci_message_buffer {
60 struct virtio_pcidev_msg hdr;
61 u8 data[8];
62 };
63
64 static struct um_pci_message_buffer __percpu *um_pci_msg_bufs;
65
um_pci_send_cmd(struct um_pci_device * dev,struct virtio_pcidev_msg * cmd,unsigned int cmd_size,const void * extra,unsigned int extra_size,void * out,unsigned int out_size)66 static int um_pci_send_cmd(struct um_pci_device *dev,
67 struct virtio_pcidev_msg *cmd,
68 unsigned int cmd_size,
69 const void *extra, unsigned int extra_size,
70 void *out, unsigned int out_size)
71 {
72 struct scatterlist out_sg, extra_sg, in_sg;
73 struct scatterlist *sgs_list[] = {
74 [0] = &out_sg,
75 [1] = extra ? &extra_sg : &in_sg,
76 [2] = extra ? &in_sg : NULL,
77 };
78 struct um_pci_message_buffer *buf;
79 int delay_count = 0;
80 int ret, len;
81 bool posted;
82
83 if (WARN_ON(cmd_size < sizeof(*cmd) || cmd_size > sizeof(*buf)))
84 return -EINVAL;
85
86 switch (cmd->op) {
87 case VIRTIO_PCIDEV_OP_CFG_WRITE:
88 case VIRTIO_PCIDEV_OP_MMIO_WRITE:
89 case VIRTIO_PCIDEV_OP_MMIO_MEMSET:
90 /* in PCI, writes are posted, so don't wait */
91 posted = !out;
92 WARN_ON(!posted);
93 break;
94 default:
95 posted = false;
96 break;
97 }
98
99 buf = get_cpu_var(um_pci_msg_bufs);
100 memcpy(buf, cmd, cmd_size);
101
102 if (posted) {
103 u8 *ncmd = kmalloc(cmd_size + extra_size, GFP_ATOMIC);
104
105 if (ncmd) {
106 memcpy(ncmd, cmd, cmd_size);
107 if (extra)
108 memcpy(ncmd + cmd_size, extra, extra_size);
109 cmd = (void *)ncmd;
110 cmd_size += extra_size;
111 extra = NULL;
112 extra_size = 0;
113 } else {
114 /* try without allocating memory */
115 posted = false;
116 cmd = (void *)buf;
117 }
118 } else {
119 cmd = (void *)buf;
120 }
121
122 sg_init_one(&out_sg, cmd, cmd_size);
123 if (extra)
124 sg_init_one(&extra_sg, extra, extra_size);
125 if (out)
126 sg_init_one(&in_sg, out, out_size);
127
128 /* add to internal virtio queue */
129 ret = virtqueue_add_sgs(dev->cmd_vq, sgs_list,
130 extra ? 2 : 1,
131 out ? 1 : 0,
132 posted ? cmd : HANDLE_NO_FREE(cmd),
133 GFP_ATOMIC);
134 if (ret) {
135 if (posted)
136 kfree(cmd);
137 goto out;
138 }
139
140 if (posted) {
141 virtqueue_kick(dev->cmd_vq);
142 ret = 0;
143 goto out;
144 }
145
146 /* kick and poll for getting a response on the queue */
147 set_bit(UM_PCI_STAT_WAITING, &dev->status);
148 virtqueue_kick(dev->cmd_vq);
149
150 while (1) {
151 void *completed = virtqueue_get_buf(dev->cmd_vq, &len);
152
153 if (completed == HANDLE_NO_FREE(cmd))
154 break;
155
156 if (completed && !HANDLE_IS_NO_FREE(completed))
157 kfree(completed);
158
159 if (WARN_ONCE(virtqueue_is_broken(dev->cmd_vq) ||
160 ++delay_count > UM_VIRT_PCI_MAXDELAY,
161 "um virt-pci delay: %d", delay_count)) {
162 ret = -EIO;
163 break;
164 }
165 udelay(1);
166 }
167 clear_bit(UM_PCI_STAT_WAITING, &dev->status);
168
169 out:
170 put_cpu_var(um_pci_msg_bufs);
171 return ret;
172 }
173
um_pci_cfgspace_read(void * priv,unsigned int offset,int size)174 static unsigned long um_pci_cfgspace_read(void *priv, unsigned int offset,
175 int size)
176 {
177 struct um_pci_device_reg *reg = priv;
178 struct um_pci_device *dev = reg->dev;
179 struct virtio_pcidev_msg hdr = {
180 .op = VIRTIO_PCIDEV_OP_CFG_READ,
181 .size = size,
182 .addr = offset,
183 };
184 /* buf->data is maximum size - we may only use parts of it */
185 struct um_pci_message_buffer *buf;
186 u8 *data;
187 unsigned long ret = ULONG_MAX;
188
189 if (!dev)
190 return ULONG_MAX;
191
192 buf = get_cpu_var(um_pci_msg_bufs);
193 data = buf->data;
194
195 memset(buf->data, 0xff, sizeof(buf->data));
196
197 switch (size) {
198 case 1:
199 case 2:
200 case 4:
201 #ifdef CONFIG_64BIT
202 case 8:
203 #endif
204 break;
205 default:
206 WARN(1, "invalid config space read size %d\n", size);
207 goto out;
208 }
209
210 if (um_pci_send_cmd(dev, &hdr, sizeof(hdr), NULL, 0, data, 8))
211 goto out;
212
213 switch (size) {
214 case 1:
215 ret = data[0];
216 break;
217 case 2:
218 ret = le16_to_cpup((void *)data);
219 break;
220 case 4:
221 ret = le32_to_cpup((void *)data);
222 break;
223 #ifdef CONFIG_64BIT
224 case 8:
225 ret = le64_to_cpup((void *)data);
226 break;
227 #endif
228 default:
229 break;
230 }
231
232 out:
233 put_cpu_var(um_pci_msg_bufs);
234 return ret;
235 }
236
um_pci_cfgspace_write(void * priv,unsigned int offset,int size,unsigned long val)237 static void um_pci_cfgspace_write(void *priv, unsigned int offset, int size,
238 unsigned long val)
239 {
240 struct um_pci_device_reg *reg = priv;
241 struct um_pci_device *dev = reg->dev;
242 struct {
243 struct virtio_pcidev_msg hdr;
244 /* maximum size - we may only use parts of it */
245 u8 data[8];
246 } msg = {
247 .hdr = {
248 .op = VIRTIO_PCIDEV_OP_CFG_WRITE,
249 .size = size,
250 .addr = offset,
251 },
252 };
253
254 if (!dev)
255 return;
256
257 switch (size) {
258 case 1:
259 msg.data[0] = (u8)val;
260 break;
261 case 2:
262 put_unaligned_le16(val, (void *)msg.data);
263 break;
264 case 4:
265 put_unaligned_le32(val, (void *)msg.data);
266 break;
267 #ifdef CONFIG_64BIT
268 case 8:
269 put_unaligned_le64(val, (void *)msg.data);
270 break;
271 #endif
272 default:
273 WARN(1, "invalid config space write size %d\n", size);
274 return;
275 }
276
277 WARN_ON(um_pci_send_cmd(dev, &msg.hdr, sizeof(msg), NULL, 0, NULL, 0));
278 }
279
280 static const struct logic_iomem_ops um_pci_device_cfgspace_ops = {
281 .read = um_pci_cfgspace_read,
282 .write = um_pci_cfgspace_write,
283 };
284
um_pci_bar_copy_from(void * priv,void * buffer,unsigned int offset,int size)285 static void um_pci_bar_copy_from(void *priv, void *buffer,
286 unsigned int offset, int size)
287 {
288 u8 *resptr = priv;
289 struct um_pci_device *dev = container_of(resptr - *resptr,
290 struct um_pci_device,
291 resptr[0]);
292 struct virtio_pcidev_msg hdr = {
293 .op = VIRTIO_PCIDEV_OP_MMIO_READ,
294 .bar = *resptr,
295 .size = size,
296 .addr = offset,
297 };
298
299 memset(buffer, 0xff, size);
300
301 um_pci_send_cmd(dev, &hdr, sizeof(hdr), NULL, 0, buffer, size);
302 }
303
um_pci_bar_read(void * priv,unsigned int offset,int size)304 static unsigned long um_pci_bar_read(void *priv, unsigned int offset,
305 int size)
306 {
307 /* buf->data is maximum size - we may only use parts of it */
308 struct um_pci_message_buffer *buf;
309 u8 *data;
310 unsigned long ret = ULONG_MAX;
311
312 buf = get_cpu_var(um_pci_msg_bufs);
313 data = buf->data;
314
315 switch (size) {
316 case 1:
317 case 2:
318 case 4:
319 #ifdef CONFIG_64BIT
320 case 8:
321 #endif
322 break;
323 default:
324 WARN(1, "invalid config space read size %d\n", size);
325 goto out;
326 }
327
328 um_pci_bar_copy_from(priv, data, offset, size);
329
330 switch (size) {
331 case 1:
332 ret = data[0];
333 break;
334 case 2:
335 ret = le16_to_cpup((void *)data);
336 break;
337 case 4:
338 ret = le32_to_cpup((void *)data);
339 break;
340 #ifdef CONFIG_64BIT
341 case 8:
342 ret = le64_to_cpup((void *)data);
343 break;
344 #endif
345 default:
346 break;
347 }
348
349 out:
350 put_cpu_var(um_pci_msg_bufs);
351 return ret;
352 }
353
um_pci_bar_copy_to(void * priv,unsigned int offset,const void * buffer,int size)354 static void um_pci_bar_copy_to(void *priv, unsigned int offset,
355 const void *buffer, int size)
356 {
357 u8 *resptr = priv;
358 struct um_pci_device *dev = container_of(resptr - *resptr,
359 struct um_pci_device,
360 resptr[0]);
361 struct virtio_pcidev_msg hdr = {
362 .op = VIRTIO_PCIDEV_OP_MMIO_WRITE,
363 .bar = *resptr,
364 .size = size,
365 .addr = offset,
366 };
367
368 um_pci_send_cmd(dev, &hdr, sizeof(hdr), buffer, size, NULL, 0);
369 }
370
um_pci_bar_write(void * priv,unsigned int offset,int size,unsigned long val)371 static void um_pci_bar_write(void *priv, unsigned int offset, int size,
372 unsigned long val)
373 {
374 /* maximum size - we may only use parts of it */
375 u8 data[8];
376
377 switch (size) {
378 case 1:
379 data[0] = (u8)val;
380 break;
381 case 2:
382 put_unaligned_le16(val, (void *)data);
383 break;
384 case 4:
385 put_unaligned_le32(val, (void *)data);
386 break;
387 #ifdef CONFIG_64BIT
388 case 8:
389 put_unaligned_le64(val, (void *)data);
390 break;
391 #endif
392 default:
393 WARN(1, "invalid config space write size %d\n", size);
394 return;
395 }
396
397 um_pci_bar_copy_to(priv, offset, data, size);
398 }
399
um_pci_bar_set(void * priv,unsigned int offset,u8 value,int size)400 static void um_pci_bar_set(void *priv, unsigned int offset, u8 value, int size)
401 {
402 u8 *resptr = priv;
403 struct um_pci_device *dev = container_of(resptr - *resptr,
404 struct um_pci_device,
405 resptr[0]);
406 struct {
407 struct virtio_pcidev_msg hdr;
408 u8 data;
409 } msg = {
410 .hdr = {
411 .op = VIRTIO_PCIDEV_OP_CFG_WRITE,
412 .bar = *resptr,
413 .size = size,
414 .addr = offset,
415 },
416 .data = value,
417 };
418
419 um_pci_send_cmd(dev, &msg.hdr, sizeof(msg), NULL, 0, NULL, 0);
420 }
421
422 static const struct logic_iomem_ops um_pci_device_bar_ops = {
423 .read = um_pci_bar_read,
424 .write = um_pci_bar_write,
425 .set = um_pci_bar_set,
426 .copy_from = um_pci_bar_copy_from,
427 .copy_to = um_pci_bar_copy_to,
428 };
429
um_pci_map_bus(struct pci_bus * bus,unsigned int devfn,int where)430 static void __iomem *um_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
431 int where)
432 {
433 struct um_pci_device_reg *dev;
434 unsigned int busn = bus->number;
435
436 if (busn > 0)
437 return NULL;
438
439 /* not allowing functions for now ... */
440 if (devfn % 8)
441 return NULL;
442
443 if (devfn / 8 >= ARRAY_SIZE(um_pci_devices))
444 return NULL;
445
446 dev = &um_pci_devices[devfn / 8];
447 if (!dev)
448 return NULL;
449
450 return (void __iomem *)((unsigned long)dev->iomem + where);
451 }
452
453 static struct pci_ops um_pci_ops = {
454 .map_bus = um_pci_map_bus,
455 .read = pci_generic_config_read,
456 .write = pci_generic_config_write,
457 };
458
um_pci_rescan(void)459 static void um_pci_rescan(void)
460 {
461 pci_lock_rescan_remove();
462 pci_rescan_bus(bridge->bus);
463 pci_unlock_rescan_remove();
464 }
465
um_pci_irq_vq_addbuf(struct virtqueue * vq,void * buf,bool kick)466 static void um_pci_irq_vq_addbuf(struct virtqueue *vq, void *buf, bool kick)
467 {
468 struct scatterlist sg[1];
469
470 sg_init_one(sg, buf, MAX_IRQ_MSG_SIZE);
471 if (virtqueue_add_inbuf(vq, sg, 1, buf, GFP_ATOMIC))
472 kfree(buf);
473 else if (kick)
474 virtqueue_kick(vq);
475 }
476
um_pci_handle_irq_message(struct virtqueue * vq,struct virtio_pcidev_msg * msg)477 static void um_pci_handle_irq_message(struct virtqueue *vq,
478 struct virtio_pcidev_msg *msg)
479 {
480 struct virtio_device *vdev = vq->vdev;
481 struct um_pci_device *dev = vdev->priv;
482
483 /* we should properly chain interrupts, but on ARCH=um we don't care */
484
485 switch (msg->op) {
486 case VIRTIO_PCIDEV_OP_INT:
487 generic_handle_irq(dev->irq);
488 break;
489 case VIRTIO_PCIDEV_OP_MSI:
490 /* our MSI message is just the interrupt number */
491 if (msg->size == sizeof(u32))
492 generic_handle_irq(le32_to_cpup((void *)msg->data));
493 else
494 generic_handle_irq(le16_to_cpup((void *)msg->data));
495 break;
496 case VIRTIO_PCIDEV_OP_PME:
497 /* nothing to do - we already woke up due to the message */
498 break;
499 default:
500 dev_err(&vdev->dev, "unexpected virt-pci message %d\n", msg->op);
501 break;
502 }
503 }
504
um_pci_cmd_vq_cb(struct virtqueue * vq)505 static void um_pci_cmd_vq_cb(struct virtqueue *vq)
506 {
507 struct virtio_device *vdev = vq->vdev;
508 struct um_pci_device *dev = vdev->priv;
509 void *cmd;
510 int len;
511
512 if (test_bit(UM_PCI_STAT_WAITING, &dev->status))
513 return;
514
515 while ((cmd = virtqueue_get_buf(vq, &len))) {
516 if (WARN_ON(HANDLE_IS_NO_FREE(cmd)))
517 continue;
518 kfree(cmd);
519 }
520 }
521
um_pci_irq_vq_cb(struct virtqueue * vq)522 static void um_pci_irq_vq_cb(struct virtqueue *vq)
523 {
524 struct virtio_pcidev_msg *msg;
525 int len;
526
527 while ((msg = virtqueue_get_buf(vq, &len))) {
528 if (len >= sizeof(*msg))
529 um_pci_handle_irq_message(vq, msg);
530
531 /* recycle the message buffer */
532 um_pci_irq_vq_addbuf(vq, msg, true);
533 }
534 }
535
um_pci_init_vqs(struct um_pci_device * dev)536 static int um_pci_init_vqs(struct um_pci_device *dev)
537 {
538 struct virtqueue *vqs[2];
539 static const char *const names[2] = { "cmd", "irq" };
540 vq_callback_t *cbs[2] = { um_pci_cmd_vq_cb, um_pci_irq_vq_cb };
541 int err, i;
542
543 err = virtio_find_vqs(dev->vdev, 2, vqs, cbs, names, NULL);
544 if (err)
545 return err;
546
547 dev->cmd_vq = vqs[0];
548 dev->irq_vq = vqs[1];
549
550 for (i = 0; i < NUM_IRQ_MSGS; i++) {
551 void *msg = kzalloc(MAX_IRQ_MSG_SIZE, GFP_KERNEL);
552
553 if (msg)
554 um_pci_irq_vq_addbuf(dev->irq_vq, msg, false);
555 }
556
557 virtqueue_kick(dev->irq_vq);
558
559 return 0;
560 }
561
um_pci_virtio_probe(struct virtio_device * vdev)562 static int um_pci_virtio_probe(struct virtio_device *vdev)
563 {
564 struct um_pci_device *dev;
565 int i, free = -1;
566 int err = -ENOSPC;
567
568 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
569 if (!dev)
570 return -ENOMEM;
571
572 dev->vdev = vdev;
573 vdev->priv = dev;
574
575 mutex_lock(&um_pci_mtx);
576 for (i = 0; i < MAX_DEVICES; i++) {
577 if (um_pci_devices[i].dev)
578 continue;
579 free = i;
580 break;
581 }
582
583 if (free < 0)
584 goto error;
585
586 err = um_pci_init_vqs(dev);
587 if (err)
588 goto error;
589
590 dev->irq = irq_alloc_desc(numa_node_id());
591 if (dev->irq < 0) {
592 err = dev->irq;
593 goto error;
594 }
595 um_pci_devices[free].dev = dev;
596 vdev->priv = dev;
597
598 mutex_unlock(&um_pci_mtx);
599
600 device_set_wakeup_enable(&vdev->dev, true);
601
602 /*
603 * In order to do suspend-resume properly, don't allow VQs
604 * to be suspended.
605 */
606 virtio_uml_set_no_vq_suspend(vdev, true);
607
608 um_pci_rescan();
609 return 0;
610 error:
611 mutex_unlock(&um_pci_mtx);
612 kfree(dev);
613 return err;
614 }
615
um_pci_virtio_remove(struct virtio_device * vdev)616 static void um_pci_virtio_remove(struct virtio_device *vdev)
617 {
618 struct um_pci_device *dev = vdev->priv;
619 int i;
620
621 device_set_wakeup_enable(&vdev->dev, false);
622
623 mutex_lock(&um_pci_mtx);
624 for (i = 0; i < MAX_DEVICES; i++) {
625 if (um_pci_devices[i].dev != dev)
626 continue;
627
628 um_pci_devices[i].dev = NULL;
629 irq_free_desc(dev->irq);
630
631 break;
632 }
633 mutex_unlock(&um_pci_mtx);
634
635 if (i < MAX_DEVICES) {
636 struct pci_dev *pci_dev;
637
638 pci_dev = pci_get_slot(bridge->bus, i);
639 if (pci_dev)
640 pci_stop_and_remove_bus_device_locked(pci_dev);
641 }
642
643 /* Stop all virtqueues */
644 virtio_reset_device(vdev);
645 dev->cmd_vq = NULL;
646 dev->irq_vq = NULL;
647 vdev->config->del_vqs(vdev);
648
649 kfree(dev);
650 }
651
652 static struct virtio_device_id id_table[] = {
653 { CONFIG_UML_PCI_OVER_VIRTIO_DEVICE_ID, VIRTIO_DEV_ANY_ID },
654 { 0 },
655 };
656 MODULE_DEVICE_TABLE(virtio, id_table);
657
658 static struct virtio_driver um_pci_virtio_driver = {
659 .driver.name = "virtio-pci",
660 .driver.owner = THIS_MODULE,
661 .id_table = id_table,
662 .probe = um_pci_virtio_probe,
663 .remove = um_pci_virtio_remove,
664 };
665
666 static struct resource virt_cfgspace_resource = {
667 .name = "PCI config space",
668 .start = 0xf0000000 - MAX_DEVICES * CFG_SPACE_SIZE,
669 .end = 0xf0000000 - 1,
670 .flags = IORESOURCE_MEM,
671 };
672
um_pci_map_cfgspace(unsigned long offset,size_t size,const struct logic_iomem_ops ** ops,void ** priv)673 static long um_pci_map_cfgspace(unsigned long offset, size_t size,
674 const struct logic_iomem_ops **ops,
675 void **priv)
676 {
677 if (WARN_ON(size > CFG_SPACE_SIZE || offset % CFG_SPACE_SIZE))
678 return -EINVAL;
679
680 if (offset / CFG_SPACE_SIZE < MAX_DEVICES) {
681 *ops = &um_pci_device_cfgspace_ops;
682 *priv = &um_pci_devices[offset / CFG_SPACE_SIZE];
683 return 0;
684 }
685
686 WARN(1, "cannot map offset 0x%lx/0x%zx\n", offset, size);
687 return -ENOENT;
688 }
689
690 static const struct logic_iomem_region_ops um_pci_cfgspace_ops = {
691 .map = um_pci_map_cfgspace,
692 };
693
694 static struct resource virt_iomem_resource = {
695 .name = "PCI iomem",
696 .start = 0xf0000000,
697 .end = 0xffffffff,
698 .flags = IORESOURCE_MEM,
699 };
700
701 struct um_pci_map_iomem_data {
702 unsigned long offset;
703 size_t size;
704 const struct logic_iomem_ops **ops;
705 void **priv;
706 long ret;
707 };
708
um_pci_map_iomem_walk(struct pci_dev * pdev,void * _data)709 static int um_pci_map_iomem_walk(struct pci_dev *pdev, void *_data)
710 {
711 struct um_pci_map_iomem_data *data = _data;
712 struct um_pci_device_reg *reg = &um_pci_devices[pdev->devfn / 8];
713 struct um_pci_device *dev;
714 int i;
715
716 if (!reg->dev)
717 return 0;
718
719 for (i = 0; i < ARRAY_SIZE(dev->resptr); i++) {
720 struct resource *r = &pdev->resource[i];
721
722 if ((r->flags & IORESOURCE_TYPE_BITS) != IORESOURCE_MEM)
723 continue;
724
725 /*
726 * must be the whole or part of the resource,
727 * not allowed to only overlap
728 */
729 if (data->offset < r->start || data->offset > r->end)
730 continue;
731 if (data->offset + data->size - 1 > r->end)
732 continue;
733
734 dev = reg->dev;
735 *data->ops = &um_pci_device_bar_ops;
736 dev->resptr[i] = i;
737 *data->priv = &dev->resptr[i];
738 data->ret = data->offset - r->start;
739
740 /* no need to continue */
741 return 1;
742 }
743
744 return 0;
745 }
746
um_pci_map_iomem(unsigned long offset,size_t size,const struct logic_iomem_ops ** ops,void ** priv)747 static long um_pci_map_iomem(unsigned long offset, size_t size,
748 const struct logic_iomem_ops **ops,
749 void **priv)
750 {
751 struct um_pci_map_iomem_data data = {
752 /* we want the full address here */
753 .offset = offset + virt_iomem_resource.start,
754 .size = size,
755 .ops = ops,
756 .priv = priv,
757 .ret = -ENOENT,
758 };
759
760 pci_walk_bus(bridge->bus, um_pci_map_iomem_walk, &data);
761 return data.ret;
762 }
763
764 static const struct logic_iomem_region_ops um_pci_iomem_ops = {
765 .map = um_pci_map_iomem,
766 };
767
um_pci_compose_msi_msg(struct irq_data * data,struct msi_msg * msg)768 static void um_pci_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
769 {
770 /*
771 * This is a very low address and not actually valid 'physical' memory
772 * in UML, so we can simply map MSI(-X) vectors to there, it cannot be
773 * legitimately written to by the device in any other way.
774 * We use the (virtual) IRQ number here as the message to simplify the
775 * code that receives the message, where for now we simply trust the
776 * device to send the correct message.
777 */
778 msg->address_hi = 0;
779 msg->address_lo = 0xa0000;
780 msg->data = data->irq;
781 }
782
783 static struct irq_chip um_pci_msi_bottom_irq_chip = {
784 .name = "UM virtio MSI",
785 .irq_compose_msi_msg = um_pci_compose_msi_msg,
786 };
787
um_pci_inner_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * args)788 static int um_pci_inner_domain_alloc(struct irq_domain *domain,
789 unsigned int virq, unsigned int nr_irqs,
790 void *args)
791 {
792 unsigned long bit;
793
794 WARN_ON(nr_irqs != 1);
795
796 mutex_lock(&um_pci_mtx);
797 bit = find_first_zero_bit(um_pci_msi_used, MAX_MSI_VECTORS);
798 if (bit >= MAX_MSI_VECTORS) {
799 mutex_unlock(&um_pci_mtx);
800 return -ENOSPC;
801 }
802
803 set_bit(bit, um_pci_msi_used);
804 mutex_unlock(&um_pci_mtx);
805
806 irq_domain_set_info(domain, virq, bit, &um_pci_msi_bottom_irq_chip,
807 domain->host_data, handle_simple_irq,
808 NULL, NULL);
809
810 return 0;
811 }
812
um_pci_inner_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)813 static void um_pci_inner_domain_free(struct irq_domain *domain,
814 unsigned int virq, unsigned int nr_irqs)
815 {
816 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
817
818 mutex_lock(&um_pci_mtx);
819
820 if (!test_bit(d->hwirq, um_pci_msi_used))
821 pr_err("trying to free unused MSI#%lu\n", d->hwirq);
822 else
823 __clear_bit(d->hwirq, um_pci_msi_used);
824
825 mutex_unlock(&um_pci_mtx);
826 }
827
828 static const struct irq_domain_ops um_pci_inner_domain_ops = {
829 .alloc = um_pci_inner_domain_alloc,
830 .free = um_pci_inner_domain_free,
831 };
832
833 static struct irq_chip um_pci_msi_irq_chip = {
834 .name = "UM virtio PCIe MSI",
835 .irq_mask = pci_msi_mask_irq,
836 .irq_unmask = pci_msi_unmask_irq,
837 };
838
839 static struct msi_domain_info um_pci_msi_domain_info = {
840 .flags = MSI_FLAG_USE_DEF_DOM_OPS |
841 MSI_FLAG_USE_DEF_CHIP_OPS |
842 MSI_FLAG_PCI_MSIX,
843 .chip = &um_pci_msi_irq_chip,
844 };
845
846 static struct resource busn_resource = {
847 .name = "PCI busn",
848 .start = 0,
849 .end = 0,
850 .flags = IORESOURCE_BUS,
851 };
852
um_pci_map_irq(const struct pci_dev * pdev,u8 slot,u8 pin)853 static int um_pci_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
854 {
855 struct um_pci_device_reg *reg = &um_pci_devices[pdev->devfn / 8];
856
857 if (WARN_ON(!reg->dev))
858 return -EINVAL;
859
860 /* Yes, we map all pins to the same IRQ ... doesn't matter for now. */
861 return reg->dev->irq;
862 }
863
pci_root_bus_fwnode(struct pci_bus * bus)864 void *pci_root_bus_fwnode(struct pci_bus *bus)
865 {
866 return um_pci_fwnode;
867 }
868
um_pci_init(void)869 static int um_pci_init(void)
870 {
871 int err, i;
872
873 WARN_ON(logic_iomem_add_region(&virt_cfgspace_resource,
874 &um_pci_cfgspace_ops));
875 WARN_ON(logic_iomem_add_region(&virt_iomem_resource,
876 &um_pci_iomem_ops));
877
878 if (WARN(CONFIG_UML_PCI_OVER_VIRTIO_DEVICE_ID < 0,
879 "No virtio device ID configured for PCI - no PCI support\n"))
880 return 0;
881
882 um_pci_msg_bufs = alloc_percpu(struct um_pci_message_buffer);
883 if (!um_pci_msg_bufs)
884 return -ENOMEM;
885
886 bridge = pci_alloc_host_bridge(0);
887 if (!bridge) {
888 err = -ENOMEM;
889 goto free;
890 }
891
892 um_pci_fwnode = irq_domain_alloc_named_fwnode("um-pci");
893 if (!um_pci_fwnode) {
894 err = -ENOMEM;
895 goto free;
896 }
897
898 um_pci_inner_domain = __irq_domain_add(um_pci_fwnode, MAX_MSI_VECTORS,
899 MAX_MSI_VECTORS, 0,
900 &um_pci_inner_domain_ops, NULL);
901 if (!um_pci_inner_domain) {
902 err = -ENOMEM;
903 goto free;
904 }
905
906 um_pci_msi_domain = pci_msi_create_irq_domain(um_pci_fwnode,
907 &um_pci_msi_domain_info,
908 um_pci_inner_domain);
909 if (!um_pci_msi_domain) {
910 err = -ENOMEM;
911 goto free;
912 }
913
914 pci_add_resource(&bridge->windows, &virt_iomem_resource);
915 pci_add_resource(&bridge->windows, &busn_resource);
916 bridge->ops = &um_pci_ops;
917 bridge->map_irq = um_pci_map_irq;
918
919 for (i = 0; i < MAX_DEVICES; i++) {
920 resource_size_t start;
921
922 start = virt_cfgspace_resource.start + i * CFG_SPACE_SIZE;
923 um_pci_devices[i].iomem = ioremap(start, CFG_SPACE_SIZE);
924 if (WARN(!um_pci_devices[i].iomem, "failed to map %d\n", i)) {
925 err = -ENOMEM;
926 goto free;
927 }
928 }
929
930 err = pci_host_probe(bridge);
931 if (err)
932 goto free;
933
934 err = register_virtio_driver(&um_pci_virtio_driver);
935 if (err)
936 goto free;
937 return 0;
938 free:
939 if (um_pci_inner_domain)
940 irq_domain_remove(um_pci_inner_domain);
941 if (um_pci_fwnode)
942 irq_domain_free_fwnode(um_pci_fwnode);
943 if (bridge) {
944 pci_free_resource_list(&bridge->windows);
945 pci_free_host_bridge(bridge);
946 }
947 free_percpu(um_pci_msg_bufs);
948 return err;
949 }
950 module_init(um_pci_init);
951
um_pci_exit(void)952 static void um_pci_exit(void)
953 {
954 unregister_virtio_driver(&um_pci_virtio_driver);
955 irq_domain_remove(um_pci_msi_domain);
956 irq_domain_remove(um_pci_inner_domain);
957 pci_free_resource_list(&bridge->windows);
958 pci_free_host_bridge(bridge);
959 free_percpu(um_pci_msg_bufs);
960 }
961 module_exit(um_pci_exit);
962