1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_H
3 #define __KVM_X86_VMX_H
4
5 #include <linux/kvm_host.h>
6
7 #include <asm/kvm.h>
8 #include <asm/intel_pt.h>
9
10 #include "capabilities.h"
11 #include "kvm_cache_regs.h"
12 #include "posted_intr.h"
13 #include "vmcs.h"
14 #include "vmx_ops.h"
15 #include "cpuid.h"
16 #include "run_flags.h"
17
18 #define MSR_TYPE_R 1
19 #define MSR_TYPE_W 2
20 #define MSR_TYPE_RW 3
21
22 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
23
24 #ifdef CONFIG_X86_64
25 #define MAX_NR_USER_RETURN_MSRS 7
26 #else
27 #define MAX_NR_USER_RETURN_MSRS 4
28 #endif
29
30 #define MAX_NR_LOADSTORE_MSRS 8
31
32 struct vmx_msrs {
33 unsigned int nr;
34 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS];
35 };
36
37 struct vmx_uret_msr {
38 bool load_into_hardware;
39 u64 data;
40 u64 mask;
41 };
42
43 enum segment_cache_field {
44 SEG_FIELD_SEL = 0,
45 SEG_FIELD_BASE = 1,
46 SEG_FIELD_LIMIT = 2,
47 SEG_FIELD_AR = 3,
48
49 SEG_FIELD_NR = 4
50 };
51
52 #define RTIT_ADDR_RANGE 4
53
54 struct pt_ctx {
55 u64 ctl;
56 u64 status;
57 u64 output_base;
58 u64 output_mask;
59 u64 cr3_match;
60 u64 addr_a[RTIT_ADDR_RANGE];
61 u64 addr_b[RTIT_ADDR_RANGE];
62 };
63
64 struct pt_desc {
65 u64 ctl_bitmask;
66 u32 addr_range;
67 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
68 struct pt_ctx host;
69 struct pt_ctx guest;
70 };
71
72 union vmx_exit_reason {
73 struct {
74 u32 basic : 16;
75 u32 reserved16 : 1;
76 u32 reserved17 : 1;
77 u32 reserved18 : 1;
78 u32 reserved19 : 1;
79 u32 reserved20 : 1;
80 u32 reserved21 : 1;
81 u32 reserved22 : 1;
82 u32 reserved23 : 1;
83 u32 reserved24 : 1;
84 u32 reserved25 : 1;
85 u32 bus_lock_detected : 1;
86 u32 enclave_mode : 1;
87 u32 smi_pending_mtf : 1;
88 u32 smi_from_vmx_root : 1;
89 u32 reserved30 : 1;
90 u32 failed_vmentry : 1;
91 };
92 u32 full;
93 };
94
intel_pmu_has_perf_global_ctrl(struct kvm_pmu * pmu)95 static inline bool intel_pmu_has_perf_global_ctrl(struct kvm_pmu *pmu)
96 {
97 /*
98 * Architecturally, Intel's SDM states that IA32_PERF_GLOBAL_CTRL is
99 * supported if "CPUID.0AH: EAX[7:0] > 0", i.e. if the PMU version is
100 * greater than zero. However, KVM only exposes and emulates the MSR
101 * to/for the guest if the guest PMU supports at least "Architectural
102 * Performance Monitoring Version 2".
103 */
104 return pmu->version > 1;
105 }
106
107 #define vcpu_to_lbr_desc(vcpu) (&to_vmx(vcpu)->lbr_desc)
108 #define vcpu_to_lbr_records(vcpu) (&to_vmx(vcpu)->lbr_desc.records)
109
110 bool intel_pmu_lbr_is_compatible(struct kvm_vcpu *vcpu);
111 bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu);
112
113 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu);
114 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu);
115
116 struct lbr_desc {
117 /* Basic info about guest LBR records. */
118 struct x86_pmu_lbr records;
119
120 /*
121 * Emulate LBR feature via passthrough LBR registers when the
122 * per-vcpu guest LBR event is scheduled on the current pcpu.
123 *
124 * The records may be inaccurate if the host reclaims the LBR.
125 */
126 struct perf_event *event;
127
128 /* True if LBRs are marked as not intercepted in the MSR bitmap */
129 bool msr_passthrough;
130 };
131
132 /*
133 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
134 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
135 */
136 struct nested_vmx {
137 /* Has the level1 guest done vmxon? */
138 bool vmxon;
139 gpa_t vmxon_ptr;
140 bool pml_full;
141
142 /* The guest-physical address of the current VMCS L1 keeps for L2 */
143 gpa_t current_vmptr;
144 /*
145 * Cache of the guest's VMCS, existing outside of guest memory.
146 * Loaded from guest memory during VMPTRLD. Flushed to guest
147 * memory during VMCLEAR and VMPTRLD.
148 */
149 struct vmcs12 *cached_vmcs12;
150 /*
151 * Cache of the guest's shadow VMCS, existing outside of guest
152 * memory. Loaded from guest memory during VM entry. Flushed
153 * to guest memory during VM exit.
154 */
155 struct vmcs12 *cached_shadow_vmcs12;
156
157 /*
158 * Indicates if the shadow vmcs or enlightened vmcs must be updated
159 * with the data held by struct vmcs12.
160 */
161 bool need_vmcs12_to_shadow_sync;
162 bool dirty_vmcs12;
163
164 /*
165 * Indicates lazily loaded guest state has not yet been decached from
166 * vmcs02.
167 */
168 bool need_sync_vmcs02_to_vmcs12_rare;
169
170 /*
171 * vmcs02 has been initialized, i.e. state that is constant for
172 * vmcs02 has been written to the backing VMCS. Initialization
173 * is delayed until L1 actually attempts to run a nested VM.
174 */
175 bool vmcs02_initialized;
176
177 bool change_vmcs01_virtual_apic_mode;
178 bool reload_vmcs01_apic_access_page;
179 bool update_vmcs01_cpu_dirty_logging;
180 bool update_vmcs01_apicv_status;
181
182 /*
183 * Enlightened VMCS has been enabled. It does not mean that L1 has to
184 * use it. However, VMX features available to L1 will be limited based
185 * on what the enlightened VMCS supports.
186 */
187 bool enlightened_vmcs_enabled;
188
189 /* L2 must run next, and mustn't decide to exit to L1. */
190 bool nested_run_pending;
191
192 /* Pending MTF VM-exit into L1. */
193 bool mtf_pending;
194
195 struct loaded_vmcs vmcs02;
196
197 /*
198 * Guest pages referred to in the vmcs02 with host-physical
199 * pointers, so we must keep them pinned while L2 runs.
200 */
201 struct page *apic_access_page;
202 struct kvm_host_map virtual_apic_map;
203 struct kvm_host_map pi_desc_map;
204
205 struct kvm_host_map msr_bitmap_map;
206
207 struct pi_desc *pi_desc;
208 bool pi_pending;
209 u16 posted_intr_nv;
210
211 struct hrtimer preemption_timer;
212 u64 preemption_timer_deadline;
213 bool has_preemption_timer_deadline;
214 bool preemption_timer_expired;
215
216 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
217 u64 vmcs01_debugctl;
218 u64 vmcs01_guest_bndcfgs;
219
220 /* to migrate it to L1 if L2 writes to L1's CR8 directly */
221 int l1_tpr_threshold;
222
223 u16 vpid02;
224 u16 last_vpid;
225
226 struct nested_vmx_msrs msrs;
227
228 /* SMM related state */
229 struct {
230 /* in VMX operation on SMM entry? */
231 bool vmxon;
232 /* in guest mode on SMM entry? */
233 bool guest_mode;
234 } smm;
235
236 gpa_t hv_evmcs_vmptr;
237 struct kvm_host_map hv_evmcs_map;
238 struct hv_enlightened_vmcs *hv_evmcs;
239 };
240
241 struct vcpu_vmx {
242 struct kvm_vcpu vcpu;
243 u8 fail;
244 u8 x2apic_msr_bitmap_mode;
245
246 /*
247 * If true, host state has been stored in vmx->loaded_vmcs for
248 * the CPU registers that only need to be switched when transitioning
249 * to/from the kernel, and the registers have been loaded with guest
250 * values. If false, host state is loaded in the CPU registers
251 * and vmx->loaded_vmcs->host_state is invalid.
252 */
253 bool guest_state_loaded;
254
255 unsigned long exit_qualification;
256 u32 exit_intr_info;
257 u32 idt_vectoring_info;
258 ulong rflags;
259
260 /*
261 * User return MSRs are always emulated when enabled in the guest, but
262 * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside
263 * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to
264 * be loaded into hardware if those conditions aren't met.
265 */
266 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS];
267 bool guest_uret_msrs_loaded;
268 #ifdef CONFIG_X86_64
269 u64 msr_host_kernel_gs_base;
270 u64 msr_guest_kernel_gs_base;
271 #endif
272
273 u64 spec_ctrl;
274 u32 msr_ia32_umwait_control;
275
276 /*
277 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
278 * non-nested (L1) guest, it always points to vmcs01. For a nested
279 * guest (L2), it points to a different VMCS.
280 */
281 struct loaded_vmcs vmcs01;
282 struct loaded_vmcs *loaded_vmcs;
283
284 struct msr_autoload {
285 struct vmx_msrs guest;
286 struct vmx_msrs host;
287 } msr_autoload;
288
289 struct msr_autostore {
290 struct vmx_msrs guest;
291 } msr_autostore;
292
293 struct {
294 int vm86_active;
295 ulong save_rflags;
296 struct kvm_segment segs[8];
297 } rmode;
298 struct {
299 u32 bitmask; /* 4 bits per segment (1 bit per field) */
300 struct kvm_save_segment {
301 u16 selector;
302 unsigned long base;
303 u32 limit;
304 u32 ar;
305 } seg[8];
306 } segment_cache;
307 int vpid;
308 bool emulation_required;
309
310 union vmx_exit_reason exit_reason;
311
312 /* Posted interrupt descriptor */
313 struct pi_desc pi_desc;
314
315 /* Support for a guest hypervisor (nested VMX) */
316 struct nested_vmx nested;
317
318 /* Dynamic PLE window. */
319 unsigned int ple_window;
320 bool ple_window_dirty;
321
322 bool req_immediate_exit;
323
324 /* Support for PML */
325 #define PML_ENTITY_NUM 512
326 struct page *pml_pg;
327
328 /* apic deadline value in host tsc */
329 u64 hv_deadline_tsc;
330
331 unsigned long host_debugctlmsr;
332
333 /*
334 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
335 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
336 * in msr_ia32_feature_control_valid_bits.
337 */
338 u64 msr_ia32_feature_control;
339 u64 msr_ia32_feature_control_valid_bits;
340 /* SGX Launch Control public key hash */
341 u64 msr_ia32_sgxlepubkeyhash[4];
342 u64 msr_ia32_mcu_opt_ctrl;
343 bool disable_fb_clear;
344
345 struct pt_desc pt_desc;
346 struct lbr_desc lbr_desc;
347
348 /* Save desired MSR intercept (read: pass-through) state */
349 #define MAX_POSSIBLE_PASSTHROUGH_MSRS 13
350 struct {
351 DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
352 DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
353 } shadow_msr_intercept;
354 };
355
356 struct kvm_vmx {
357 struct kvm kvm;
358
359 unsigned int tss_addr;
360 bool ept_identity_pagetable_done;
361 gpa_t ept_identity_map_addr;
362 };
363
364 bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
365 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
366 struct loaded_vmcs *buddy);
367 int allocate_vpid(void);
368 void free_vpid(int vpid);
369 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
370 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
371 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
372 unsigned long fs_base, unsigned long gs_base);
373 int vmx_get_cpl(struct kvm_vcpu *vcpu);
374 bool vmx_emulation_required(struct kvm_vcpu *vcpu);
375 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
376 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
377 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
378 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
379 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
380 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
381 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
382 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
383 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
384 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
385 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
386 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level);
387
388 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu);
389 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu);
390 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu);
391 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
392 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
393 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
394 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
395 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr);
396 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu);
397 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
398 void vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx, unsigned int flags);
399 unsigned int __vmx_vcpu_run_flags(struct vcpu_vmx *vmx);
400 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs,
401 unsigned int flags);
402 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr);
403 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu);
404
405 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type);
406 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type);
407
408 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu);
409 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu);
410
vmx_set_intercept_for_msr(struct kvm_vcpu * vcpu,u32 msr,int type,bool value)411 static inline void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr,
412 int type, bool value)
413 {
414 if (value)
415 vmx_enable_intercept_for_msr(vcpu, msr, type);
416 else
417 vmx_disable_intercept_for_msr(vcpu, msr, type);
418 }
419
420 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu);
421
vmx_test_msr_bitmap_read(ulong * msr_bitmap,u32 msr)422 static inline bool vmx_test_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
423 {
424 int f = sizeof(unsigned long);
425
426 if (msr <= 0x1fff)
427 return test_bit(msr, msr_bitmap + 0x000 / f);
428 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
429 return test_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
430 return true;
431 }
432
vmx_test_msr_bitmap_write(ulong * msr_bitmap,u32 msr)433 static inline bool vmx_test_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
434 {
435 int f = sizeof(unsigned long);
436
437 if (msr <= 0x1fff)
438 return test_bit(msr, msr_bitmap + 0x800 / f);
439 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
440 return test_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
441 return true;
442 }
443
vmx_clear_msr_bitmap_read(ulong * msr_bitmap,u32 msr)444 static inline void vmx_clear_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
445 {
446 int f = sizeof(unsigned long);
447
448 if (msr <= 0x1fff)
449 __clear_bit(msr, msr_bitmap + 0x000 / f);
450 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
451 __clear_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
452 }
453
vmx_clear_msr_bitmap_write(ulong * msr_bitmap,u32 msr)454 static inline void vmx_clear_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
455 {
456 int f = sizeof(unsigned long);
457
458 if (msr <= 0x1fff)
459 __clear_bit(msr, msr_bitmap + 0x800 / f);
460 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
461 __clear_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
462 }
463
vmx_set_msr_bitmap_read(ulong * msr_bitmap,u32 msr)464 static inline void vmx_set_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
465 {
466 int f = sizeof(unsigned long);
467
468 if (msr <= 0x1fff)
469 __set_bit(msr, msr_bitmap + 0x000 / f);
470 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
471 __set_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
472 }
473
vmx_set_msr_bitmap_write(ulong * msr_bitmap,u32 msr)474 static inline void vmx_set_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
475 {
476 int f = sizeof(unsigned long);
477
478 if (msr <= 0x1fff)
479 __set_bit(msr, msr_bitmap + 0x800 / f);
480 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
481 __set_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
482 }
483
484
vmx_get_rvi(void)485 static inline u8 vmx_get_rvi(void)
486 {
487 return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
488 }
489
490 #define BUILD_CONTROLS_SHADOW(lname, uname) \
491 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \
492 { \
493 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \
494 vmcs_write32(uname, val); \
495 vmx->loaded_vmcs->controls_shadow.lname = val; \
496 } \
497 } \
498 static inline u32 __##lname##_controls_get(struct loaded_vmcs *vmcs) \
499 { \
500 return vmcs->controls_shadow.lname; \
501 } \
502 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \
503 { \
504 return __##lname##_controls_get(vmx->loaded_vmcs); \
505 } \
506 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \
507 { \
508 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \
509 } \
510 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
511 { \
512 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \
513 }
BUILD_CONTROLS_SHADOW(vm_entry,VM_ENTRY_CONTROLS)514 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
515 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
516 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
517 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
518 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)
519
520 static inline void vmx_register_cache_reset(struct kvm_vcpu *vcpu)
521 {
522 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
523 | (1 << VCPU_EXREG_RFLAGS)
524 | (1 << VCPU_EXREG_PDPTR)
525 | (1 << VCPU_EXREG_SEGMENTS)
526 | (1 << VCPU_EXREG_CR0)
527 | (1 << VCPU_EXREG_CR3)
528 | (1 << VCPU_EXREG_CR4)
529 | (1 << VCPU_EXREG_EXIT_INFO_1)
530 | (1 << VCPU_EXREG_EXIT_INFO_2));
531 vcpu->arch.regs_dirty = 0;
532 }
533
to_kvm_vmx(struct kvm * kvm)534 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
535 {
536 return container_of(kvm, struct kvm_vmx, kvm);
537 }
538
to_vmx(struct kvm_vcpu * vcpu)539 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
540 {
541 return container_of(vcpu, struct vcpu_vmx, vcpu);
542 }
543
vmx_get_exit_qual(struct kvm_vcpu * vcpu)544 static inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu)
545 {
546 struct vcpu_vmx *vmx = to_vmx(vcpu);
547
548 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_1)) {
549 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
550 vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
551 }
552 return vmx->exit_qualification;
553 }
554
vmx_get_intr_info(struct kvm_vcpu * vcpu)555 static inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu)
556 {
557 struct vcpu_vmx *vmx = to_vmx(vcpu);
558
559 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_2)) {
560 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
561 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
562 }
563 return vmx->exit_intr_info;
564 }
565
566 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
567 void free_vmcs(struct vmcs *vmcs);
568 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
569 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
570 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
571
alloc_vmcs(bool shadow)572 static inline struct vmcs *alloc_vmcs(bool shadow)
573 {
574 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
575 GFP_KERNEL_ACCOUNT);
576 }
577
vmx_has_waitpkg(struct vcpu_vmx * vmx)578 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
579 {
580 return secondary_exec_controls_get(vmx) &
581 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
582 }
583
vmx_need_pf_intercept(struct kvm_vcpu * vcpu)584 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu)
585 {
586 if (!enable_ept)
587 return true;
588
589 return allow_smaller_maxphyaddr && cpuid_maxphyaddr(vcpu) < boot_cpu_data.x86_phys_bits;
590 }
591
is_unrestricted_guest(struct kvm_vcpu * vcpu)592 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu)
593 {
594 return enable_unrestricted_guest && (!is_guest_mode(vcpu) ||
595 (secondary_exec_controls_get(to_vmx(vcpu)) &
596 SECONDARY_EXEC_UNRESTRICTED_GUEST));
597 }
598
599 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu);
vmx_guest_state_valid(struct kvm_vcpu * vcpu)600 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu)
601 {
602 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu);
603 }
604
605 void dump_vmcs(struct kvm_vcpu *vcpu);
606
607 #endif /* __KVM_X86_VMX_H */
608