1 #include <linux/gfp.h>
2 #include <linux/initrd.h>
3 #include <linux/ioport.h>
4 #include <linux/swap.h>
5 #include <linux/memblock.h>
6 #include <linux/swapfile.h>
7 #include <linux/swapops.h>
8 #include <linux/kmemleak.h>
9 #include <linux/sched/task.h>
10
11 #include <asm/set_memory.h>
12 #include <asm/cpu_device_id.h>
13 #include <asm/e820/api.h>
14 #include <asm/init.h>
15 #include <asm/page.h>
16 #include <asm/page_types.h>
17 #include <asm/sections.h>
18 #include <asm/setup.h>
19 #include <asm/tlbflush.h>
20 #include <asm/tlb.h>
21 #include <asm/proto.h>
22 #include <asm/dma.h> /* for MAX_DMA_PFN */
23 #include <asm/microcode.h>
24 #include <asm/kaslr.h>
25 #include <asm/hypervisor.h>
26 #include <asm/cpufeature.h>
27 #include <asm/pti.h>
28 #include <asm/text-patching.h>
29 #include <asm/memtype.h>
30 #include <asm/paravirt.h>
31
32 /*
33 * We need to define the tracepoints somewhere, and tlb.c
34 * is only compiled when SMP=y.
35 */
36 #define CREATE_TRACE_POINTS
37 #include <trace/events/tlb.h>
38
39 #include "mm_internal.h"
40
41 /*
42 * Tables translating between page_cache_type_t and pte encoding.
43 *
44 * The default values are defined statically as minimal supported mode;
45 * WC and WT fall back to UC-. pat_init() updates these values to support
46 * more cache modes, WC and WT, when it is safe to do so. See pat_init()
47 * for the details. Note, __early_ioremap() used during early boot-time
48 * takes pgprot_t (pte encoding) and does not use these tables.
49 *
50 * Index into __cachemode2pte_tbl[] is the cachemode.
51 *
52 * Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte
53 * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2.
54 */
55 static uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
56 [_PAGE_CACHE_MODE_WB ] = 0 | 0 ,
57 [_PAGE_CACHE_MODE_WC ] = 0 | _PAGE_PCD,
58 [_PAGE_CACHE_MODE_UC_MINUS] = 0 | _PAGE_PCD,
59 [_PAGE_CACHE_MODE_UC ] = _PAGE_PWT | _PAGE_PCD,
60 [_PAGE_CACHE_MODE_WT ] = 0 | _PAGE_PCD,
61 [_PAGE_CACHE_MODE_WP ] = 0 | _PAGE_PCD,
62 };
63
cachemode2protval(enum page_cache_mode pcm)64 unsigned long cachemode2protval(enum page_cache_mode pcm)
65 {
66 if (likely(pcm == 0))
67 return 0;
68 return __cachemode2pte_tbl[pcm];
69 }
70 EXPORT_SYMBOL(cachemode2protval);
71
72 static uint8_t __pte2cachemode_tbl[8] = {
73 [__pte2cm_idx( 0 | 0 | 0 )] = _PAGE_CACHE_MODE_WB,
74 [__pte2cm_idx(_PAGE_PWT | 0 | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
75 [__pte2cm_idx( 0 | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC_MINUS,
76 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0 )] = _PAGE_CACHE_MODE_UC,
77 [__pte2cm_idx( 0 | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB,
78 [__pte2cm_idx(_PAGE_PWT | 0 | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
79 [__pte2cm_idx(0 | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
80 [__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC,
81 };
82
83 /*
84 * Check that the write-protect PAT entry is set for write-protect.
85 * To do this without making assumptions how PAT has been set up (Xen has
86 * another layout than the kernel), translate the _PAGE_CACHE_MODE_WP cache
87 * mode via the __cachemode2pte_tbl[] into protection bits (those protection
88 * bits will select a cache mode of WP or better), and then translate the
89 * protection bits back into the cache mode using __pte2cm_idx() and the
90 * __pte2cachemode_tbl[] array. This will return the really used cache mode.
91 */
x86_has_pat_wp(void)92 bool x86_has_pat_wp(void)
93 {
94 uint16_t prot = __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP];
95
96 return __pte2cachemode_tbl[__pte2cm_idx(prot)] == _PAGE_CACHE_MODE_WP;
97 }
98
pgprot2cachemode(pgprot_t pgprot)99 enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
100 {
101 unsigned long masked;
102
103 masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK;
104 if (likely(masked == 0))
105 return 0;
106 return __pte2cachemode_tbl[__pte2cm_idx(masked)];
107 }
108
109 static unsigned long __initdata pgt_buf_start;
110 static unsigned long __initdata pgt_buf_end;
111 static unsigned long __initdata pgt_buf_top;
112
113 static unsigned long min_pfn_mapped;
114
115 static bool __initdata can_use_brk_pgt = true;
116
117 /*
118 * Provide a run-time mean of disabling ZONE_DMA32 if it is enabled via
119 * CONFIG_ZONE_DMA32.
120 */
121 static bool disable_dma32 __ro_after_init;
122
123 /*
124 * Pages returned are already directly mapped.
125 *
126 * Changing that is likely to break Xen, see commit:
127 *
128 * 279b706 x86,xen: introduce x86_init.mapping.pagetable_reserve
129 *
130 * for detailed information.
131 */
alloc_low_pages(unsigned int num)132 __ref void *alloc_low_pages(unsigned int num)
133 {
134 unsigned long pfn;
135 int i;
136
137 if (after_bootmem) {
138 unsigned int order;
139
140 order = get_order((unsigned long)num << PAGE_SHIFT);
141 return (void *)__get_free_pages(GFP_ATOMIC | __GFP_ZERO, order);
142 }
143
144 if ((pgt_buf_end + num) > pgt_buf_top || !can_use_brk_pgt) {
145 unsigned long ret = 0;
146
147 if (min_pfn_mapped < max_pfn_mapped) {
148 ret = memblock_phys_alloc_range(
149 PAGE_SIZE * num, PAGE_SIZE,
150 min_pfn_mapped << PAGE_SHIFT,
151 max_pfn_mapped << PAGE_SHIFT);
152 }
153 if (!ret && can_use_brk_pgt)
154 ret = __pa(extend_brk(PAGE_SIZE * num, PAGE_SIZE));
155
156 if (!ret)
157 panic("alloc_low_pages: can not alloc memory");
158
159 pfn = ret >> PAGE_SHIFT;
160 } else {
161 pfn = pgt_buf_end;
162 pgt_buf_end += num;
163 }
164
165 for (i = 0; i < num; i++) {
166 void *adr;
167
168 adr = __va((pfn + i) << PAGE_SHIFT);
169 clear_page(adr);
170 }
171
172 return __va(pfn << PAGE_SHIFT);
173 }
174
175 /*
176 * By default need to be able to allocate page tables below PGD firstly for
177 * the 0-ISA_END_ADDRESS range and secondly for the initial PMD_SIZE mapping.
178 * With KASLR memory randomization, depending on the machine e820 memory and the
179 * PUD alignment, twice that many pages may be needed when KASLR memory
180 * randomization is enabled.
181 */
182
183 #ifndef CONFIG_X86_5LEVEL
184 #define INIT_PGD_PAGE_TABLES 3
185 #else
186 #define INIT_PGD_PAGE_TABLES 4
187 #endif
188
189 #ifndef CONFIG_RANDOMIZE_MEMORY
190 #define INIT_PGD_PAGE_COUNT (2 * INIT_PGD_PAGE_TABLES)
191 #else
192 #define INIT_PGD_PAGE_COUNT (4 * INIT_PGD_PAGE_TABLES)
193 #endif
194
195 #define INIT_PGT_BUF_SIZE (INIT_PGD_PAGE_COUNT * PAGE_SIZE)
196 RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE);
early_alloc_pgt_buf(void)197 void __init early_alloc_pgt_buf(void)
198 {
199 unsigned long tables = INIT_PGT_BUF_SIZE;
200 phys_addr_t base;
201
202 base = __pa(extend_brk(tables, PAGE_SIZE));
203
204 pgt_buf_start = base >> PAGE_SHIFT;
205 pgt_buf_end = pgt_buf_start;
206 pgt_buf_top = pgt_buf_start + (tables >> PAGE_SHIFT);
207 }
208
209 int after_bootmem;
210
211 early_param_on_off("gbpages", "nogbpages", direct_gbpages, CONFIG_X86_DIRECT_GBPAGES);
212
213 struct map_range {
214 unsigned long start;
215 unsigned long end;
216 unsigned page_size_mask;
217 };
218
219 static int page_size_mask;
220
221 /*
222 * Save some of cr4 feature set we're using (e.g. Pentium 4MB
223 * enable and PPro Global page enable), so that any CPU's that boot
224 * up after us can get the correct flags. Invoked on the boot CPU.
225 */
cr4_set_bits_and_update_boot(unsigned long mask)226 static inline void cr4_set_bits_and_update_boot(unsigned long mask)
227 {
228 mmu_cr4_features |= mask;
229 if (trampoline_cr4_features)
230 *trampoline_cr4_features = mmu_cr4_features;
231 cr4_set_bits(mask);
232 }
233
probe_page_size_mask(void)234 static void __init probe_page_size_mask(void)
235 {
236 /*
237 * For pagealloc debugging, identity mapping will use small pages.
238 * This will simplify cpa(), which otherwise needs to support splitting
239 * large pages into small in interrupt context, etc.
240 */
241 if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled())
242 page_size_mask |= 1 << PG_LEVEL_2M;
243 else
244 direct_gbpages = 0;
245
246 /* Enable PSE if available */
247 if (boot_cpu_has(X86_FEATURE_PSE))
248 cr4_set_bits_and_update_boot(X86_CR4_PSE);
249
250 /* Enable PGE if available */
251 __supported_pte_mask &= ~_PAGE_GLOBAL;
252 if (boot_cpu_has(X86_FEATURE_PGE)) {
253 cr4_set_bits_and_update_boot(X86_CR4_PGE);
254 __supported_pte_mask |= _PAGE_GLOBAL;
255 }
256
257 /* By the default is everything supported: */
258 __default_kernel_pte_mask = __supported_pte_mask;
259 /* Except when with PTI where the kernel is mostly non-Global: */
260 if (cpu_feature_enabled(X86_FEATURE_PTI))
261 __default_kernel_pte_mask &= ~_PAGE_GLOBAL;
262
263 /* Enable 1 GB linear kernel mappings if available: */
264 if (direct_gbpages && boot_cpu_has(X86_FEATURE_GBPAGES)) {
265 printk(KERN_INFO "Using GB pages for direct mapping\n");
266 page_size_mask |= 1 << PG_LEVEL_1G;
267 } else {
268 direct_gbpages = 0;
269 }
270 }
271
272 #define INTEL_MATCH(_model) { .vendor = X86_VENDOR_INTEL, \
273 .family = 6, \
274 .model = _model, \
275 }
276 /*
277 * INVLPG may not properly flush Global entries
278 * on these CPUs when PCIDs are enabled.
279 */
280 static const struct x86_cpu_id invlpg_miss_ids[] = {
281 INTEL_MATCH(INTEL_FAM6_ALDERLAKE ),
282 INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ),
283 INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ),
284 INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ),
285 INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P),
286 INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S),
287 {}
288 };
289
setup_pcid(void)290 static void setup_pcid(void)
291 {
292 if (!IS_ENABLED(CONFIG_X86_64))
293 return;
294
295 if (!boot_cpu_has(X86_FEATURE_PCID))
296 return;
297
298 if (x86_match_cpu(invlpg_miss_ids)) {
299 pr_info("Incomplete global flushes, disabling PCID");
300 setup_clear_cpu_cap(X86_FEATURE_PCID);
301 return;
302 }
303
304 if (boot_cpu_has(X86_FEATURE_PGE)) {
305 /*
306 * This can't be cr4_set_bits_and_update_boot() -- the
307 * trampoline code can't handle CR4.PCIDE and it wouldn't
308 * do any good anyway. Despite the name,
309 * cr4_set_bits_and_update_boot() doesn't actually cause
310 * the bits in question to remain set all the way through
311 * the secondary boot asm.
312 *
313 * Instead, we brute-force it and set CR4.PCIDE manually in
314 * start_secondary().
315 */
316 cr4_set_bits(X86_CR4_PCIDE);
317
318 /*
319 * INVPCID's single-context modes (2/3) only work if we set
320 * X86_CR4_PCIDE, *and* we INVPCID support. It's unusable
321 * on systems that have X86_CR4_PCIDE clear, or that have
322 * no INVPCID support at all.
323 */
324 if (boot_cpu_has(X86_FEATURE_INVPCID))
325 setup_force_cpu_cap(X86_FEATURE_INVPCID_SINGLE);
326 } else {
327 /*
328 * flush_tlb_all(), as currently implemented, won't work if
329 * PCID is on but PGE is not. Since that combination
330 * doesn't exist on real hardware, there's no reason to try
331 * to fully support it, but it's polite to avoid corrupting
332 * data if we're on an improperly configured VM.
333 */
334 setup_clear_cpu_cap(X86_FEATURE_PCID);
335 }
336 }
337
338 #ifdef CONFIG_X86_32
339 #define NR_RANGE_MR 3
340 #else /* CONFIG_X86_64 */
341 #define NR_RANGE_MR 5
342 #endif
343
save_mr(struct map_range * mr,int nr_range,unsigned long start_pfn,unsigned long end_pfn,unsigned long page_size_mask)344 static int __meminit save_mr(struct map_range *mr, int nr_range,
345 unsigned long start_pfn, unsigned long end_pfn,
346 unsigned long page_size_mask)
347 {
348 if (start_pfn < end_pfn) {
349 if (nr_range >= NR_RANGE_MR)
350 panic("run out of range for init_memory_mapping\n");
351 mr[nr_range].start = start_pfn<<PAGE_SHIFT;
352 mr[nr_range].end = end_pfn<<PAGE_SHIFT;
353 mr[nr_range].page_size_mask = page_size_mask;
354 nr_range++;
355 }
356
357 return nr_range;
358 }
359
360 /*
361 * adjust the page_size_mask for small range to go with
362 * big page size instead small one if nearby are ram too.
363 */
adjust_range_page_size_mask(struct map_range * mr,int nr_range)364 static void __ref adjust_range_page_size_mask(struct map_range *mr,
365 int nr_range)
366 {
367 int i;
368
369 for (i = 0; i < nr_range; i++) {
370 if ((page_size_mask & (1<<PG_LEVEL_2M)) &&
371 !(mr[i].page_size_mask & (1<<PG_LEVEL_2M))) {
372 unsigned long start = round_down(mr[i].start, PMD_SIZE);
373 unsigned long end = round_up(mr[i].end, PMD_SIZE);
374
375 #ifdef CONFIG_X86_32
376 if ((end >> PAGE_SHIFT) > max_low_pfn)
377 continue;
378 #endif
379
380 if (memblock_is_region_memory(start, end - start))
381 mr[i].page_size_mask |= 1<<PG_LEVEL_2M;
382 }
383 if ((page_size_mask & (1<<PG_LEVEL_1G)) &&
384 !(mr[i].page_size_mask & (1<<PG_LEVEL_1G))) {
385 unsigned long start = round_down(mr[i].start, PUD_SIZE);
386 unsigned long end = round_up(mr[i].end, PUD_SIZE);
387
388 if (memblock_is_region_memory(start, end - start))
389 mr[i].page_size_mask |= 1<<PG_LEVEL_1G;
390 }
391 }
392 }
393
page_size_string(struct map_range * mr)394 static const char *page_size_string(struct map_range *mr)
395 {
396 static const char str_1g[] = "1G";
397 static const char str_2m[] = "2M";
398 static const char str_4m[] = "4M";
399 static const char str_4k[] = "4k";
400
401 if (mr->page_size_mask & (1<<PG_LEVEL_1G))
402 return str_1g;
403 /*
404 * 32-bit without PAE has a 4M large page size.
405 * PG_LEVEL_2M is misnamed, but we can at least
406 * print out the right size in the string.
407 */
408 if (IS_ENABLED(CONFIG_X86_32) &&
409 !IS_ENABLED(CONFIG_X86_PAE) &&
410 mr->page_size_mask & (1<<PG_LEVEL_2M))
411 return str_4m;
412
413 if (mr->page_size_mask & (1<<PG_LEVEL_2M))
414 return str_2m;
415
416 return str_4k;
417 }
418
split_mem_range(struct map_range * mr,int nr_range,unsigned long start,unsigned long end)419 static int __meminit split_mem_range(struct map_range *mr, int nr_range,
420 unsigned long start,
421 unsigned long end)
422 {
423 unsigned long start_pfn, end_pfn, limit_pfn;
424 unsigned long pfn;
425 int i;
426
427 limit_pfn = PFN_DOWN(end);
428
429 /* head if not big page alignment ? */
430 pfn = start_pfn = PFN_DOWN(start);
431 #ifdef CONFIG_X86_32
432 /*
433 * Don't use a large page for the first 2/4MB of memory
434 * because there are often fixed size MTRRs in there
435 * and overlapping MTRRs into large pages can cause
436 * slowdowns.
437 */
438 if (pfn == 0)
439 end_pfn = PFN_DOWN(PMD_SIZE);
440 else
441 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
442 #else /* CONFIG_X86_64 */
443 end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
444 #endif
445 if (end_pfn > limit_pfn)
446 end_pfn = limit_pfn;
447 if (start_pfn < end_pfn) {
448 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
449 pfn = end_pfn;
450 }
451
452 /* big page (2M) range */
453 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
454 #ifdef CONFIG_X86_32
455 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
456 #else /* CONFIG_X86_64 */
457 end_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE));
458 if (end_pfn > round_down(limit_pfn, PFN_DOWN(PMD_SIZE)))
459 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
460 #endif
461
462 if (start_pfn < end_pfn) {
463 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
464 page_size_mask & (1<<PG_LEVEL_2M));
465 pfn = end_pfn;
466 }
467
468 #ifdef CONFIG_X86_64
469 /* big page (1G) range */
470 start_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE));
471 end_pfn = round_down(limit_pfn, PFN_DOWN(PUD_SIZE));
472 if (start_pfn < end_pfn) {
473 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
474 page_size_mask &
475 ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G)));
476 pfn = end_pfn;
477 }
478
479 /* tail is not big page (1G) alignment */
480 start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
481 end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
482 if (start_pfn < end_pfn) {
483 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
484 page_size_mask & (1<<PG_LEVEL_2M));
485 pfn = end_pfn;
486 }
487 #endif
488
489 /* tail is not big page (2M) alignment */
490 start_pfn = pfn;
491 end_pfn = limit_pfn;
492 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
493
494 if (!after_bootmem)
495 adjust_range_page_size_mask(mr, nr_range);
496
497 /* try to merge same page size and continuous */
498 for (i = 0; nr_range > 1 && i < nr_range - 1; i++) {
499 unsigned long old_start;
500 if (mr[i].end != mr[i+1].start ||
501 mr[i].page_size_mask != mr[i+1].page_size_mask)
502 continue;
503 /* move it */
504 old_start = mr[i].start;
505 memmove(&mr[i], &mr[i+1],
506 (nr_range - 1 - i) * sizeof(struct map_range));
507 mr[i--].start = old_start;
508 nr_range--;
509 }
510
511 for (i = 0; i < nr_range; i++)
512 pr_debug(" [mem %#010lx-%#010lx] page %s\n",
513 mr[i].start, mr[i].end - 1,
514 page_size_string(&mr[i]));
515
516 return nr_range;
517 }
518
519 struct range pfn_mapped[E820_MAX_ENTRIES];
520 int nr_pfn_mapped;
521
add_pfn_range_mapped(unsigned long start_pfn,unsigned long end_pfn)522 static void add_pfn_range_mapped(unsigned long start_pfn, unsigned long end_pfn)
523 {
524 nr_pfn_mapped = add_range_with_merge(pfn_mapped, E820_MAX_ENTRIES,
525 nr_pfn_mapped, start_pfn, end_pfn);
526 nr_pfn_mapped = clean_sort_range(pfn_mapped, E820_MAX_ENTRIES);
527
528 max_pfn_mapped = max(max_pfn_mapped, end_pfn);
529
530 if (start_pfn < (1UL<<(32-PAGE_SHIFT)))
531 max_low_pfn_mapped = max(max_low_pfn_mapped,
532 min(end_pfn, 1UL<<(32-PAGE_SHIFT)));
533 }
534
pfn_range_is_mapped(unsigned long start_pfn,unsigned long end_pfn)535 bool pfn_range_is_mapped(unsigned long start_pfn, unsigned long end_pfn)
536 {
537 int i;
538
539 for (i = 0; i < nr_pfn_mapped; i++)
540 if ((start_pfn >= pfn_mapped[i].start) &&
541 (end_pfn <= pfn_mapped[i].end))
542 return true;
543
544 return false;
545 }
546
547 /*
548 * Setup the direct mapping of the physical memory at PAGE_OFFSET.
549 * This runs before bootmem is initialized and gets pages directly from
550 * the physical memory. To access them they are temporarily mapped.
551 */
init_memory_mapping(unsigned long start,unsigned long end,pgprot_t prot)552 unsigned long __ref init_memory_mapping(unsigned long start,
553 unsigned long end, pgprot_t prot)
554 {
555 struct map_range mr[NR_RANGE_MR];
556 unsigned long ret = 0;
557 int nr_range, i;
558
559 pr_debug("init_memory_mapping: [mem %#010lx-%#010lx]\n",
560 start, end - 1);
561
562 memset(mr, 0, sizeof(mr));
563 nr_range = split_mem_range(mr, 0, start, end);
564
565 for (i = 0; i < nr_range; i++)
566 ret = kernel_physical_mapping_init(mr[i].start, mr[i].end,
567 mr[i].page_size_mask,
568 prot);
569
570 add_pfn_range_mapped(start >> PAGE_SHIFT, ret >> PAGE_SHIFT);
571
572 return ret >> PAGE_SHIFT;
573 }
574
575 /*
576 * We need to iterate through the E820 memory map and create direct mappings
577 * for only E820_TYPE_RAM and E820_KERN_RESERVED regions. We cannot simply
578 * create direct mappings for all pfns from [0 to max_low_pfn) and
579 * [4GB to max_pfn) because of possible memory holes in high addresses
580 * that cannot be marked as UC by fixed/variable range MTRRs.
581 * Depending on the alignment of E820 ranges, this may possibly result
582 * in using smaller size (i.e. 4K instead of 2M or 1G) page tables.
583 *
584 * init_mem_mapping() calls init_range_memory_mapping() with big range.
585 * That range would have hole in the middle or ends, and only ram parts
586 * will be mapped in init_range_memory_mapping().
587 */
init_range_memory_mapping(unsigned long r_start,unsigned long r_end)588 static unsigned long __init init_range_memory_mapping(
589 unsigned long r_start,
590 unsigned long r_end)
591 {
592 unsigned long start_pfn, end_pfn;
593 unsigned long mapped_ram_size = 0;
594 int i;
595
596 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) {
597 u64 start = clamp_val(PFN_PHYS(start_pfn), r_start, r_end);
598 u64 end = clamp_val(PFN_PHYS(end_pfn), r_start, r_end);
599 if (start >= end)
600 continue;
601
602 /*
603 * if it is overlapping with brk pgt, we need to
604 * alloc pgt buf from memblock instead.
605 */
606 can_use_brk_pgt = max(start, (u64)pgt_buf_end<<PAGE_SHIFT) >=
607 min(end, (u64)pgt_buf_top<<PAGE_SHIFT);
608 init_memory_mapping(start, end, PAGE_KERNEL);
609 mapped_ram_size += end - start;
610 can_use_brk_pgt = true;
611 }
612
613 return mapped_ram_size;
614 }
615
get_new_step_size(unsigned long step_size)616 static unsigned long __init get_new_step_size(unsigned long step_size)
617 {
618 /*
619 * Initial mapped size is PMD_SIZE (2M).
620 * We can not set step_size to be PUD_SIZE (1G) yet.
621 * In worse case, when we cross the 1G boundary, and
622 * PG_LEVEL_2M is not set, we will need 1+1+512 pages (2M + 8k)
623 * to map 1G range with PTE. Hence we use one less than the
624 * difference of page table level shifts.
625 *
626 * Don't need to worry about overflow in the top-down case, on 32bit,
627 * when step_size is 0, round_down() returns 0 for start, and that
628 * turns it into 0x100000000ULL.
629 * In the bottom-up case, round_up(x, 0) returns 0 though too, which
630 * needs to be taken into consideration by the code below.
631 */
632 return step_size << (PMD_SHIFT - PAGE_SHIFT - 1);
633 }
634
635 /**
636 * memory_map_top_down - Map [map_start, map_end) top down
637 * @map_start: start address of the target memory range
638 * @map_end: end address of the target memory range
639 *
640 * This function will setup direct mapping for memory range
641 * [map_start, map_end) in top-down. That said, the page tables
642 * will be allocated at the end of the memory, and we map the
643 * memory in top-down.
644 */
memory_map_top_down(unsigned long map_start,unsigned long map_end)645 static void __init memory_map_top_down(unsigned long map_start,
646 unsigned long map_end)
647 {
648 unsigned long real_end, last_start;
649 unsigned long step_size;
650 unsigned long addr;
651 unsigned long mapped_ram_size = 0;
652
653 /*
654 * Systems that have many reserved areas near top of the memory,
655 * e.g. QEMU with less than 1G RAM and EFI enabled, or Xen, will
656 * require lots of 4K mappings which may exhaust pgt_buf.
657 * Start with top-most PMD_SIZE range aligned at PMD_SIZE to ensure
658 * there is enough mapped memory that can be allocated from
659 * memblock.
660 */
661 addr = memblock_phys_alloc_range(PMD_SIZE, PMD_SIZE, map_start,
662 map_end);
663 memblock_free(addr, PMD_SIZE);
664 real_end = addr + PMD_SIZE;
665
666 /* step_size need to be small so pgt_buf from BRK could cover it */
667 step_size = PMD_SIZE;
668 max_pfn_mapped = 0; /* will get exact value next */
669 min_pfn_mapped = real_end >> PAGE_SHIFT;
670 last_start = real_end;
671
672 /*
673 * We start from the top (end of memory) and go to the bottom.
674 * The memblock_find_in_range() gets us a block of RAM from the
675 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages
676 * for page table.
677 */
678 while (last_start > map_start) {
679 unsigned long start;
680
681 if (last_start > step_size) {
682 start = round_down(last_start - 1, step_size);
683 if (start < map_start)
684 start = map_start;
685 } else
686 start = map_start;
687 mapped_ram_size += init_range_memory_mapping(start,
688 last_start);
689 last_start = start;
690 min_pfn_mapped = last_start >> PAGE_SHIFT;
691 if (mapped_ram_size >= step_size)
692 step_size = get_new_step_size(step_size);
693 }
694
695 if (real_end < map_end)
696 init_range_memory_mapping(real_end, map_end);
697 }
698
699 /**
700 * memory_map_bottom_up - Map [map_start, map_end) bottom up
701 * @map_start: start address of the target memory range
702 * @map_end: end address of the target memory range
703 *
704 * This function will setup direct mapping for memory range
705 * [map_start, map_end) in bottom-up. Since we have limited the
706 * bottom-up allocation above the kernel, the page tables will
707 * be allocated just above the kernel and we map the memory
708 * in [map_start, map_end) in bottom-up.
709 */
memory_map_bottom_up(unsigned long map_start,unsigned long map_end)710 static void __init memory_map_bottom_up(unsigned long map_start,
711 unsigned long map_end)
712 {
713 unsigned long next, start;
714 unsigned long mapped_ram_size = 0;
715 /* step_size need to be small so pgt_buf from BRK could cover it */
716 unsigned long step_size = PMD_SIZE;
717
718 start = map_start;
719 min_pfn_mapped = start >> PAGE_SHIFT;
720
721 /*
722 * We start from the bottom (@map_start) and go to the top (@map_end).
723 * The memblock_find_in_range() gets us a block of RAM from the
724 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages
725 * for page table.
726 */
727 while (start < map_end) {
728 if (step_size && map_end - start > step_size) {
729 next = round_up(start + 1, step_size);
730 if (next > map_end)
731 next = map_end;
732 } else {
733 next = map_end;
734 }
735
736 mapped_ram_size += init_range_memory_mapping(start, next);
737 start = next;
738
739 if (mapped_ram_size >= step_size)
740 step_size = get_new_step_size(step_size);
741 }
742 }
743
744 /*
745 * The real mode trampoline, which is required for bootstrapping CPUs
746 * occupies only a small area under the low 1MB. See reserve_real_mode()
747 * for details.
748 *
749 * If KASLR is disabled the first PGD entry of the direct mapping is copied
750 * to map the real mode trampoline.
751 *
752 * If KASLR is enabled, copy only the PUD which covers the low 1MB
753 * area. This limits the randomization granularity to 1GB for both 4-level
754 * and 5-level paging.
755 */
init_trampoline(void)756 static void __init init_trampoline(void)
757 {
758 #ifdef CONFIG_X86_64
759 if (!kaslr_memory_enabled())
760 trampoline_pgd_entry = init_top_pgt[pgd_index(__PAGE_OFFSET)];
761 else
762 init_trampoline_kaslr();
763 #endif
764 }
765
init_mem_mapping(void)766 void __init init_mem_mapping(void)
767 {
768 unsigned long end;
769
770 pti_check_boottime_disable();
771 probe_page_size_mask();
772 setup_pcid();
773
774 #ifdef CONFIG_X86_64
775 end = max_pfn << PAGE_SHIFT;
776 #else
777 end = max_low_pfn << PAGE_SHIFT;
778 #endif
779
780 /* the ISA range is always mapped regardless of memory holes */
781 init_memory_mapping(0, ISA_END_ADDRESS, PAGE_KERNEL);
782
783 /* Init the trampoline, possibly with KASLR memory offset */
784 init_trampoline();
785
786 /*
787 * If the allocation is in bottom-up direction, we setup direct mapping
788 * in bottom-up, otherwise we setup direct mapping in top-down.
789 */
790 if (memblock_bottom_up()) {
791 unsigned long kernel_end = __pa_symbol(_end);
792
793 /*
794 * we need two separate calls here. This is because we want to
795 * allocate page tables above the kernel. So we first map
796 * [kernel_end, end) to make memory above the kernel be mapped
797 * as soon as possible. And then use page tables allocated above
798 * the kernel to map [ISA_END_ADDRESS, kernel_end).
799 */
800 memory_map_bottom_up(kernel_end, end);
801 memory_map_bottom_up(ISA_END_ADDRESS, kernel_end);
802 } else {
803 memory_map_top_down(ISA_END_ADDRESS, end);
804 }
805
806 #ifdef CONFIG_X86_64
807 if (max_pfn > max_low_pfn) {
808 /* can we preserve max_low_pfn ?*/
809 max_low_pfn = max_pfn;
810 }
811 #else
812 early_ioremap_page_table_range_init();
813 #endif
814
815 load_cr3(swapper_pg_dir);
816 __flush_tlb_all();
817
818 x86_init.hyper.init_mem_mapping();
819
820 early_memtest(0, max_pfn_mapped << PAGE_SHIFT);
821 }
822
823 /*
824 * Initialize an mm_struct to be used during poking and a pointer to be used
825 * during patching.
826 */
poking_init(void)827 void __init poking_init(void)
828 {
829 spinlock_t *ptl;
830 pte_t *ptep;
831
832 poking_mm = mm_alloc();
833 BUG_ON(!poking_mm);
834
835 /* Xen PV guests need the PGD to be pinned. */
836 paravirt_arch_dup_mmap(NULL, poking_mm);
837
838 /*
839 * Randomize the poking address, but make sure that the following page
840 * will be mapped at the same PMD. We need 2 pages, so find space for 3,
841 * and adjust the address if the PMD ends after the first one.
842 */
843 poking_addr = TASK_UNMAPPED_BASE;
844 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
845 poking_addr += (kaslr_get_random_long("Poking") & PAGE_MASK) %
846 (TASK_SIZE - TASK_UNMAPPED_BASE - 3 * PAGE_SIZE);
847
848 if (((poking_addr + PAGE_SIZE) & ~PMD_MASK) == 0)
849 poking_addr += PAGE_SIZE;
850
851 /*
852 * We need to trigger the allocation of the page-tables that will be
853 * needed for poking now. Later, poking may be performed in an atomic
854 * section, which might cause allocation to fail.
855 */
856 ptep = get_locked_pte(poking_mm, poking_addr, &ptl);
857 BUG_ON(!ptep);
858 pte_unmap_unlock(ptep, ptl);
859 }
860
861 /*
862 * devmem_is_allowed() checks to see if /dev/mem access to a certain address
863 * is valid. The argument is a physical page number.
864 *
865 * On x86, access has to be given to the first megabyte of RAM because that
866 * area traditionally contains BIOS code and data regions used by X, dosemu,
867 * and similar apps. Since they map the entire memory range, the whole range
868 * must be allowed (for mapping), but any areas that would otherwise be
869 * disallowed are flagged as being "zero filled" instead of rejected.
870 * Access has to be given to non-kernel-ram areas as well, these contain the
871 * PCI mmio resources as well as potential bios/acpi data regions.
872 */
devmem_is_allowed(unsigned long pagenr)873 int devmem_is_allowed(unsigned long pagenr)
874 {
875 if (region_intersects(PFN_PHYS(pagenr), PAGE_SIZE,
876 IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE)
877 != REGION_DISJOINT) {
878 /*
879 * For disallowed memory regions in the low 1MB range,
880 * request that the page be shown as all zeros.
881 */
882 if (pagenr < 256)
883 return 2;
884
885 return 0;
886 }
887
888 /*
889 * This must follow RAM test, since System RAM is considered a
890 * restricted resource under CONFIG_STRICT_IOMEM.
891 */
892 if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) {
893 /* Low 1MB bypasses iomem restrictions. */
894 if (pagenr < 256)
895 return 1;
896
897 return 0;
898 }
899
900 return 1;
901 }
902
free_init_pages(const char * what,unsigned long begin,unsigned long end)903 void free_init_pages(const char *what, unsigned long begin, unsigned long end)
904 {
905 unsigned long begin_aligned, end_aligned;
906
907 /* Make sure boundaries are page aligned */
908 begin_aligned = PAGE_ALIGN(begin);
909 end_aligned = end & PAGE_MASK;
910
911 if (WARN_ON(begin_aligned != begin || end_aligned != end)) {
912 begin = begin_aligned;
913 end = end_aligned;
914 }
915
916 if (begin >= end)
917 return;
918
919 /*
920 * If debugging page accesses then do not free this memory but
921 * mark them not present - any buggy init-section access will
922 * create a kernel page fault:
923 */
924 if (debug_pagealloc_enabled()) {
925 pr_info("debug: unmapping init [mem %#010lx-%#010lx]\n",
926 begin, end - 1);
927 /*
928 * Inform kmemleak about the hole in the memory since the
929 * corresponding pages will be unmapped.
930 */
931 kmemleak_free_part((void *)begin, end - begin);
932 set_memory_np(begin, (end - begin) >> PAGE_SHIFT);
933 } else {
934 /*
935 * We just marked the kernel text read only above, now that
936 * we are going to free part of that, we need to make that
937 * writeable and non-executable first.
938 */
939 set_memory_nx(begin, (end - begin) >> PAGE_SHIFT);
940 set_memory_rw(begin, (end - begin) >> PAGE_SHIFT);
941
942 free_reserved_area((void *)begin, (void *)end,
943 POISON_FREE_INITMEM, what);
944 }
945 }
946
947 /*
948 * begin/end can be in the direct map or the "high kernel mapping"
949 * used for the kernel image only. free_init_pages() will do the
950 * right thing for either kind of address.
951 */
free_kernel_image_pages(const char * what,void * begin,void * end)952 void free_kernel_image_pages(const char *what, void *begin, void *end)
953 {
954 unsigned long begin_ul = (unsigned long)begin;
955 unsigned long end_ul = (unsigned long)end;
956 unsigned long len_pages = (end_ul - begin_ul) >> PAGE_SHIFT;
957
958 free_init_pages(what, begin_ul, end_ul);
959
960 /*
961 * PTI maps some of the kernel into userspace. For performance,
962 * this includes some kernel areas that do not contain secrets.
963 * Those areas might be adjacent to the parts of the kernel image
964 * being freed, which may contain secrets. Remove the "high kernel
965 * image mapping" for these freed areas, ensuring they are not even
966 * potentially vulnerable to Meltdown regardless of the specific
967 * optimizations PTI is currently using.
968 *
969 * The "noalias" prevents unmapping the direct map alias which is
970 * needed to access the freed pages.
971 *
972 * This is only valid for 64bit kernels. 32bit has only one mapping
973 * which can't be treated in this way for obvious reasons.
974 */
975 if (IS_ENABLED(CONFIG_X86_64) && cpu_feature_enabled(X86_FEATURE_PTI))
976 set_memory_np_noalias(begin_ul, len_pages);
977 }
978
free_initmem(void)979 void __ref free_initmem(void)
980 {
981 e820__reallocate_tables();
982
983 mem_encrypt_free_decrypted_mem();
984
985 free_kernel_image_pages("unused kernel image (initmem)",
986 &__init_begin, &__init_end);
987 }
988
989 #ifdef CONFIG_BLK_DEV_INITRD
free_initrd_mem(unsigned long start,unsigned long end)990 void __init free_initrd_mem(unsigned long start, unsigned long end)
991 {
992 /*
993 * end could be not aligned, and We can not align that,
994 * decompressor could be confused by aligned initrd_end
995 * We already reserve the end partial page before in
996 * - i386_start_kernel()
997 * - x86_64_start_kernel()
998 * - relocate_initrd()
999 * So here We can do PAGE_ALIGN() safely to get partial page to be freed
1000 */
1001 free_init_pages("initrd", start, PAGE_ALIGN(end));
1002 }
1003 #endif
1004
1005 /*
1006 * Calculate the precise size of the DMA zone (first 16 MB of RAM),
1007 * and pass it to the MM layer - to help it set zone watermarks more
1008 * accurately.
1009 *
1010 * Done on 64-bit systems only for the time being, although 32-bit systems
1011 * might benefit from this as well.
1012 */
memblock_find_dma_reserve(void)1013 void __init memblock_find_dma_reserve(void)
1014 {
1015 #ifdef CONFIG_X86_64
1016 u64 nr_pages = 0, nr_free_pages = 0;
1017 unsigned long start_pfn, end_pfn;
1018 phys_addr_t start_addr, end_addr;
1019 int i;
1020 u64 u;
1021
1022 /*
1023 * Iterate over all memory ranges (free and reserved ones alike),
1024 * to calculate the total number of pages in the first 16 MB of RAM:
1025 */
1026 nr_pages = 0;
1027 for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) {
1028 start_pfn = min(start_pfn, MAX_DMA_PFN);
1029 end_pfn = min(end_pfn, MAX_DMA_PFN);
1030
1031 nr_pages += end_pfn - start_pfn;
1032 }
1033
1034 /*
1035 * Iterate over free memory ranges to calculate the number of free
1036 * pages in the DMA zone, while not counting potential partial
1037 * pages at the beginning or the end of the range:
1038 */
1039 nr_free_pages = 0;
1040 for_each_free_mem_range(u, NUMA_NO_NODE, MEMBLOCK_NONE, &start_addr, &end_addr, NULL) {
1041 start_pfn = min_t(unsigned long, PFN_UP(start_addr), MAX_DMA_PFN);
1042 end_pfn = min_t(unsigned long, PFN_DOWN(end_addr), MAX_DMA_PFN);
1043
1044 if (start_pfn < end_pfn)
1045 nr_free_pages += end_pfn - start_pfn;
1046 }
1047
1048 set_dma_reserve(nr_pages - nr_free_pages);
1049 #endif
1050 }
1051
zone_sizes_init(void)1052 void __init zone_sizes_init(void)
1053 {
1054 unsigned long max_zone_pfns[MAX_NR_ZONES];
1055
1056 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1057
1058 #ifdef CONFIG_ZONE_DMA
1059 max_zone_pfns[ZONE_DMA] = min(MAX_DMA_PFN, max_low_pfn);
1060 #endif
1061 #ifdef CONFIG_ZONE_DMA32
1062 max_zone_pfns[ZONE_DMA32] = disable_dma32 ? 0 : min(MAX_DMA32_PFN, max_low_pfn);
1063 #endif
1064 max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
1065 #ifdef CONFIG_HIGHMEM
1066 max_zone_pfns[ZONE_HIGHMEM] = max_pfn;
1067 #endif
1068
1069 free_area_init(max_zone_pfns);
1070 }
1071
early_disable_dma32(char * buf)1072 static int __init early_disable_dma32(char *buf)
1073 {
1074 if (!buf)
1075 return -EINVAL;
1076
1077 if (!strcmp(buf, "on"))
1078 disable_dma32 = true;
1079
1080 return 0;
1081 }
1082 early_param("disable_dma32", early_disable_dma32);
1083
1084 __visible DEFINE_PER_CPU_ALIGNED(struct tlb_state, cpu_tlbstate) = {
1085 .loaded_mm = &init_mm,
1086 .next_asid = 1,
1087 .cr4 = ~0UL, /* fail hard if we screw up cr4 shadow initialization */
1088 };
1089
update_cache_mode_entry(unsigned entry,enum page_cache_mode cache)1090 void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache)
1091 {
1092 /* entry 0 MUST be WB (hardwired to speed up translations) */
1093 BUG_ON(!entry && cache != _PAGE_CACHE_MODE_WB);
1094
1095 __cachemode2pte_tbl[cache] = __cm_idx2pte(entry);
1096 __pte2cachemode_tbl[entry] = cache;
1097 }
1098
1099 #ifdef CONFIG_SWAP
max_swapfile_size(void)1100 unsigned long max_swapfile_size(void)
1101 {
1102 unsigned long pages;
1103
1104 pages = generic_max_swapfile_size();
1105
1106 if (boot_cpu_has_bug(X86_BUG_L1TF) && l1tf_mitigation != L1TF_MITIGATION_OFF) {
1107 /* Limit the swap file size to MAX_PA/2 for L1TF workaround */
1108 unsigned long long l1tf_limit = l1tf_pfn_limit();
1109 /*
1110 * We encode swap offsets also with 3 bits below those for pfn
1111 * which makes the usable limit higher.
1112 */
1113 #if CONFIG_PGTABLE_LEVELS > 2
1114 l1tf_limit <<= PAGE_SHIFT - SWP_OFFSET_FIRST_BIT;
1115 #endif
1116 pages = min_t(unsigned long long, l1tf_limit, pages);
1117 }
1118 return pages;
1119 }
1120 #endif
1121