1 /*
2 * mmp2 clock framework source file
3 *
4 * Copyright (C) 2012 Marvell
5 * Chao Xie <xiechao.mail@gmail.com>
6 * Copyright (C) 2020 Lubomir Rintel <lkundrak@v3.sk>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/spinlock.h>
16 #include <linux/io.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/of_address.h>
20 #include <linux/clk.h>
21
22 #include <dt-bindings/clock/marvell,mmp2.h>
23 #include <dt-bindings/power/marvell,mmp2.h>
24
25 #include "clk.h"
26 #include "reset.h"
27
28 #define APBC_RTC 0x0
29 #define APBC_TWSI0 0x4
30 #define APBC_TWSI1 0x8
31 #define APBC_TWSI2 0xc
32 #define APBC_TWSI3 0x10
33 #define APBC_TWSI4 0x7c
34 #define APBC_TWSI5 0x80
35 #define APBC_KPC 0x18
36 #define APBC_TIMER 0x24
37 #define APBC_UART0 0x2c
38 #define APBC_UART1 0x30
39 #define APBC_UART2 0x34
40 #define APBC_UART3 0x88
41 #define APBC_GPIO 0x38
42 #define APBC_PWM0 0x3c
43 #define APBC_PWM1 0x40
44 #define APBC_PWM2 0x44
45 #define APBC_PWM3 0x48
46 #define APBC_SSP0 0x50
47 #define APBC_SSP1 0x54
48 #define APBC_SSP2 0x58
49 #define APBC_SSP3 0x5c
50 #define APBC_THERMAL0 0x90
51 #define APBC_THERMAL1 0x98
52 #define APBC_THERMAL2 0x9c
53 #define APBC_THERMAL3 0xa0
54 #define APMU_SDH0 0x54
55 #define APMU_SDH1 0x58
56 #define APMU_SDH2 0xe8
57 #define APMU_SDH3 0xec
58 #define APMU_SDH4 0x15c
59 #define APMU_USB 0x5c
60 #define APMU_DISP0 0x4c
61 #define APMU_DISP1 0x110
62 #define APMU_CCIC0 0x50
63 #define APMU_CCIC1 0xf4
64 #define APMU_USBHSIC0 0xf8
65 #define APMU_USBHSIC1 0xfc
66 #define APMU_GPU 0xcc
67 #define APMU_AUDIO 0x10c
68 #define APMU_CAMERA 0x1fc
69
70 #define MPMU_FCCR 0x8
71 #define MPMU_POSR 0x10
72 #define MPMU_UART_PLL 0x14
73 #define MPMU_PLL2_CR 0x34
74 #define MPMU_I2S0_PLL 0x40
75 #define MPMU_I2S1_PLL 0x44
76 #define MPMU_ACGR 0x1024
77 /* MMP3 specific below */
78 #define MPMU_PLL3_CR 0x50
79 #define MPMU_PLL3_CTRL1 0x58
80 #define MPMU_PLL1_CTRL 0x5c
81 #define MPMU_PLL_DIFF_CTRL 0x68
82 #define MPMU_PLL2_CTRL1 0x414
83
84 enum mmp2_clk_model {
85 CLK_MODEL_MMP2,
86 CLK_MODEL_MMP3,
87 };
88
89 struct mmp2_clk_unit {
90 struct mmp_clk_unit unit;
91 enum mmp2_clk_model model;
92 struct genpd_onecell_data pd_data;
93 struct generic_pm_domain *pm_domains[MMP2_NR_POWER_DOMAINS];
94 void __iomem *mpmu_base;
95 void __iomem *apmu_base;
96 void __iomem *apbc_base;
97 };
98
99 static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
100 {MMP2_CLK_CLK32, "clk32", NULL, 0, 32768},
101 {MMP2_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
102 {MMP2_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
103 {0, "i2s_pll", NULL, 0, 99666667},
104 };
105
106 static struct mmp_param_pll_clk pll_clks[] = {
107 {MMP2_CLK_PLL1, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0},
108 {MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10},
109 };
110
111 static struct mmp_param_pll_clk mmp3_pll_clks[] = {
112 {MMP2_CLK_PLL2, "pll1", 797330000, MPMU_FCCR, 0x4000, MPMU_POSR, 0, 26000000, MPMU_PLL1_CTRL, 25},
113 {MMP2_CLK_PLL2, "pll2", 0, MPMU_PLL2_CR, 0x0300, MPMU_PLL2_CR, 10, 26000000, MPMU_PLL2_CTRL1, 25},
114 {MMP3_CLK_PLL1_P, "pll1_p", 0, MPMU_PLL_DIFF_CTRL, 0x0010, 0, 0, 797330000, MPMU_PLL_DIFF_CTRL, 0},
115 {MMP3_CLK_PLL2_P, "pll2_p", 0, MPMU_PLL_DIFF_CTRL, 0x0100, MPMU_PLL2_CR, 10, 26000000, MPMU_PLL_DIFF_CTRL, 5},
116 {MMP3_CLK_PLL3, "pll3", 0, MPMU_PLL3_CR, 0x0300, MPMU_PLL3_CR, 10, 26000000, MPMU_PLL3_CTRL1, 25},
117 };
118
119 static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
120 {MMP2_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0},
121 {MMP2_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0},
122 {MMP2_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0},
123 {MMP2_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0},
124 {MMP2_CLK_PLL1_20, "pll1_20", "pll1_4", 1, 5, 0},
125 {MMP2_CLK_PLL1_3, "pll1_3", "pll1", 1, 3, 0},
126 {MMP2_CLK_PLL1_6, "pll1_6", "pll1_3", 1, 2, 0},
127 {MMP2_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0},
128 {MMP2_CLK_PLL2_2, "pll2_2", "pll2", 1, 2, 0},
129 {MMP2_CLK_PLL2_4, "pll2_4", "pll2_2", 1, 2, 0},
130 {MMP2_CLK_PLL2_8, "pll2_8", "pll2_4", 1, 2, 0},
131 {MMP2_CLK_PLL2_16, "pll2_16", "pll2_8", 1, 2, 0},
132 {MMP2_CLK_PLL2_3, "pll2_3", "pll2", 1, 3, 0},
133 {MMP2_CLK_PLL2_6, "pll2_6", "pll2_3", 1, 2, 0},
134 {MMP2_CLK_PLL2_12, "pll2_12", "pll2_6", 1, 2, 0},
135 {MMP2_CLK_VCTCXO_2, "vctcxo_2", "vctcxo", 1, 2, 0},
136 {MMP2_CLK_VCTCXO_4, "vctcxo_4", "vctcxo_2", 1, 2, 0},
137 };
138
139 static struct mmp_clk_factor_masks uart_factor_masks = {
140 .factor = 2,
141 .num_mask = 0x1fff,
142 .den_mask = 0x1fff,
143 .num_shift = 16,
144 .den_shift = 0,
145 };
146
147 static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
148 {.num = 8125, .den = 1536}, /*14.745MHZ */
149 {.num = 3521, .den = 689}, /*19.23MHZ */
150 };
151
152 static struct mmp_clk_factor_masks i2s_factor_masks = {
153 .factor = 2,
154 .num_mask = 0x7fff,
155 .den_mask = 0x1fff,
156 .num_shift = 0,
157 .den_shift = 15,
158 .enable_mask = 0xd0000000,
159 };
160
161 static struct mmp_clk_factor_tbl i2s_factor_tbl[] = {
162 {.num = 24868, .den = 511}, /* 2.0480 MHz */
163 {.num = 28003, .den = 793}, /* 2.8224 MHz */
164 {.num = 24941, .den = 1025}, /* 4.0960 MHz */
165 {.num = 28003, .den = 1586}, /* 5.6448 MHz */
166 {.num = 31158, .den = 2561}, /* 8.1920 MHz */
167 {.num = 16288, .den = 1845}, /* 11.2896 MHz */
168 {.num = 20772, .den = 2561}, /* 12.2880 MHz */
169 {.num = 8144, .den = 1845}, /* 22.5792 MHz */
170 {.num = 10386, .den = 2561}, /* 24.5760 MHz */
171 };
172
173 static DEFINE_SPINLOCK(acgr_lock);
174
175 static struct mmp_param_gate_clk mpmu_gate_clks[] = {
176 {MMP2_CLK_I2S0, "i2s0_clk", "i2s0_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x200000, 0x200000, 0x0, 0, &acgr_lock},
177 {MMP2_CLK_I2S1, "i2s1_clk", "i2s1_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x100000, 0x100000, 0x0, 0, &acgr_lock},
178 };
179
mmp2_main_clk_init(struct mmp2_clk_unit * pxa_unit)180 static void mmp2_main_clk_init(struct mmp2_clk_unit *pxa_unit)
181 {
182 struct clk *clk;
183 struct mmp_clk_unit *unit = &pxa_unit->unit;
184
185 mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
186 ARRAY_SIZE(fixed_rate_clks));
187
188 if (pxa_unit->model == CLK_MODEL_MMP3) {
189 mmp_register_pll_clks(unit, mmp3_pll_clks,
190 pxa_unit->mpmu_base,
191 ARRAY_SIZE(mmp3_pll_clks));
192 } else {
193 mmp_register_pll_clks(unit, pll_clks,
194 pxa_unit->mpmu_base,
195 ARRAY_SIZE(pll_clks));
196 }
197
198 mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
199 ARRAY_SIZE(fixed_factor_clks));
200
201 clk = mmp_clk_register_factor("uart_pll", "pll1_4",
202 CLK_SET_RATE_PARENT,
203 pxa_unit->mpmu_base + MPMU_UART_PLL,
204 &uart_factor_masks, uart_factor_tbl,
205 ARRAY_SIZE(uart_factor_tbl), NULL);
206 mmp_clk_add(unit, MMP2_CLK_UART_PLL, clk);
207
208 mmp_clk_register_factor("i2s0_pll", "pll1_4",
209 CLK_SET_RATE_PARENT,
210 pxa_unit->mpmu_base + MPMU_I2S0_PLL,
211 &i2s_factor_masks, i2s_factor_tbl,
212 ARRAY_SIZE(i2s_factor_tbl), NULL);
213 mmp_clk_register_factor("i2s1_pll", "pll1_4",
214 CLK_SET_RATE_PARENT,
215 pxa_unit->mpmu_base + MPMU_I2S1_PLL,
216 &i2s_factor_masks, i2s_factor_tbl,
217 ARRAY_SIZE(i2s_factor_tbl), NULL);
218
219 mmp_register_gate_clks(unit, mpmu_gate_clks, pxa_unit->mpmu_base,
220 ARRAY_SIZE(mpmu_gate_clks));
221 }
222
223 static DEFINE_SPINLOCK(uart0_lock);
224 static DEFINE_SPINLOCK(uart1_lock);
225 static DEFINE_SPINLOCK(uart2_lock);
226 static const char * const uart_parent_names[] = {"uart_pll", "vctcxo"};
227
228 static DEFINE_SPINLOCK(ssp0_lock);
229 static DEFINE_SPINLOCK(ssp1_lock);
230 static DEFINE_SPINLOCK(ssp2_lock);
231 static DEFINE_SPINLOCK(ssp3_lock);
232 static const char * const ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
233
234 static DEFINE_SPINLOCK(timer_lock);
235 static const char * const timer_parent_names[] = {"clk32", "vctcxo_4", "vctcxo_2", "vctcxo"};
236
237 static DEFINE_SPINLOCK(reset_lock);
238
239 static struct mmp_param_mux_clk apbc_mux_clks[] = {
240 {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
241 {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
242 {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock},
243 {0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3, 4, 3, 0, &uart2_lock},
244 {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
245 {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
246 {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock},
247 {0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock},
248 {0, "timer_mux", timer_parent_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER, 4, 3, 0, &timer_lock},
249 };
250
251 static struct mmp_param_gate_clk apbc_gate_clks[] = {
252 {MMP2_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_lock},
253 {MMP2_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 0x3, 0x0, 0, &reset_lock},
254 {MMP2_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI2, 0x7, 0x3, 0x0, 0, &reset_lock},
255 {MMP2_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 0x3, 0x0, 0, &reset_lock},
256 {MMP2_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI4, 0x7, 0x3, 0x0, 0, &reset_lock},
257 {MMP2_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI5, 0x7, 0x3, 0x0, 0, &reset_lock},
258 {MMP2_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 0x3, 0x0, 0, &reset_lock},
259 {MMP2_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
260 {MMP2_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
261 {MMP2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lock},
262 {MMP2_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x7, 0x3, 0x0, 0, &reset_lock},
263 {MMP2_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x7, 0x3, 0x0, 0, &reset_lock},
264 {MMP2_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x7, 0x3, 0x0, 0, &reset_lock},
265 /* The gate clocks has mux parent. */
266 {MMP2_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 0x3, 0x0, 0, &uart0_lock},
267 {MMP2_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 0x3, 0x0, 0, &uart1_lock},
268 {MMP2_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock},
269 {MMP2_CLK_UART3, "uart3_clk", "uart3_mux", CLK_SET_RATE_PARENT, APBC_UART3, 0x7, 0x3, 0x0, 0, &uart2_lock},
270 {MMP2_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x7, 0x3, 0x0, 0, &ssp0_lock},
271 {MMP2_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x7, 0x3, 0x0, 0, &ssp1_lock},
272 {MMP2_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x7, 0x3, 0x0, 0, &ssp2_lock},
273 {MMP2_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x7, 0x3, 0x0, 0, &ssp3_lock},
274 {MMP2_CLK_TIMER, "timer_clk", "timer_mux", CLK_SET_RATE_PARENT, APBC_TIMER, 0x7, 0x3, 0x0, 0, &timer_lock},
275 {MMP2_CLK_THERMAL0, "thermal0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL0, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
276 };
277
278 static struct mmp_param_gate_clk mmp3_apbc_gate_clks[] = {
279 {MMP3_CLK_THERMAL1, "thermal1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL1, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
280 {MMP3_CLK_THERMAL2, "thermal2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL2, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
281 {MMP3_CLK_THERMAL3, "thermal3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL3, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
282 };
283
mmp2_apb_periph_clk_init(struct mmp2_clk_unit * pxa_unit)284 static void mmp2_apb_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
285 {
286 struct mmp_clk_unit *unit = &pxa_unit->unit;
287
288 mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
289 ARRAY_SIZE(apbc_mux_clks));
290
291 mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
292 ARRAY_SIZE(apbc_gate_clks));
293
294 if (pxa_unit->model == CLK_MODEL_MMP3) {
295 mmp_register_gate_clks(unit, mmp3_apbc_gate_clks, pxa_unit->apbc_base,
296 ARRAY_SIZE(mmp3_apbc_gate_clks));
297 }
298 }
299
300 static DEFINE_SPINLOCK(sdh_lock);
301 static const char * const sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
302 static struct mmp_clk_mix_config sdh_mix_config = {
303 .reg_info = DEFINE_MIX_REG_INFO(4, 10, 2, 8, 32),
304 };
305
306 static DEFINE_SPINLOCK(usb_lock);
307 static DEFINE_SPINLOCK(usbhsic0_lock);
308 static DEFINE_SPINLOCK(usbhsic1_lock);
309
310 static DEFINE_SPINLOCK(disp0_lock);
311 static DEFINE_SPINLOCK(disp1_lock);
312 static const char * const disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
313
314 static DEFINE_SPINLOCK(ccic0_lock);
315 static DEFINE_SPINLOCK(ccic1_lock);
316 static const char * const ccic_parent_names[] = {"pll1_2", "pll1_16", "vctcxo"};
317
318 static DEFINE_SPINLOCK(gpu_lock);
319 static const char * const mmp2_gpu_gc_parent_names[] = {"pll1_2", "pll1_3", "pll2_2", "pll2_3", "pll2", "usb_pll"};
320 static u32 mmp2_gpu_gc_parent_table[] = { 0x0000, 0x0040, 0x0080, 0x00c0, 0x1000, 0x1040 };
321 static const char * const mmp2_gpu_bus_parent_names[] = {"pll1_4", "pll2", "pll2_2", "usb_pll"};
322 static u32 mmp2_gpu_bus_parent_table[] = { 0x0000, 0x0020, 0x0030, 0x4020 };
323 static const char * const mmp3_gpu_bus_parent_names[] = {"pll1_4", "pll1_6", "pll1_2", "pll2_2"};
324 static const char * const mmp3_gpu_gc_parent_names[] = {"pll1", "pll2", "pll1_p", "pll2_p"};
325
326 static DEFINE_SPINLOCK(audio_lock);
327
328 static struct mmp_clk_mix_config ccic0_mix_config = {
329 .reg_info = DEFINE_MIX_REG_INFO(4, 17, 2, 6, 32),
330 };
331 static struct mmp_clk_mix_config ccic1_mix_config = {
332 .reg_info = DEFINE_MIX_REG_INFO(4, 16, 2, 6, 32),
333 };
334
335 static struct mmp_param_mux_clk apmu_mux_clks[] = {
336 {MMP2_CLK_DISP0_MUX, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 2, 0, &disp0_lock},
337 {MMP2_CLK_DISP1_MUX, "disp1_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP1, 6, 2, 0, &disp1_lock},
338 };
339
340 static struct mmp_param_mux_clk mmp3_apmu_mux_clks[] = {
341 {0, "gpu_bus_mux", mmp3_gpu_bus_parent_names, ARRAY_SIZE(mmp3_gpu_bus_parent_names),
342 CLK_SET_RATE_PARENT, APMU_GPU, 4, 2, 0, &gpu_lock},
343 {0, "gpu_3d_mux", mmp3_gpu_gc_parent_names, ARRAY_SIZE(mmp3_gpu_gc_parent_names),
344 CLK_SET_RATE_PARENT, APMU_GPU, 6, 2, 0, &gpu_lock},
345 {0, "gpu_2d_mux", mmp3_gpu_gc_parent_names, ARRAY_SIZE(mmp3_gpu_gc_parent_names),
346 CLK_SET_RATE_PARENT, APMU_GPU, 12, 2, 0, &gpu_lock},
347 };
348
349 static struct mmp_param_div_clk apmu_div_clks[] = {
350 {0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, CLK_DIVIDER_ONE_BASED, &disp0_lock},
351 {0, "disp0_sphy_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 15, 5, 0, &disp0_lock},
352 {0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, CLK_DIVIDER_ONE_BASED, &disp1_lock},
353 {0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
354 {0, "ccic1_sphy_div", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 10, 5, 0, &ccic1_lock},
355 };
356
357 static struct mmp_param_div_clk mmp3_apmu_div_clks[] = {
358 {0, "gpu_3d_div", "gpu_3d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 24, 4, 0, &gpu_lock},
359 {0, "gpu_2d_div", "gpu_2d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 28, 4, 0, &gpu_lock},
360 };
361
362 static struct mmp_param_gate_clk apmu_gate_clks[] = {
363 {MMP2_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
364 {MMP2_CLK_USBHSIC0, "usbhsic0_clk", "usb_pll", 0, APMU_USBHSIC0, 0x1b, 0x1b, 0x0, 0, &usbhsic0_lock},
365 {MMP2_CLK_USBHSIC1, "usbhsic1_clk", "usb_pll", 0, APMU_USBHSIC1, 0x1b, 0x1b, 0x0, 0, &usbhsic1_lock},
366 /* The gate clocks has mux parent. */
367 {MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
368 {MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
369 {MMP2_CLK_SDH2, "sdh2_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH2, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
370 {MMP2_CLK_SDH3, "sdh3_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH3, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
371 {MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x12, 0x12, 0x0, 0, &disp0_lock},
372 {MMP2_CLK_DISP0_LCDC, "disp0_lcdc_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x09, 0x09, 0x0, 0, &disp0_lock},
373 {MMP2_CLK_DISP0_SPHY, "disp0_sphy_clk", "disp0_sphy_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1024, 0x1024, 0x0, 0, &disp0_lock},
374 {MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x09, 0x09, 0x0, 0, &disp1_lock},
375 {MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800, 0x0, 0, &ccic0_lock},
376 {MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
377 {MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
378 {MMP2_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock},
379 {MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0, &ccic1_lock},
380 {MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock},
381 {MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_lock},
382 {MMP2_CLK_GPU_BUS, "gpu_bus_clk", "gpu_bus_mux", CLK_SET_RATE_PARENT, APMU_GPU, 0xa, 0xa, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
383 {MMP2_CLK_AUDIO, "audio_clk", "audio_mix_clk", CLK_SET_RATE_PARENT, APMU_AUDIO, 0x12, 0x12, 0x0, 0, &audio_lock},
384 };
385
386 static struct mmp_param_gate_clk mmp2_apmu_gate_clks[] = {
387 {MMP2_CLK_GPU_3D, "gpu_3d_clk", "gpu_3d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 0x5, 0x5, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
388 };
389
390 static struct mmp_param_gate_clk mmp3_apmu_gate_clks[] = {
391 {MMP3_CLK_SDH4, "sdh4_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH4, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
392 {MMP3_CLK_GPU_3D, "gpu_3d_clk", "gpu_3d_div", CLK_SET_RATE_PARENT, APMU_GPU, 0x5, 0x5, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
393 {MMP3_CLK_GPU_2D, "gpu_2d_clk", "gpu_2d_div", CLK_SET_RATE_PARENT, APMU_GPU, 0x1c0000, 0x1c0000, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
394 };
395
mmp2_axi_periph_clk_init(struct mmp2_clk_unit * pxa_unit)396 static void mmp2_axi_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
397 {
398 struct clk *clk;
399 struct mmp_clk_unit *unit = &pxa_unit->unit;
400
401 sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0;
402 clk = mmp_clk_register_mix(NULL, "sdh_mix_clk", sdh_parent_names,
403 ARRAY_SIZE(sdh_parent_names),
404 CLK_SET_RATE_PARENT,
405 &sdh_mix_config, &sdh_lock);
406
407 ccic0_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC0;
408 clk = mmp_clk_register_mix(NULL, "ccic0_mix_clk", ccic_parent_names,
409 ARRAY_SIZE(ccic_parent_names),
410 CLK_SET_RATE_PARENT,
411 &ccic0_mix_config, &ccic0_lock);
412 mmp_clk_add(unit, MMP2_CLK_CCIC0_MIX, clk);
413
414 ccic1_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC1;
415 clk = mmp_clk_register_mix(NULL, "ccic1_mix_clk", ccic_parent_names,
416 ARRAY_SIZE(ccic_parent_names),
417 CLK_SET_RATE_PARENT,
418 &ccic1_mix_config, &ccic1_lock);
419 mmp_clk_add(unit, MMP2_CLK_CCIC1_MIX, clk);
420
421 mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base,
422 ARRAY_SIZE(apmu_mux_clks));
423
424 mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base,
425 ARRAY_SIZE(apmu_div_clks));
426
427 mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
428 ARRAY_SIZE(apmu_gate_clks));
429
430 if (pxa_unit->model == CLK_MODEL_MMP3) {
431 mmp_register_mux_clks(unit, mmp3_apmu_mux_clks, pxa_unit->apmu_base,
432 ARRAY_SIZE(mmp3_apmu_mux_clks));
433
434 mmp_register_div_clks(unit, mmp3_apmu_div_clks, pxa_unit->apmu_base,
435 ARRAY_SIZE(mmp3_apmu_div_clks));
436
437 mmp_register_gate_clks(unit, mmp3_apmu_gate_clks, pxa_unit->apmu_base,
438 ARRAY_SIZE(mmp3_apmu_gate_clks));
439 } else {
440 clk_register_mux_table(NULL, "gpu_3d_mux", mmp2_gpu_gc_parent_names,
441 ARRAY_SIZE(mmp2_gpu_gc_parent_names),
442 CLK_SET_RATE_PARENT,
443 pxa_unit->apmu_base + APMU_GPU,
444 0, 0x10c0, 0,
445 mmp2_gpu_gc_parent_table, &gpu_lock);
446
447 clk_register_mux_table(NULL, "gpu_bus_mux", mmp2_gpu_bus_parent_names,
448 ARRAY_SIZE(mmp2_gpu_bus_parent_names),
449 CLK_SET_RATE_PARENT,
450 pxa_unit->apmu_base + APMU_GPU,
451 0, 0x4030, 0,
452 mmp2_gpu_bus_parent_table, &gpu_lock);
453
454 mmp_register_gate_clks(unit, mmp2_apmu_gate_clks, pxa_unit->apmu_base,
455 ARRAY_SIZE(mmp2_apmu_gate_clks));
456 }
457 }
458
mmp2_clk_reset_init(struct device_node * np,struct mmp2_clk_unit * pxa_unit)459 static void mmp2_clk_reset_init(struct device_node *np,
460 struct mmp2_clk_unit *pxa_unit)
461 {
462 struct mmp_clk_reset_cell *cells;
463 int i, nr_resets;
464
465 nr_resets = ARRAY_SIZE(apbc_gate_clks);
466 cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL);
467 if (!cells)
468 return;
469
470 for (i = 0; i < nr_resets; i++) {
471 cells[i].clk_id = apbc_gate_clks[i].id;
472 cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset;
473 cells[i].flags = 0;
474 cells[i].lock = apbc_gate_clks[i].lock;
475 cells[i].bits = 0x4;
476 }
477
478 mmp_clk_reset_register(np, cells, nr_resets);
479 }
480
mmp2_pm_domain_init(struct device_node * np,struct mmp2_clk_unit * pxa_unit)481 static void mmp2_pm_domain_init(struct device_node *np,
482 struct mmp2_clk_unit *pxa_unit)
483 {
484 if (pxa_unit->model == CLK_MODEL_MMP3) {
485 pxa_unit->pm_domains[MMP2_POWER_DOMAIN_GPU]
486 = mmp_pm_domain_register("gpu",
487 pxa_unit->apmu_base + APMU_GPU,
488 0x0600, 0x40003, 0x18000c, 0, &gpu_lock);
489 } else {
490 pxa_unit->pm_domains[MMP2_POWER_DOMAIN_GPU]
491 = mmp_pm_domain_register("gpu",
492 pxa_unit->apmu_base + APMU_GPU,
493 0x8600, 0x00003, 0x00000c,
494 MMP_PM_DOMAIN_NO_DISABLE, &gpu_lock);
495 }
496 pxa_unit->pd_data.num_domains++;
497
498 pxa_unit->pm_domains[MMP2_POWER_DOMAIN_AUDIO]
499 = mmp_pm_domain_register("audio",
500 pxa_unit->apmu_base + APMU_AUDIO,
501 0x600, 0x2, 0, 0, &audio_lock);
502 pxa_unit->pd_data.num_domains++;
503
504 if (pxa_unit->model == CLK_MODEL_MMP3) {
505 pxa_unit->pm_domains[MMP3_POWER_DOMAIN_CAMERA]
506 = mmp_pm_domain_register("camera",
507 pxa_unit->apmu_base + APMU_CAMERA,
508 0x600, 0, 0, 0, NULL);
509 pxa_unit->pd_data.num_domains++;
510 }
511
512 pxa_unit->pd_data.domains = pxa_unit->pm_domains;
513 of_genpd_add_provider_onecell(np, &pxa_unit->pd_data);
514 }
515
mmp2_clk_init(struct device_node * np)516 static void __init mmp2_clk_init(struct device_node *np)
517 {
518 struct mmp2_clk_unit *pxa_unit;
519
520 pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
521 if (!pxa_unit)
522 return;
523
524 if (of_device_is_compatible(np, "marvell,mmp3-clock"))
525 pxa_unit->model = CLK_MODEL_MMP3;
526 else
527 pxa_unit->model = CLK_MODEL_MMP2;
528
529 pxa_unit->mpmu_base = of_iomap(np, 0);
530 if (!pxa_unit->mpmu_base) {
531 pr_err("failed to map mpmu registers\n");
532 goto free_memory;
533 }
534
535 pxa_unit->apmu_base = of_iomap(np, 1);
536 if (!pxa_unit->apmu_base) {
537 pr_err("failed to map apmu registers\n");
538 goto unmap_mpmu_region;
539 }
540
541 pxa_unit->apbc_base = of_iomap(np, 2);
542 if (!pxa_unit->apbc_base) {
543 pr_err("failed to map apbc registers\n");
544 goto unmap_apmu_region;
545 }
546
547 mmp2_pm_domain_init(np, pxa_unit);
548
549 mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS);
550
551 mmp2_main_clk_init(pxa_unit);
552
553 mmp2_apb_periph_clk_init(pxa_unit);
554
555 mmp2_axi_periph_clk_init(pxa_unit);
556
557 mmp2_clk_reset_init(np, pxa_unit);
558
559 return;
560
561 unmap_apmu_region:
562 iounmap(pxa_unit->apmu_base);
563 unmap_mpmu_region:
564 iounmap(pxa_unit->mpmu_base);
565 free_memory:
566 kfree(pxa_unit);
567 }
568
569 CLK_OF_DECLARE(mmp2_clk, "marvell,mmp2-clock", mmp2_clk_init);
570 CLK_OF_DECLARE(mmp3_clk, "marvell,mmp3-clock", mmp2_clk_init);
571