1 // SPDX-License-Identifier: GPL-2.0-only
2 /**
3 * Copyright (C) 2020 Microchip
4 *
5 * Author: Kamel Bouhara <kamel.bouhara@bootlin.com>
6 */
7 #include <linux/clk.h>
8 #include <linux/counter.h>
9 #include <linux/mfd/syscon.h>
10 #include <linux/module.h>
11 #include <linux/mutex.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <soc/at91/atmel_tcb.h>
17
18 #define ATMEL_TC_CMR_MASK (ATMEL_TC_LDRA_RISING | ATMEL_TC_LDRB_FALLING | \
19 ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_LDBDIS | \
20 ATMEL_TC_LDBSTOP)
21
22 #define ATMEL_TC_QDEN BIT(8)
23 #define ATMEL_TC_POSEN BIT(9)
24
25 struct mchp_tc_data {
26 const struct atmel_tcb_config *tc_cfg;
27 struct counter_device counter;
28 struct regmap *regmap;
29 int qdec_mode;
30 int num_channels;
31 int channel[2];
32 };
33
34 static const enum counter_function mchp_tc_count_functions[] = {
35 COUNTER_FUNCTION_INCREASE,
36 COUNTER_FUNCTION_QUADRATURE_X4,
37 };
38
39 static const enum counter_synapse_action mchp_tc_synapse_actions[] = {
40 COUNTER_SYNAPSE_ACTION_NONE,
41 COUNTER_SYNAPSE_ACTION_RISING_EDGE,
42 COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
43 COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
44 };
45
46 static struct counter_signal mchp_tc_count_signals[] = {
47 {
48 .id = 0,
49 .name = "Channel A",
50 },
51 {
52 .id = 1,
53 .name = "Channel B",
54 }
55 };
56
57 static struct counter_synapse mchp_tc_count_synapses[] = {
58 {
59 .actions_list = mchp_tc_synapse_actions,
60 .num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
61 .signal = &mchp_tc_count_signals[0]
62 },
63 {
64 .actions_list = mchp_tc_synapse_actions,
65 .num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
66 .signal = &mchp_tc_count_signals[1]
67 }
68 };
69
mchp_tc_count_function_read(struct counter_device * counter,struct counter_count * count,enum counter_function * function)70 static int mchp_tc_count_function_read(struct counter_device *counter,
71 struct counter_count *count,
72 enum counter_function *function)
73 {
74 struct mchp_tc_data *const priv = counter->priv;
75
76 if (priv->qdec_mode)
77 *function = COUNTER_FUNCTION_QUADRATURE_X4;
78 else
79 *function = COUNTER_FUNCTION_INCREASE;
80
81 return 0;
82 }
83
mchp_tc_count_function_write(struct counter_device * counter,struct counter_count * count,enum counter_function function)84 static int mchp_tc_count_function_write(struct counter_device *counter,
85 struct counter_count *count,
86 enum counter_function function)
87 {
88 struct mchp_tc_data *const priv = counter->priv;
89 u32 bmr, cmr;
90
91 regmap_read(priv->regmap, ATMEL_TC_BMR, &bmr);
92 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
93
94 /* Set capture mode */
95 cmr &= ~ATMEL_TC_WAVE;
96
97 switch (function) {
98 case COUNTER_FUNCTION_INCREASE:
99 priv->qdec_mode = 0;
100 /* Set highest rate based on whether soc has gclk or not */
101 bmr &= ~(ATMEL_TC_QDEN | ATMEL_TC_POSEN);
102 if (!priv->tc_cfg->has_gclk)
103 cmr |= ATMEL_TC_TIMER_CLOCK2;
104 else
105 cmr |= ATMEL_TC_TIMER_CLOCK1;
106 /* Setup the period capture mode */
107 cmr |= ATMEL_TC_CMR_MASK;
108 cmr &= ~(ATMEL_TC_ABETRG | ATMEL_TC_XC0);
109 break;
110 case COUNTER_FUNCTION_QUADRATURE_X4:
111 if (!priv->tc_cfg->has_qdec)
112 return -EINVAL;
113 /* In QDEC mode settings both channels 0 and 1 are required */
114 if (priv->num_channels < 2 || priv->channel[0] != 0 ||
115 priv->channel[1] != 1) {
116 pr_err("Invalid channels number or id for quadrature mode\n");
117 return -EINVAL;
118 }
119 priv->qdec_mode = 1;
120 bmr |= ATMEL_TC_QDEN | ATMEL_TC_POSEN;
121 cmr |= ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_ABETRG | ATMEL_TC_XC0;
122 break;
123 default:
124 /* should never reach this path */
125 return -EINVAL;
126 }
127
128 regmap_write(priv->regmap, ATMEL_TC_BMR, bmr);
129 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), cmr);
130
131 /* Enable clock and trigger counter */
132 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR),
133 ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
134
135 if (priv->qdec_mode) {
136 regmap_write(priv->regmap,
137 ATMEL_TC_REG(priv->channel[1], CMR), cmr);
138 regmap_write(priv->regmap,
139 ATMEL_TC_REG(priv->channel[1], CCR),
140 ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
141 }
142
143 return 0;
144 }
145
mchp_tc_count_signal_read(struct counter_device * counter,struct counter_signal * signal,enum counter_signal_level * lvl)146 static int mchp_tc_count_signal_read(struct counter_device *counter,
147 struct counter_signal *signal,
148 enum counter_signal_level *lvl)
149 {
150 struct mchp_tc_data *const priv = counter->priv;
151 bool sigstatus;
152 u32 sr;
153
154 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], SR), &sr);
155
156 if (signal->id == 1)
157 sigstatus = (sr & ATMEL_TC_MTIOB);
158 else
159 sigstatus = (sr & ATMEL_TC_MTIOA);
160
161 *lvl = sigstatus ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW;
162
163 return 0;
164 }
165
mchp_tc_count_action_read(struct counter_device * counter,struct counter_count * count,struct counter_synapse * synapse,enum counter_synapse_action * action)166 static int mchp_tc_count_action_read(struct counter_device *counter,
167 struct counter_count *count,
168 struct counter_synapse *synapse,
169 enum counter_synapse_action *action)
170 {
171 struct mchp_tc_data *const priv = counter->priv;
172 u32 cmr;
173
174 if (priv->qdec_mode) {
175 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
176 return 0;
177 }
178
179 /* Only TIOA signal is evaluated in non-QDEC mode */
180 if (synapse->signal->id != 0) {
181 *action = COUNTER_SYNAPSE_ACTION_NONE;
182 return 0;
183 }
184
185 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
186
187 switch (cmr & ATMEL_TC_ETRGEDG) {
188 default:
189 *action = COUNTER_SYNAPSE_ACTION_NONE;
190 break;
191 case ATMEL_TC_ETRGEDG_RISING:
192 *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE;
193 break;
194 case ATMEL_TC_ETRGEDG_FALLING:
195 *action = COUNTER_SYNAPSE_ACTION_FALLING_EDGE;
196 break;
197 case ATMEL_TC_ETRGEDG_BOTH:
198 *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
199 break;
200 }
201
202 return 0;
203 }
204
mchp_tc_count_action_write(struct counter_device * counter,struct counter_count * count,struct counter_synapse * synapse,enum counter_synapse_action action)205 static int mchp_tc_count_action_write(struct counter_device *counter,
206 struct counter_count *count,
207 struct counter_synapse *synapse,
208 enum counter_synapse_action action)
209 {
210 struct mchp_tc_data *const priv = counter->priv;
211 u32 edge = ATMEL_TC_ETRGEDG_NONE;
212
213 /* QDEC mode is rising edge only; only TIOA handled in non-QDEC mode */
214 if (priv->qdec_mode || synapse->signal->id != 0)
215 return -EINVAL;
216
217 switch (action) {
218 case COUNTER_SYNAPSE_ACTION_NONE:
219 edge = ATMEL_TC_ETRGEDG_NONE;
220 break;
221 case COUNTER_SYNAPSE_ACTION_RISING_EDGE:
222 edge = ATMEL_TC_ETRGEDG_RISING;
223 break;
224 case COUNTER_SYNAPSE_ACTION_FALLING_EDGE:
225 edge = ATMEL_TC_ETRGEDG_FALLING;
226 break;
227 case COUNTER_SYNAPSE_ACTION_BOTH_EDGES:
228 edge = ATMEL_TC_ETRGEDG_BOTH;
229 break;
230 default:
231 /* should never reach this path */
232 return -EINVAL;
233 }
234
235 return regmap_write_bits(priv->regmap,
236 ATMEL_TC_REG(priv->channel[0], CMR),
237 ATMEL_TC_ETRGEDG, edge);
238 }
239
mchp_tc_count_read(struct counter_device * counter,struct counter_count * count,u64 * val)240 static int mchp_tc_count_read(struct counter_device *counter,
241 struct counter_count *count, u64 *val)
242 {
243 struct mchp_tc_data *const priv = counter->priv;
244 u32 cnt;
245
246 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CV), &cnt);
247 *val = cnt;
248
249 return 0;
250 }
251
252 static struct counter_count mchp_tc_counts[] = {
253 {
254 .id = 0,
255 .name = "Timer Counter",
256 .functions_list = mchp_tc_count_functions,
257 .num_functions = ARRAY_SIZE(mchp_tc_count_functions),
258 .synapses = mchp_tc_count_synapses,
259 .num_synapses = ARRAY_SIZE(mchp_tc_count_synapses),
260 },
261 };
262
263 static const struct counter_ops mchp_tc_ops = {
264 .signal_read = mchp_tc_count_signal_read,
265 .count_read = mchp_tc_count_read,
266 .function_read = mchp_tc_count_function_read,
267 .function_write = mchp_tc_count_function_write,
268 .action_read = mchp_tc_count_action_read,
269 .action_write = mchp_tc_count_action_write
270 };
271
272 static const struct atmel_tcb_config tcb_rm9200_config = {
273 .counter_width = 16,
274 };
275
276 static const struct atmel_tcb_config tcb_sam9x5_config = {
277 .counter_width = 32,
278 };
279
280 static const struct atmel_tcb_config tcb_sama5d2_config = {
281 .counter_width = 32,
282 .has_gclk = true,
283 .has_qdec = true,
284 };
285
286 static const struct atmel_tcb_config tcb_sama5d3_config = {
287 .counter_width = 32,
288 .has_qdec = true,
289 };
290
291 static const struct of_device_id atmel_tc_of_match[] = {
292 { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
293 { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
294 { .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
295 { .compatible = "atmel,sama5d3-tcb", .data = &tcb_sama5d3_config, },
296 { /* sentinel */ }
297 };
298
mchp_tc_clk_remove(void * ptr)299 static void mchp_tc_clk_remove(void *ptr)
300 {
301 clk_disable_unprepare((struct clk *)ptr);
302 }
303
mchp_tc_probe(struct platform_device * pdev)304 static int mchp_tc_probe(struct platform_device *pdev)
305 {
306 struct device_node *np = pdev->dev.of_node;
307 const struct atmel_tcb_config *tcb_config;
308 const struct of_device_id *match;
309 struct mchp_tc_data *priv;
310 char clk_name[7];
311 struct regmap *regmap;
312 struct clk *clk[3];
313 int channel;
314 int ret, i;
315
316 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
317 if (!priv)
318 return -ENOMEM;
319
320 platform_set_drvdata(pdev, priv);
321
322 match = of_match_node(atmel_tc_of_match, np->parent);
323 tcb_config = match->data;
324 if (!tcb_config) {
325 dev_err(&pdev->dev, "No matching parent node found\n");
326 return -ENODEV;
327 }
328
329 regmap = syscon_node_to_regmap(np->parent);
330 if (IS_ERR(regmap))
331 return PTR_ERR(regmap);
332
333 /* max. channels number is 2 when in QDEC mode */
334 priv->num_channels = of_property_count_u32_elems(np, "reg");
335 if (priv->num_channels < 0) {
336 dev_err(&pdev->dev, "Invalid or missing channel\n");
337 return -EINVAL;
338 }
339
340 /* Register channels and initialize clocks */
341 for (i = 0; i < priv->num_channels; i++) {
342 ret = of_property_read_u32_index(np, "reg", i, &channel);
343 if (ret < 0 || channel > 2)
344 return -ENODEV;
345
346 priv->channel[i] = channel;
347
348 snprintf(clk_name, sizeof(clk_name), "t%d_clk", channel);
349
350 clk[i] = of_clk_get_by_name(np->parent, clk_name);
351 if (IS_ERR(clk[i])) {
352 /* Fallback to t0_clk */
353 clk[i] = of_clk_get_by_name(np->parent, "t0_clk");
354 if (IS_ERR(clk[i]))
355 return PTR_ERR(clk[i]);
356 }
357
358 ret = clk_prepare_enable(clk[i]);
359 if (ret)
360 return ret;
361
362 ret = devm_add_action_or_reset(&pdev->dev,
363 mchp_tc_clk_remove,
364 clk[i]);
365 if (ret)
366 return ret;
367
368 dev_dbg(&pdev->dev,
369 "Initialized capture mode on channel %d\n",
370 channel);
371 }
372
373 priv->tc_cfg = tcb_config;
374 priv->regmap = regmap;
375 priv->counter.name = dev_name(&pdev->dev);
376 priv->counter.parent = &pdev->dev;
377 priv->counter.ops = &mchp_tc_ops;
378 priv->counter.num_counts = ARRAY_SIZE(mchp_tc_counts);
379 priv->counter.counts = mchp_tc_counts;
380 priv->counter.num_signals = ARRAY_SIZE(mchp_tc_count_signals);
381 priv->counter.signals = mchp_tc_count_signals;
382 priv->counter.priv = priv;
383
384 return devm_counter_register(&pdev->dev, &priv->counter);
385 }
386
387 static const struct of_device_id mchp_tc_dt_ids[] = {
388 { .compatible = "microchip,tcb-capture", },
389 { /* sentinel */ },
390 };
391 MODULE_DEVICE_TABLE(of, mchp_tc_dt_ids);
392
393 static struct platform_driver mchp_tc_driver = {
394 .probe = mchp_tc_probe,
395 .driver = {
396 .name = "microchip-tcb-capture",
397 .of_match_table = mchp_tc_dt_ids,
398 },
399 };
400 module_platform_driver(mchp_tc_driver);
401
402 MODULE_AUTHOR("Kamel Bouhara <kamel.bouhara@bootlin.com>");
403 MODULE_DESCRIPTION("Microchip TCB Capture driver");
404 MODULE_LICENSE("GPL v2");
405