1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2020 Intel Corporation */
3 #include <linux/iopoll.h>
4 #include <adf_accel_devices.h>
5 #include <adf_common_drv.h>
6 #include <adf_pf2vf_msg.h>
7 #include <adf_gen4_hw_data.h>
8 #include "adf_4xxx_hw_data.h"
9 #include "icp_qat_hw.h"
10
11 struct adf_fw_config {
12 u32 ae_mask;
13 char *obj_name;
14 };
15
16 static struct adf_fw_config adf_4xxx_fw_config[] = {
17 {0xF0, ADF_4XXX_SYM_OBJ},
18 {0xF, ADF_4XXX_ASYM_OBJ},
19 {0x100, ADF_4XXX_ADMIN_OBJ},
20 };
21
22 /* Worker thread to service arbiter mappings */
23 static const u32 thrd_to_arb_map[ADF_4XXX_MAX_ACCELENGINES] = {
24 0x5555555, 0x5555555, 0x5555555, 0x5555555,
25 0xAAAAAAA, 0xAAAAAAA, 0xAAAAAAA, 0xAAAAAAA,
26 0x0
27 };
28
29 static struct adf_hw_device_class adf_4xxx_class = {
30 .name = ADF_4XXX_DEVICE_NAME,
31 .type = DEV_4XXX,
32 .instances = 0,
33 };
34
get_accel_mask(struct adf_hw_device_data * self)35 static u32 get_accel_mask(struct adf_hw_device_data *self)
36 {
37 return ADF_4XXX_ACCELERATORS_MASK;
38 }
39
get_ae_mask(struct adf_hw_device_data * self)40 static u32 get_ae_mask(struct adf_hw_device_data *self)
41 {
42 u32 me_disable = self->fuses;
43
44 return ~me_disable & ADF_4XXX_ACCELENGINES_MASK;
45 }
46
get_num_accels(struct adf_hw_device_data * self)47 static u32 get_num_accels(struct adf_hw_device_data *self)
48 {
49 return ADF_4XXX_MAX_ACCELERATORS;
50 }
51
get_num_aes(struct adf_hw_device_data * self)52 static u32 get_num_aes(struct adf_hw_device_data *self)
53 {
54 if (!self || !self->ae_mask)
55 return 0;
56
57 return hweight32(self->ae_mask);
58 }
59
get_misc_bar_id(struct adf_hw_device_data * self)60 static u32 get_misc_bar_id(struct adf_hw_device_data *self)
61 {
62 return ADF_4XXX_PMISC_BAR;
63 }
64
get_etr_bar_id(struct adf_hw_device_data * self)65 static u32 get_etr_bar_id(struct adf_hw_device_data *self)
66 {
67 return ADF_4XXX_ETR_BAR;
68 }
69
get_sram_bar_id(struct adf_hw_device_data * self)70 static u32 get_sram_bar_id(struct adf_hw_device_data *self)
71 {
72 return ADF_4XXX_SRAM_BAR;
73 }
74
75 /*
76 * The vector routing table is used to select the MSI-X entry to use for each
77 * interrupt source.
78 * The first ADF_4XXX_ETR_MAX_BANKS entries correspond to ring interrupts.
79 * The final entry corresponds to VF2PF or error interrupts.
80 * This vector table could be used to configure one MSI-X entry to be shared
81 * between multiple interrupt sources.
82 *
83 * The default routing is set to have a one to one correspondence between the
84 * interrupt source and the MSI-X entry used.
85 */
set_msix_default_rttable(struct adf_accel_dev * accel_dev)86 static void set_msix_default_rttable(struct adf_accel_dev *accel_dev)
87 {
88 void __iomem *csr;
89 int i;
90
91 csr = (&GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR])->virt_addr;
92 for (i = 0; i <= ADF_4XXX_ETR_MAX_BANKS; i++)
93 ADF_CSR_WR(csr, ADF_4XXX_MSIX_RTTABLE_OFFSET(i), i);
94 }
95
get_accel_cap(struct adf_accel_dev * accel_dev)96 static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
97 {
98 struct pci_dev *pdev = accel_dev->accel_pci_dev.pci_dev;
99 u32 fusectl1;
100 u32 capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
101 ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
102 ICP_ACCEL_CAPABILITIES_AUTHENTICATION |
103 ICP_ACCEL_CAPABILITIES_AES_V2;
104
105 /* Read accelerator capabilities mask */
106 pci_read_config_dword(pdev, ADF_4XXX_FUSECTL1_OFFSET, &fusectl1);
107
108 if (fusectl1 & ICP_ACCEL_4XXX_MASK_CIPHER_SLICE)
109 capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
110 if (fusectl1 & ICP_ACCEL_4XXX_MASK_AUTH_SLICE)
111 capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
112 if (fusectl1 & ICP_ACCEL_4XXX_MASK_PKE_SLICE)
113 capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
114
115 return capabilities;
116 }
117
get_sku(struct adf_hw_device_data * self)118 static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
119 {
120 return DEV_SKU_1;
121 }
122
adf_get_arbiter_mapping(void)123 static const u32 *adf_get_arbiter_mapping(void)
124 {
125 return thrd_to_arb_map;
126 }
127
get_arb_info(struct arb_info * arb_info)128 static void get_arb_info(struct arb_info *arb_info)
129 {
130 arb_info->arb_cfg = ADF_4XXX_ARB_CONFIG;
131 arb_info->arb_offset = ADF_4XXX_ARB_OFFSET;
132 arb_info->wt2sam_offset = ADF_4XXX_ARB_WRK_2_SER_MAP_OFFSET;
133 }
134
get_admin_info(struct admin_info * admin_csrs_info)135 static void get_admin_info(struct admin_info *admin_csrs_info)
136 {
137 admin_csrs_info->mailbox_offset = ADF_4XXX_MAILBOX_BASE_OFFSET;
138 admin_csrs_info->admin_msg_ur = ADF_4XXX_ADMINMSGUR_OFFSET;
139 admin_csrs_info->admin_msg_lr = ADF_4XXX_ADMINMSGLR_OFFSET;
140 }
141
adf_enable_error_correction(struct adf_accel_dev * accel_dev)142 static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
143 {
144 struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR];
145 void __iomem *csr = misc_bar->virt_addr;
146
147 /* Enable all in errsou3 except VFLR notification on host */
148 ADF_CSR_WR(csr, ADF_4XXX_ERRMSK3, ADF_4XXX_VFLNOTIFY);
149 }
150
adf_enable_ints(struct adf_accel_dev * accel_dev)151 static void adf_enable_ints(struct adf_accel_dev *accel_dev)
152 {
153 void __iomem *addr;
154
155 addr = (&GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR])->virt_addr;
156
157 /* Enable bundle interrupts */
158 ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_RP_X0_MASK_OFFSET, 0);
159 ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_RP_X1_MASK_OFFSET, 0);
160
161 /* Enable misc interrupts */
162 ADF_CSR_WR(addr, ADF_4XXX_SMIAPF_MASK_OFFSET, 0);
163 }
164
adf_init_device(struct adf_accel_dev * accel_dev)165 static int adf_init_device(struct adf_accel_dev *accel_dev)
166 {
167 void __iomem *addr;
168 u32 status;
169 u32 csr;
170 int ret;
171
172 addr = (&GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR])->virt_addr;
173
174 /* Temporarily mask PM interrupt */
175 csr = ADF_CSR_RD(addr, ADF_4XXX_ERRMSK2);
176 csr |= ADF_4XXX_PM_SOU;
177 ADF_CSR_WR(addr, ADF_4XXX_ERRMSK2, csr);
178
179 /* Set DRV_ACTIVE bit to power up the device */
180 ADF_CSR_WR(addr, ADF_4XXX_PM_INTERRUPT, ADF_4XXX_PM_DRV_ACTIVE);
181
182 /* Poll status register to make sure the device is powered up */
183 ret = read_poll_timeout(ADF_CSR_RD, status,
184 status & ADF_4XXX_PM_INIT_STATE,
185 ADF_4XXX_PM_POLL_DELAY_US,
186 ADF_4XXX_PM_POLL_TIMEOUT_US, true, addr,
187 ADF_4XXX_PM_STATUS);
188 if (ret)
189 dev_err(&GET_DEV(accel_dev), "Failed to power up the device\n");
190
191 return ret;
192 }
193
adf_enable_pf2vf_comms(struct adf_accel_dev * accel_dev)194 static int adf_enable_pf2vf_comms(struct adf_accel_dev *accel_dev)
195 {
196 return 0;
197 }
198
uof_get_num_objs(void)199 static u32 uof_get_num_objs(void)
200 {
201 return ARRAY_SIZE(adf_4xxx_fw_config);
202 }
203
uof_get_name(u32 obj_num)204 static char *uof_get_name(u32 obj_num)
205 {
206 return adf_4xxx_fw_config[obj_num].obj_name;
207 }
208
uof_get_ae_mask(u32 obj_num)209 static u32 uof_get_ae_mask(u32 obj_num)
210 {
211 return adf_4xxx_fw_config[obj_num].ae_mask;
212 }
213
adf_init_hw_data_4xxx(struct adf_hw_device_data * hw_data)214 void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data)
215 {
216 hw_data->dev_class = &adf_4xxx_class;
217 hw_data->instance_id = adf_4xxx_class.instances++;
218 hw_data->num_banks = ADF_4XXX_ETR_MAX_BANKS;
219 hw_data->num_rings_per_bank = ADF_4XXX_NUM_RINGS_PER_BANK;
220 hw_data->num_accel = ADF_4XXX_MAX_ACCELERATORS;
221 hw_data->num_engines = ADF_4XXX_MAX_ACCELENGINES;
222 hw_data->num_logical_accel = 1;
223 hw_data->tx_rx_gap = ADF_4XXX_RX_RINGS_OFFSET;
224 hw_data->tx_rings_mask = ADF_4XXX_TX_RINGS_MASK;
225 hw_data->alloc_irq = adf_isr_resource_alloc;
226 hw_data->free_irq = adf_isr_resource_free;
227 hw_data->enable_error_correction = adf_enable_error_correction;
228 hw_data->get_accel_mask = get_accel_mask;
229 hw_data->get_ae_mask = get_ae_mask;
230 hw_data->get_num_accels = get_num_accels;
231 hw_data->get_num_aes = get_num_aes;
232 hw_data->get_sram_bar_id = get_sram_bar_id;
233 hw_data->get_etr_bar_id = get_etr_bar_id;
234 hw_data->get_misc_bar_id = get_misc_bar_id;
235 hw_data->get_arb_info = get_arb_info;
236 hw_data->get_admin_info = get_admin_info;
237 hw_data->get_accel_cap = get_accel_cap;
238 hw_data->get_sku = get_sku;
239 hw_data->fw_name = ADF_4XXX_FW;
240 hw_data->fw_mmp_name = ADF_4XXX_MMP;
241 hw_data->init_admin_comms = adf_init_admin_comms;
242 hw_data->exit_admin_comms = adf_exit_admin_comms;
243 hw_data->send_admin_init = adf_send_admin_init;
244 hw_data->init_arb = adf_init_arb;
245 hw_data->exit_arb = adf_exit_arb;
246 hw_data->get_arb_mapping = adf_get_arbiter_mapping;
247 hw_data->enable_ints = adf_enable_ints;
248 hw_data->init_device = adf_init_device;
249 hw_data->reset_device = adf_reset_flr;
250 hw_data->admin_ae_mask = ADF_4XXX_ADMIN_AE_MASK;
251 hw_data->uof_get_num_objs = uof_get_num_objs;
252 hw_data->uof_get_name = uof_get_name;
253 hw_data->uof_get_ae_mask = uof_get_ae_mask;
254 hw_data->set_msix_rttable = set_msix_default_rttable;
255 hw_data->set_ssm_wdtimer = adf_gen4_set_ssm_wdtimer;
256 hw_data->enable_pfvf_comms = adf_enable_pf2vf_comms;
257 hw_data->disable_iov = adf_disable_sriov;
258 hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION;
259
260 adf_gen4_init_hw_csr_ops(&hw_data->csr_ops);
261 }
262
adf_clean_hw_data_4xxx(struct adf_hw_device_data * hw_data)263 void adf_clean_hw_data_4xxx(struct adf_hw_device_data *hw_data)
264 {
265 hw_data->dev_class->instances--;
266 }
267