1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
5 *
6 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
7 */
8
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/gpio/driver.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_address.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24 #include <linux/regmap.h>
25
26 #include "../pinctrl/core.h"
27 #include "../pinctrl/pinctrl-rockchip.h"
28
29 #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
30 #define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
31
32 static const struct rockchip_gpio_regs gpio_regs_v1 = {
33 .port_dr = 0x00,
34 .port_ddr = 0x04,
35 .int_en = 0x30,
36 .int_mask = 0x34,
37 .int_type = 0x38,
38 .int_polarity = 0x3c,
39 .int_status = 0x40,
40 .int_rawstatus = 0x44,
41 .debounce = 0x48,
42 .port_eoi = 0x4c,
43 .ext_port = 0x50,
44 };
45
46 static const struct rockchip_gpio_regs gpio_regs_v2 = {
47 .port_dr = 0x00,
48 .port_ddr = 0x08,
49 .int_en = 0x10,
50 .int_mask = 0x18,
51 .int_type = 0x20,
52 .int_polarity = 0x28,
53 .int_bothedge = 0x30,
54 .int_status = 0x50,
55 .int_rawstatus = 0x58,
56 .debounce = 0x38,
57 .dbclk_div_en = 0x40,
58 .dbclk_div_con = 0x48,
59 .port_eoi = 0x60,
60 .ext_port = 0x70,
61 .version_id = 0x78,
62 };
63
gpio_writel_v2(u32 val,void __iomem * reg)64 static inline void gpio_writel_v2(u32 val, void __iomem *reg)
65 {
66 writel((val & 0xffff) | 0xffff0000, reg);
67 writel((val >> 16) | 0xffff0000, reg + 0x4);
68 }
69
gpio_readl_v2(void __iomem * reg)70 static inline u32 gpio_readl_v2(void __iomem *reg)
71 {
72 return readl(reg + 0x4) << 16 | readl(reg);
73 }
74
rockchip_gpio_writel(struct rockchip_pin_bank * bank,u32 value,unsigned int offset)75 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
76 u32 value, unsigned int offset)
77 {
78 void __iomem *reg = bank->reg_base + offset;
79
80 if (bank->gpio_type == GPIO_TYPE_V2)
81 gpio_writel_v2(value, reg);
82 else
83 writel(value, reg);
84 }
85
rockchip_gpio_readl(struct rockchip_pin_bank * bank,unsigned int offset)86 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
87 unsigned int offset)
88 {
89 void __iomem *reg = bank->reg_base + offset;
90 u32 value;
91
92 if (bank->gpio_type == GPIO_TYPE_V2)
93 value = gpio_readl_v2(reg);
94 else
95 value = readl(reg);
96
97 return value;
98 }
99
rockchip_gpio_writel_bit(struct rockchip_pin_bank * bank,u32 bit,u32 value,unsigned int offset)100 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
101 u32 bit, u32 value,
102 unsigned int offset)
103 {
104 void __iomem *reg = bank->reg_base + offset;
105 u32 data;
106
107 if (bank->gpio_type == GPIO_TYPE_V2) {
108 if (value)
109 data = BIT(bit % 16) | BIT(bit % 16 + 16);
110 else
111 data = BIT(bit % 16 + 16);
112 writel(data, bit >= 16 ? reg + 0x4 : reg);
113 } else {
114 data = readl(reg);
115 data &= ~BIT(bit);
116 if (value)
117 data |= BIT(bit);
118 writel(data, reg);
119 }
120 }
121
rockchip_gpio_readl_bit(struct rockchip_pin_bank * bank,u32 bit,unsigned int offset)122 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
123 u32 bit, unsigned int offset)
124 {
125 void __iomem *reg = bank->reg_base + offset;
126 u32 data;
127
128 if (bank->gpio_type == GPIO_TYPE_V2) {
129 data = readl(bit >= 16 ? reg + 0x4 : reg);
130 data >>= bit % 16;
131 } else {
132 data = readl(reg);
133 data >>= bit;
134 }
135
136 return data & (0x1);
137 }
138
rockchip_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)139 static int rockchip_gpio_get_direction(struct gpio_chip *chip,
140 unsigned int offset)
141 {
142 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
143 u32 data;
144
145 data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
146 if (data)
147 return GPIO_LINE_DIRECTION_OUT;
148
149 return GPIO_LINE_DIRECTION_IN;
150 }
151
rockchip_gpio_set_direction(struct gpio_chip * chip,unsigned int offset,bool input)152 static int rockchip_gpio_set_direction(struct gpio_chip *chip,
153 unsigned int offset, bool input)
154 {
155 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
156 unsigned long flags;
157 u32 data = input ? 0 : 1;
158
159
160 if (input)
161 pinctrl_gpio_direction_input(bank->pin_base + offset);
162 else
163 pinctrl_gpio_direction_output(bank->pin_base + offset);
164
165 raw_spin_lock_irqsave(&bank->slock, flags);
166 rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
167 raw_spin_unlock_irqrestore(&bank->slock, flags);
168
169 return 0;
170 }
171
rockchip_gpio_set(struct gpio_chip * gc,unsigned int offset,int value)172 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
173 int value)
174 {
175 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
176 unsigned long flags;
177
178 raw_spin_lock_irqsave(&bank->slock, flags);
179 rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
180 raw_spin_unlock_irqrestore(&bank->slock, flags);
181 }
182
rockchip_gpio_get(struct gpio_chip * gc,unsigned int offset)183 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
184 {
185 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
186 u32 data;
187
188 data = readl(bank->reg_base + bank->gpio_regs->ext_port);
189 data >>= offset;
190 data &= 1;
191
192 return data;
193 }
194
rockchip_gpio_set_debounce(struct gpio_chip * gc,unsigned int offset,unsigned int debounce)195 static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
196 unsigned int offset,
197 unsigned int debounce)
198 {
199 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
200 const struct rockchip_gpio_regs *reg = bank->gpio_regs;
201 unsigned long flags, div_reg, freq, max_debounce;
202 bool div_debounce_support;
203 unsigned int cur_div_reg;
204 u64 div;
205
206 if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {
207 div_debounce_support = true;
208 freq = clk_get_rate(bank->db_clk);
209 max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;
210 if (debounce > max_debounce)
211 return -EINVAL;
212
213 div = debounce * freq;
214 div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1;
215 } else {
216 div_debounce_support = false;
217 }
218
219 raw_spin_lock_irqsave(&bank->slock, flags);
220
221 /* Only the v1 needs to configure div_en and div_con for dbclk */
222 if (debounce) {
223 if (div_debounce_support) {
224 /* Configure the max debounce from consumers */
225 cur_div_reg = readl(bank->reg_base +
226 reg->dbclk_div_con);
227 if (cur_div_reg < div_reg)
228 writel(div_reg, bank->reg_base +
229 reg->dbclk_div_con);
230 rockchip_gpio_writel_bit(bank, offset, 1,
231 reg->dbclk_div_en);
232 }
233
234 rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce);
235 } else {
236 if (div_debounce_support)
237 rockchip_gpio_writel_bit(bank, offset, 0,
238 reg->dbclk_div_en);
239
240 rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce);
241 }
242
243 raw_spin_unlock_irqrestore(&bank->slock, flags);
244
245 /* Enable or disable dbclk at last */
246 if (div_debounce_support) {
247 if (debounce)
248 clk_prepare_enable(bank->db_clk);
249 else
250 clk_disable_unprepare(bank->db_clk);
251 }
252
253 return 0;
254 }
255
rockchip_gpio_direction_input(struct gpio_chip * gc,unsigned int offset)256 static int rockchip_gpio_direction_input(struct gpio_chip *gc,
257 unsigned int offset)
258 {
259 return rockchip_gpio_set_direction(gc, offset, true);
260 }
261
rockchip_gpio_direction_output(struct gpio_chip * gc,unsigned int offset,int value)262 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
263 unsigned int offset, int value)
264 {
265 rockchip_gpio_set(gc, offset, value);
266
267 return rockchip_gpio_set_direction(gc, offset, false);
268 }
269
270 /*
271 * gpiolib set_config callback function. The setting of the pin
272 * mux function as 'gpio output' will be handled by the pinctrl subsystem
273 * interface.
274 */
rockchip_gpio_set_config(struct gpio_chip * gc,unsigned int offset,unsigned long config)275 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
276 unsigned long config)
277 {
278 enum pin_config_param param = pinconf_to_config_param(config);
279
280 switch (param) {
281 case PIN_CONFIG_INPUT_DEBOUNCE:
282 rockchip_gpio_set_debounce(gc, offset, true);
283 /*
284 * Rockchip's gpio could only support up to one period
285 * of the debounce clock(pclk), which is far away from
286 * satisftying the requirement, as pclk is usually near
287 * 100MHz shared by all peripherals. So the fact is it
288 * has crippled debounce capability could only be useful
289 * to prevent any spurious glitches from waking up the system
290 * if the gpio is conguired as wakeup interrupt source. Let's
291 * still return -ENOTSUPP as before, to make sure the caller
292 * of gpiod_set_debounce won't change its behaviour.
293 */
294 return -ENOTSUPP;
295 default:
296 return -ENOTSUPP;
297 }
298 }
299
300 /*
301 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
302 * and a virtual IRQ, if not already present.
303 */
rockchip_gpio_to_irq(struct gpio_chip * gc,unsigned int offset)304 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
305 {
306 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
307 unsigned int virq;
308
309 if (!bank->domain)
310 return -ENXIO;
311
312 virq = irq_create_mapping(bank->domain, offset);
313
314 return (virq) ? : -ENXIO;
315 }
316
317 static const struct gpio_chip rockchip_gpiolib_chip = {
318 .request = gpiochip_generic_request,
319 .free = gpiochip_generic_free,
320 .set = rockchip_gpio_set,
321 .get = rockchip_gpio_get,
322 .get_direction = rockchip_gpio_get_direction,
323 .direction_input = rockchip_gpio_direction_input,
324 .direction_output = rockchip_gpio_direction_output,
325 .set_config = rockchip_gpio_set_config,
326 .to_irq = rockchip_gpio_to_irq,
327 .owner = THIS_MODULE,
328 };
329
rockchip_irq_demux(struct irq_desc * desc)330 static void rockchip_irq_demux(struct irq_desc *desc)
331 {
332 struct irq_chip *chip = irq_desc_get_chip(desc);
333 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
334 u32 pend;
335
336 dev_dbg(bank->dev, "got irq for bank %s\n", bank->name);
337
338 chained_irq_enter(chip, desc);
339
340 pend = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);
341
342 while (pend) {
343 unsigned int irq, virq;
344
345 irq = __ffs(pend);
346 pend &= ~BIT(irq);
347 virq = irq_find_mapping(bank->domain, irq);
348
349 if (!virq) {
350 dev_err(bank->dev, "unmapped irq %d\n", irq);
351 continue;
352 }
353
354 dev_dbg(bank->dev, "handling irq %d\n", irq);
355
356 /*
357 * Triggering IRQ on both rising and falling edge
358 * needs manual intervention.
359 */
360 if (bank->toggle_edge_mode & BIT(irq)) {
361 u32 data, data_old, polarity;
362 unsigned long flags;
363
364 data = readl_relaxed(bank->reg_base +
365 bank->gpio_regs->ext_port);
366 do {
367 raw_spin_lock_irqsave(&bank->slock, flags);
368
369 polarity = readl_relaxed(bank->reg_base +
370 bank->gpio_regs->int_polarity);
371 if (data & BIT(irq))
372 polarity &= ~BIT(irq);
373 else
374 polarity |= BIT(irq);
375 writel(polarity,
376 bank->reg_base +
377 bank->gpio_regs->int_polarity);
378
379 raw_spin_unlock_irqrestore(&bank->slock, flags);
380
381 data_old = data;
382 data = readl_relaxed(bank->reg_base +
383 bank->gpio_regs->ext_port);
384 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
385 }
386
387 generic_handle_irq(virq);
388 }
389
390 chained_irq_exit(chip, desc);
391 }
392
rockchip_irq_set_type(struct irq_data * d,unsigned int type)393 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
394 {
395 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
396 struct rockchip_pin_bank *bank = gc->private;
397 u32 mask = BIT(d->hwirq);
398 u32 polarity;
399 u32 level;
400 u32 data;
401 unsigned long flags;
402 int ret = 0;
403
404 raw_spin_lock_irqsave(&bank->slock, flags);
405
406 rockchip_gpio_writel_bit(bank, d->hwirq, 0,
407 bank->gpio_regs->port_ddr);
408
409 raw_spin_unlock_irqrestore(&bank->slock, flags);
410
411 if (type & IRQ_TYPE_EDGE_BOTH)
412 irq_set_handler_locked(d, handle_edge_irq);
413 else
414 irq_set_handler_locked(d, handle_level_irq);
415
416 raw_spin_lock_irqsave(&bank->slock, flags);
417
418 level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
419 polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
420
421 if (type == IRQ_TYPE_EDGE_BOTH) {
422 if (bank->gpio_type == GPIO_TYPE_V2) {
423 rockchip_gpio_writel_bit(bank, d->hwirq, 1,
424 bank->gpio_regs->int_bothedge);
425 goto out;
426 } else {
427 bank->toggle_edge_mode |= mask;
428 level &= ~mask;
429
430 /*
431 * Determine gpio state. If 1 next interrupt should be
432 * low otherwise high.
433 */
434 data = readl(bank->reg_base + bank->gpio_regs->ext_port);
435 if (data & mask)
436 polarity &= ~mask;
437 else
438 polarity |= mask;
439 }
440 } else {
441 if (bank->gpio_type == GPIO_TYPE_V2) {
442 rockchip_gpio_writel_bit(bank, d->hwirq, 0,
443 bank->gpio_regs->int_bothedge);
444 } else {
445 bank->toggle_edge_mode &= ~mask;
446 }
447 switch (type) {
448 case IRQ_TYPE_EDGE_RISING:
449 level |= mask;
450 polarity |= mask;
451 break;
452 case IRQ_TYPE_EDGE_FALLING:
453 level |= mask;
454 polarity &= ~mask;
455 break;
456 case IRQ_TYPE_LEVEL_HIGH:
457 level &= ~mask;
458 polarity |= mask;
459 break;
460 case IRQ_TYPE_LEVEL_LOW:
461 level &= ~mask;
462 polarity &= ~mask;
463 break;
464 default:
465 ret = -EINVAL;
466 goto out;
467 }
468 }
469
470 rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
471 rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
472 out:
473 raw_spin_unlock_irqrestore(&bank->slock, flags);
474
475 return ret;
476 }
477
rockchip_irq_suspend(struct irq_data * d)478 static void rockchip_irq_suspend(struct irq_data *d)
479 {
480 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
481 struct rockchip_pin_bank *bank = gc->private;
482
483 bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
484 irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
485 }
486
rockchip_irq_resume(struct irq_data * d)487 static void rockchip_irq_resume(struct irq_data *d)
488 {
489 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
490 struct rockchip_pin_bank *bank = gc->private;
491
492 irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
493 }
494
rockchip_irq_enable(struct irq_data * d)495 static void rockchip_irq_enable(struct irq_data *d)
496 {
497 irq_gc_mask_clr_bit(d);
498 }
499
rockchip_irq_disable(struct irq_data * d)500 static void rockchip_irq_disable(struct irq_data *d)
501 {
502 irq_gc_mask_set_bit(d);
503 }
504
rockchip_interrupts_register(struct rockchip_pin_bank * bank)505 static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
506 {
507 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
508 struct irq_chip_generic *gc;
509 int ret;
510
511 bank->domain = irq_domain_add_linear(bank->of_node, 32,
512 &irq_generic_chip_ops, NULL);
513 if (!bank->domain) {
514 dev_warn(bank->dev, "could not init irq domain for bank %s\n",
515 bank->name);
516 return -EINVAL;
517 }
518
519 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
520 "rockchip_gpio_irq",
521 handle_level_irq,
522 clr, 0, 0);
523 if (ret) {
524 dev_err(bank->dev, "could not alloc generic chips for bank %s\n",
525 bank->name);
526 irq_domain_remove(bank->domain);
527 return -EINVAL;
528 }
529
530 gc = irq_get_domain_generic_chip(bank->domain, 0);
531 if (bank->gpio_type == GPIO_TYPE_V2) {
532 gc->reg_writel = gpio_writel_v2;
533 gc->reg_readl = gpio_readl_v2;
534 }
535
536 gc->reg_base = bank->reg_base;
537 gc->private = bank;
538 gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
539 gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
540 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
541 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
542 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
543 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
544 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
545 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
546 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
547 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
548 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
549 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
550
551 /*
552 * Linux assumes that all interrupts start out disabled/masked.
553 * Our driver only uses the concept of masked and always keeps
554 * things enabled, so for us that's all masked and all enabled.
555 */
556 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask);
557 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi);
558 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);
559 gc->mask_cache = 0xffffffff;
560
561 irq_set_chained_handler_and_data(bank->irq,
562 rockchip_irq_demux, bank);
563
564 return 0;
565 }
566
rockchip_gpiolib_register(struct rockchip_pin_bank * bank)567 static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)
568 {
569 struct gpio_chip *gc;
570 int ret;
571
572 bank->gpio_chip = rockchip_gpiolib_chip;
573
574 gc = &bank->gpio_chip;
575 gc->base = bank->pin_base;
576 gc->ngpio = bank->nr_pins;
577 gc->label = bank->name;
578 gc->parent = bank->dev;
579 #ifdef CONFIG_OF_GPIO
580 gc->of_node = of_node_get(bank->of_node);
581 #endif
582
583 ret = gpiochip_add_data(gc, bank);
584 if (ret) {
585 dev_err(bank->dev, "failed to add gpiochip %s, %d\n",
586 gc->label, ret);
587 return ret;
588 }
589
590 /*
591 * For DeviceTree-supported systems, the gpio core checks the
592 * pinctrl's device node for the "gpio-ranges" property.
593 * If it is present, it takes care of adding the pin ranges
594 * for the driver. In this case the driver can skip ahead.
595 *
596 * In order to remain compatible with older, existing DeviceTree
597 * files which don't set the "gpio-ranges" property or systems that
598 * utilize ACPI the driver has to call gpiochip_add_pin_range().
599 */
600 if (!of_property_read_bool(bank->of_node, "gpio-ranges")) {
601 struct device_node *pctlnp = of_get_parent(bank->of_node);
602 struct pinctrl_dev *pctldev = NULL;
603
604 if (!pctlnp)
605 return -ENODATA;
606
607 pctldev = of_pinctrl_get(pctlnp);
608 of_node_put(pctlnp);
609 if (!pctldev)
610 return -ENODEV;
611
612 ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0,
613 gc->base, gc->ngpio);
614 if (ret) {
615 dev_err(bank->dev, "Failed to add pin range\n");
616 goto fail;
617 }
618 }
619
620 ret = rockchip_interrupts_register(bank);
621 if (ret) {
622 dev_err(bank->dev, "failed to register interrupt, %d\n", ret);
623 goto fail;
624 }
625
626 return 0;
627
628 fail:
629 gpiochip_remove(&bank->gpio_chip);
630
631 return ret;
632 }
633
rockchip_get_bank_data(struct rockchip_pin_bank * bank)634 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
635 {
636 struct resource res;
637 int id = 0;
638
639 if (of_address_to_resource(bank->of_node, 0, &res)) {
640 dev_err(bank->dev, "cannot find IO resource for bank\n");
641 return -ENOENT;
642 }
643
644 bank->reg_base = devm_ioremap_resource(bank->dev, &res);
645 if (IS_ERR(bank->reg_base))
646 return PTR_ERR(bank->reg_base);
647
648 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
649 if (!bank->irq)
650 return -EINVAL;
651
652 bank->clk = of_clk_get(bank->of_node, 0);
653 if (IS_ERR(bank->clk))
654 return PTR_ERR(bank->clk);
655
656 clk_prepare_enable(bank->clk);
657 id = readl(bank->reg_base + gpio_regs_v2.version_id);
658
659 /* If not gpio v2, that is default to v1. */
660 if (id == GPIO_TYPE_V2) {
661 bank->gpio_regs = &gpio_regs_v2;
662 bank->gpio_type = GPIO_TYPE_V2;
663 bank->db_clk = of_clk_get(bank->of_node, 1);
664 if (IS_ERR(bank->db_clk)) {
665 dev_err(bank->dev, "cannot find debounce clk\n");
666 clk_disable_unprepare(bank->clk);
667 return -EINVAL;
668 }
669 } else {
670 bank->gpio_regs = &gpio_regs_v1;
671 bank->gpio_type = GPIO_TYPE_V1;
672 }
673
674 return 0;
675 }
676
677 static struct rockchip_pin_bank *
rockchip_gpio_find_bank(struct pinctrl_dev * pctldev,int id)678 rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id)
679 {
680 struct rockchip_pinctrl *info;
681 struct rockchip_pin_bank *bank;
682 int i, found = 0;
683
684 info = pinctrl_dev_get_drvdata(pctldev);
685 bank = info->ctrl->pin_banks;
686 for (i = 0; i < info->ctrl->nr_banks; i++, bank++) {
687 if (bank->bank_num == id) {
688 found = 1;
689 break;
690 }
691 }
692
693 return found ? bank : NULL;
694 }
695
rockchip_gpio_probe(struct platform_device * pdev)696 static int rockchip_gpio_probe(struct platform_device *pdev)
697 {
698 struct device *dev = &pdev->dev;
699 struct device_node *np = dev->of_node;
700 struct device_node *pctlnp = of_get_parent(np);
701 struct pinctrl_dev *pctldev = NULL;
702 struct rockchip_pin_bank *bank = NULL;
703 struct rockchip_pin_deferred *cfg;
704 static int gpio;
705 int id, ret;
706
707 if (!np || !pctlnp)
708 return -ENODEV;
709
710 pctldev = of_pinctrl_get(pctlnp);
711 if (!pctldev)
712 return -EPROBE_DEFER;
713
714 id = of_alias_get_id(np, "gpio");
715 if (id < 0)
716 id = gpio++;
717
718 bank = rockchip_gpio_find_bank(pctldev, id);
719 if (!bank)
720 return -EINVAL;
721
722 bank->dev = dev;
723 bank->of_node = np;
724
725 raw_spin_lock_init(&bank->slock);
726
727 ret = rockchip_get_bank_data(bank);
728 if (ret)
729 return ret;
730
731 /*
732 * Prevent clashes with a deferred output setting
733 * being added right at this moment.
734 */
735 mutex_lock(&bank->deferred_lock);
736
737 ret = rockchip_gpiolib_register(bank);
738 if (ret) {
739 clk_disable_unprepare(bank->clk);
740 mutex_unlock(&bank->deferred_lock);
741 return ret;
742 }
743
744 while (!list_empty(&bank->deferred_pins)) {
745 cfg = list_first_entry(&bank->deferred_pins,
746 struct rockchip_pin_deferred, head);
747 list_del(&cfg->head);
748
749 switch (cfg->param) {
750 case PIN_CONFIG_OUTPUT:
751 ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg);
752 if (ret)
753 dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin,
754 cfg->arg);
755 break;
756 default:
757 dev_warn(dev, "unknown deferred config param %d\n", cfg->param);
758 break;
759 }
760 kfree(cfg);
761 }
762
763 mutex_unlock(&bank->deferred_lock);
764
765 platform_set_drvdata(pdev, bank);
766 dev_info(dev, "probed %pOF\n", np);
767
768 return 0;
769 }
770
rockchip_gpio_remove(struct platform_device * pdev)771 static int rockchip_gpio_remove(struct platform_device *pdev)
772 {
773 struct rockchip_pin_bank *bank = platform_get_drvdata(pdev);
774
775 clk_disable_unprepare(bank->clk);
776 gpiochip_remove(&bank->gpio_chip);
777
778 return 0;
779 }
780
781 static const struct of_device_id rockchip_gpio_match[] = {
782 { .compatible = "rockchip,gpio-bank", },
783 { .compatible = "rockchip,rk3188-gpio-bank0" },
784 { },
785 };
786
787 static struct platform_driver rockchip_gpio_driver = {
788 .probe = rockchip_gpio_probe,
789 .remove = rockchip_gpio_remove,
790 .driver = {
791 .name = "rockchip-gpio",
792 .of_match_table = rockchip_gpio_match,
793 },
794 };
795
rockchip_gpio_init(void)796 static int __init rockchip_gpio_init(void)
797 {
798 return platform_driver_register(&rockchip_gpio_driver);
799 }
800 postcore_initcall(rockchip_gpio_init);
801
rockchip_gpio_exit(void)802 static void __exit rockchip_gpio_exit(void)
803 {
804 platform_driver_unregister(&rockchip_gpio_driver);
805 }
806 module_exit(rockchip_gpio_exit);
807
808 MODULE_DESCRIPTION("Rockchip gpio driver");
809 MODULE_ALIAS("platform:rockchip-gpio");
810 MODULE_LICENSE("GPL v2");
811 MODULE_DEVICE_TABLE(of, rockchip_gpio_match);
812