1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016-2017 NVIDIA Corporation
4 *
5 * Author: Thierry Reding <treding@nvidia.com>
6 */
7
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14
15 #include <dt-bindings/gpio/tegra186-gpio.h>
16 #include <dt-bindings/gpio/tegra194-gpio.h>
17
18 /* security registers */
19 #define TEGRA186_GPIO_CTL_SCR 0x0c
20 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
21 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
22
23 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
24
25 /* control registers */
26 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
27 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
28 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
29 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
30 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
31 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
32 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
33 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
34 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
35 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
36 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
37
38 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
39 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
40
41 #define TEGRA186_GPIO_INPUT 0x08
42 #define TEGRA186_GPIO_INPUT_HIGH BIT(0)
43
44 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
45 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
46
47 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
48 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
49
50 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
51
52 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
53
54 struct tegra_gpio_port {
55 const char *name;
56 unsigned int bank;
57 unsigned int port;
58 unsigned int pins;
59 };
60
61 struct tegra186_pin_range {
62 unsigned int offset;
63 const char *group;
64 };
65
66 struct tegra_gpio_soc {
67 const struct tegra_gpio_port *ports;
68 unsigned int num_ports;
69 const char *name;
70 unsigned int instance;
71
72 const struct tegra186_pin_range *pin_ranges;
73 unsigned int num_pin_ranges;
74 const char *pinmux;
75 };
76
77 struct tegra_gpio {
78 struct gpio_chip gpio;
79 struct irq_chip intc;
80 unsigned int num_irq;
81 unsigned int *irq;
82
83 const struct tegra_gpio_soc *soc;
84
85 void __iomem *secure;
86 void __iomem *base;
87 };
88
89 static const struct tegra_gpio_port *
tegra186_gpio_get_port(struct tegra_gpio * gpio,unsigned int * pin)90 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
91 {
92 unsigned int start = 0, i;
93
94 for (i = 0; i < gpio->soc->num_ports; i++) {
95 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
96
97 if (*pin >= start && *pin < start + port->pins) {
98 *pin -= start;
99 return port;
100 }
101
102 start += port->pins;
103 }
104
105 return NULL;
106 }
107
tegra186_gpio_get_base(struct tegra_gpio * gpio,unsigned int pin)108 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
109 unsigned int pin)
110 {
111 const struct tegra_gpio_port *port;
112 unsigned int offset;
113
114 port = tegra186_gpio_get_port(gpio, &pin);
115 if (!port)
116 return NULL;
117
118 offset = port->bank * 0x1000 + port->port * 0x200;
119
120 return gpio->base + offset + pin * 0x20;
121 }
122
tegra186_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)123 static int tegra186_gpio_get_direction(struct gpio_chip *chip,
124 unsigned int offset)
125 {
126 struct tegra_gpio *gpio = gpiochip_get_data(chip);
127 void __iomem *base;
128 u32 value;
129
130 base = tegra186_gpio_get_base(gpio, offset);
131 if (WARN_ON(base == NULL))
132 return -ENODEV;
133
134 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
135 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
136 return GPIO_LINE_DIRECTION_OUT;
137
138 return GPIO_LINE_DIRECTION_IN;
139 }
140
tegra186_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)141 static int tegra186_gpio_direction_input(struct gpio_chip *chip,
142 unsigned int offset)
143 {
144 struct tegra_gpio *gpio = gpiochip_get_data(chip);
145 void __iomem *base;
146 u32 value;
147
148 base = tegra186_gpio_get_base(gpio, offset);
149 if (WARN_ON(base == NULL))
150 return -ENODEV;
151
152 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
153 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
154 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
155
156 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
157 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
158 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
159 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
160
161 return 0;
162 }
163
tegra186_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int level)164 static int tegra186_gpio_direction_output(struct gpio_chip *chip,
165 unsigned int offset, int level)
166 {
167 struct tegra_gpio *gpio = gpiochip_get_data(chip);
168 void __iomem *base;
169 u32 value;
170
171 /* configure output level first */
172 chip->set(chip, offset, level);
173
174 base = tegra186_gpio_get_base(gpio, offset);
175 if (WARN_ON(base == NULL))
176 return -EINVAL;
177
178 /* set the direction */
179 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
180 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
181 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
182
183 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
184 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
185 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
186 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
187
188 return 0;
189 }
190
tegra186_gpio_get(struct gpio_chip * chip,unsigned int offset)191 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
192 {
193 struct tegra_gpio *gpio = gpiochip_get_data(chip);
194 void __iomem *base;
195 u32 value;
196
197 base = tegra186_gpio_get_base(gpio, offset);
198 if (WARN_ON(base == NULL))
199 return -ENODEV;
200
201 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
202 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
203 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
204 else
205 value = readl(base + TEGRA186_GPIO_INPUT);
206
207 return value & BIT(0);
208 }
209
tegra186_gpio_set(struct gpio_chip * chip,unsigned int offset,int level)210 static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
211 int level)
212 {
213 struct tegra_gpio *gpio = gpiochip_get_data(chip);
214 void __iomem *base;
215 u32 value;
216
217 base = tegra186_gpio_get_base(gpio, offset);
218 if (WARN_ON(base == NULL))
219 return;
220
221 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
222 if (level == 0)
223 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
224 else
225 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
226
227 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
228 }
229
tegra186_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)230 static int tegra186_gpio_set_config(struct gpio_chip *chip,
231 unsigned int offset,
232 unsigned long config)
233 {
234 struct tegra_gpio *gpio = gpiochip_get_data(chip);
235 u32 debounce, value;
236 void __iomem *base;
237
238 base = tegra186_gpio_get_base(gpio, offset);
239 if (base == NULL)
240 return -ENXIO;
241
242 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
243 return -ENOTSUPP;
244
245 debounce = pinconf_to_config_argument(config);
246
247 /*
248 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
249 * time.
250 */
251 if (debounce > 255000)
252 return -EINVAL;
253
254 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
255
256 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
257 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
258
259 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
260 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
261 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
262
263 return 0;
264 }
265
tegra186_gpio_add_pin_ranges(struct gpio_chip * chip)266 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
267 {
268 struct tegra_gpio *gpio = gpiochip_get_data(chip);
269 struct pinctrl_dev *pctldev;
270 struct device_node *np;
271 unsigned int i, j;
272 int err;
273
274 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
275 return 0;
276
277 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
278 if (!np)
279 return -ENODEV;
280
281 pctldev = of_pinctrl_get(np);
282 of_node_put(np);
283 if (!pctldev)
284 return -EPROBE_DEFER;
285
286 for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
287 unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
288 const char *group = gpio->soc->pin_ranges[i].group;
289
290 port = pin / 8;
291 pin = pin % 8;
292
293 if (port >= gpio->soc->num_ports) {
294 dev_warn(chip->parent, "invalid port %u for %s\n",
295 port, group);
296 continue;
297 }
298
299 for (j = 0; j < port; j++)
300 pin += gpio->soc->ports[j].pins;
301
302 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
303 if (err < 0)
304 return err;
305 }
306
307 return 0;
308 }
309
tegra186_gpio_of_xlate(struct gpio_chip * chip,const struct of_phandle_args * spec,u32 * flags)310 static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
311 const struct of_phandle_args *spec,
312 u32 *flags)
313 {
314 struct tegra_gpio *gpio = gpiochip_get_data(chip);
315 unsigned int port, pin, i, offset = 0;
316
317 if (WARN_ON(chip->of_gpio_n_cells < 2))
318 return -EINVAL;
319
320 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
321 return -EINVAL;
322
323 port = spec->args[0] / 8;
324 pin = spec->args[0] % 8;
325
326 if (port >= gpio->soc->num_ports) {
327 dev_err(chip->parent, "invalid port number: %u\n", port);
328 return -EINVAL;
329 }
330
331 for (i = 0; i < port; i++)
332 offset += gpio->soc->ports[i].pins;
333
334 if (flags)
335 *flags = spec->args[1];
336
337 return offset + pin;
338 }
339
340 #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)
341
tegra186_irq_ack(struct irq_data * data)342 static void tegra186_irq_ack(struct irq_data *data)
343 {
344 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
345 struct tegra_gpio *gpio = to_tegra_gpio(gc);
346 void __iomem *base;
347
348 base = tegra186_gpio_get_base(gpio, data->hwirq);
349 if (WARN_ON(base == NULL))
350 return;
351
352 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
353 }
354
tegra186_irq_mask(struct irq_data * data)355 static void tegra186_irq_mask(struct irq_data *data)
356 {
357 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
358 struct tegra_gpio *gpio = to_tegra_gpio(gc);
359 void __iomem *base;
360 u32 value;
361
362 base = tegra186_gpio_get_base(gpio, data->hwirq);
363 if (WARN_ON(base == NULL))
364 return;
365
366 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
367 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
368 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
369 }
370
tegra186_irq_unmask(struct irq_data * data)371 static void tegra186_irq_unmask(struct irq_data *data)
372 {
373 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
374 struct tegra_gpio *gpio = to_tegra_gpio(gc);
375 void __iomem *base;
376 u32 value;
377
378 base = tegra186_gpio_get_base(gpio, data->hwirq);
379 if (WARN_ON(base == NULL))
380 return;
381
382 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
383 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
384 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
385 }
386
tegra186_irq_set_type(struct irq_data * data,unsigned int type)387 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
388 {
389 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
390 struct tegra_gpio *gpio = to_tegra_gpio(gc);
391 void __iomem *base;
392 u32 value;
393
394 base = tegra186_gpio_get_base(gpio, data->hwirq);
395 if (WARN_ON(base == NULL))
396 return -ENODEV;
397
398 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
399 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
400 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
401
402 switch (type & IRQ_TYPE_SENSE_MASK) {
403 case IRQ_TYPE_NONE:
404 break;
405
406 case IRQ_TYPE_EDGE_RISING:
407 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
408 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
409 break;
410
411 case IRQ_TYPE_EDGE_FALLING:
412 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
413 break;
414
415 case IRQ_TYPE_EDGE_BOTH:
416 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
417 break;
418
419 case IRQ_TYPE_LEVEL_HIGH:
420 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
421 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
422 break;
423
424 case IRQ_TYPE_LEVEL_LOW:
425 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
426 break;
427
428 default:
429 return -EINVAL;
430 }
431
432 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
433
434 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
435 irq_set_handler_locked(data, handle_level_irq);
436 else
437 irq_set_handler_locked(data, handle_edge_irq);
438
439 if (data->parent_data)
440 return irq_chip_set_type_parent(data, type);
441
442 return 0;
443 }
444
tegra186_irq_set_wake(struct irq_data * data,unsigned int on)445 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
446 {
447 if (data->parent_data)
448 return irq_chip_set_wake_parent(data, on);
449
450 return 0;
451 }
452
tegra186_gpio_irq(struct irq_desc * desc)453 static void tegra186_gpio_irq(struct irq_desc *desc)
454 {
455 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
456 struct irq_domain *domain = gpio->gpio.irq.domain;
457 struct irq_chip *chip = irq_desc_get_chip(desc);
458 unsigned int parent = irq_desc_get_irq(desc);
459 unsigned int i, offset = 0;
460
461 chained_irq_enter(chip, desc);
462
463 for (i = 0; i < gpio->soc->num_ports; i++) {
464 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
465 unsigned int pin;
466 unsigned long value;
467 void __iomem *base;
468
469 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
470
471 /* skip ports that are not associated with this bank */
472 if (parent != gpio->irq[port->bank])
473 goto skip;
474
475 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
476
477 for_each_set_bit(pin, &value, port->pins) {
478 int ret = generic_handle_domain_irq(domain, offset + pin);
479 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
480 }
481
482 skip:
483 offset += port->pins;
484 }
485
486 chained_irq_exit(chip, desc);
487 }
488
tegra186_gpio_irq_domain_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)489 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
490 struct irq_fwspec *fwspec,
491 unsigned long *hwirq,
492 unsigned int *type)
493 {
494 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
495 unsigned int port, pin, i, offset = 0;
496
497 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
498 return -EINVAL;
499
500 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
501 return -EINVAL;
502
503 port = fwspec->param[0] / 8;
504 pin = fwspec->param[0] % 8;
505
506 if (port >= gpio->soc->num_ports)
507 return -EINVAL;
508
509 for (i = 0; i < port; i++)
510 offset += gpio->soc->ports[i].pins;
511
512 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
513 *hwirq = offset + pin;
514
515 return 0;
516 }
517
tegra186_gpio_populate_parent_fwspec(struct gpio_chip * chip,unsigned int parent_hwirq,unsigned int parent_type)518 static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
519 unsigned int parent_hwirq,
520 unsigned int parent_type)
521 {
522 struct tegra_gpio *gpio = gpiochip_get_data(chip);
523 struct irq_fwspec *fwspec;
524
525 fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL);
526 if (!fwspec)
527 return NULL;
528
529 fwspec->fwnode = chip->irq.parent_domain->fwnode;
530 fwspec->param_count = 3;
531 fwspec->param[0] = gpio->soc->instance;
532 fwspec->param[1] = parent_hwirq;
533 fwspec->param[2] = parent_type;
534
535 return fwspec;
536 }
537
tegra186_gpio_child_to_parent_hwirq(struct gpio_chip * chip,unsigned int hwirq,unsigned int type,unsigned int * parent_hwirq,unsigned int * parent_type)538 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
539 unsigned int hwirq,
540 unsigned int type,
541 unsigned int *parent_hwirq,
542 unsigned int *parent_type)
543 {
544 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
545 *parent_type = type;
546
547 return 0;
548 }
549
tegra186_gpio_child_offset_to_irq(struct gpio_chip * chip,unsigned int offset)550 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
551 unsigned int offset)
552 {
553 struct tegra_gpio *gpio = gpiochip_get_data(chip);
554 unsigned int i;
555
556 for (i = 0; i < gpio->soc->num_ports; i++) {
557 if (offset < gpio->soc->ports[i].pins)
558 break;
559
560 offset -= gpio->soc->ports[i].pins;
561 }
562
563 return offset + i * 8;
564 }
565
566 static const struct of_device_id tegra186_pmc_of_match[] = {
567 { .compatible = "nvidia,tegra186-pmc" },
568 { .compatible = "nvidia,tegra194-pmc" },
569 { /* sentinel */ }
570 };
571
tegra186_gpio_init_route_mapping(struct tegra_gpio * gpio)572 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
573 {
574 unsigned int i, j;
575 u32 value;
576
577 for (i = 0; i < gpio->soc->num_ports; i++) {
578 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
579 unsigned int offset, p = port->port;
580 void __iomem *base;
581
582 base = gpio->secure + port->bank * 0x1000 + 0x800;
583
584 value = readl(base + TEGRA186_GPIO_CTL_SCR);
585
586 /*
587 * For controllers that haven't been locked down yet, make
588 * sure to program the default interrupt route mapping.
589 */
590 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
591 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
592 for (j = 0; j < 8; j++) {
593 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j);
594
595 value = readl(base + offset);
596 value = BIT(port->pins) - 1;
597 writel(value, base + offset);
598 }
599 }
600 }
601 }
602
tegra186_gpio_probe(struct platform_device * pdev)603 static int tegra186_gpio_probe(struct platform_device *pdev)
604 {
605 unsigned int i, j, offset;
606 struct gpio_irq_chip *irq;
607 struct tegra_gpio *gpio;
608 struct device_node *np;
609 char **names;
610 int err;
611
612 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
613 if (!gpio)
614 return -ENOMEM;
615
616 gpio->soc = device_get_match_data(&pdev->dev);
617
618 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
619 if (IS_ERR(gpio->secure)) {
620 gpio->secure = devm_platform_ioremap_resource(pdev, 0);
621 if (IS_ERR(gpio->secure))
622 return PTR_ERR(gpio->secure);
623 }
624
625 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
626 if (IS_ERR(gpio->base)) {
627 gpio->base = devm_platform_ioremap_resource(pdev, 1);
628 if (IS_ERR(gpio->base))
629 return PTR_ERR(gpio->base);
630 }
631
632 err = platform_irq_count(pdev);
633 if (err < 0)
634 return err;
635
636 gpio->num_irq = err;
637
638 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
639 GFP_KERNEL);
640 if (!gpio->irq)
641 return -ENOMEM;
642
643 for (i = 0; i < gpio->num_irq; i++) {
644 err = platform_get_irq(pdev, i);
645 if (err < 0)
646 return err;
647
648 gpio->irq[i] = err;
649 }
650
651 gpio->gpio.label = gpio->soc->name;
652 gpio->gpio.parent = &pdev->dev;
653
654 gpio->gpio.request = gpiochip_generic_request;
655 gpio->gpio.free = gpiochip_generic_free;
656 gpio->gpio.get_direction = tegra186_gpio_get_direction;
657 gpio->gpio.direction_input = tegra186_gpio_direction_input;
658 gpio->gpio.direction_output = tegra186_gpio_direction_output;
659 gpio->gpio.get = tegra186_gpio_get;
660 gpio->gpio.set = tegra186_gpio_set;
661 gpio->gpio.set_config = tegra186_gpio_set_config;
662 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
663
664 gpio->gpio.base = -1;
665
666 for (i = 0; i < gpio->soc->num_ports; i++)
667 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
668
669 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
670 sizeof(*names), GFP_KERNEL);
671 if (!names)
672 return -ENOMEM;
673
674 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
675 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
676 char *name;
677
678 for (j = 0; j < port->pins; j++) {
679 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
680 "P%s.%02x", port->name, j);
681 if (!name)
682 return -ENOMEM;
683
684 names[offset + j] = name;
685 }
686
687 offset += port->pins;
688 }
689
690 gpio->gpio.names = (const char * const *)names;
691
692 #if defined(CONFIG_OF_GPIO)
693 gpio->gpio.of_node = pdev->dev.of_node;
694 gpio->gpio.of_gpio_n_cells = 2;
695 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
696 #endif /* CONFIG_OF_GPIO */
697
698 gpio->intc.name = dev_name(&pdev->dev);
699 gpio->intc.irq_ack = tegra186_irq_ack;
700 gpio->intc.irq_mask = tegra186_irq_mask;
701 gpio->intc.irq_unmask = tegra186_irq_unmask;
702 gpio->intc.irq_set_type = tegra186_irq_set_type;
703 gpio->intc.irq_set_wake = tegra186_irq_set_wake;
704
705 irq = &gpio->gpio.irq;
706 irq->chip = &gpio->intc;
707 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
708 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
709 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
710 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
711 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
712 irq->handler = handle_simple_irq;
713 irq->default_type = IRQ_TYPE_NONE;
714 irq->parent_handler = tegra186_gpio_irq;
715 irq->parent_handler_data = gpio;
716 irq->num_parents = gpio->num_irq;
717 irq->parents = gpio->irq;
718
719 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
720 if (np) {
721 irq->parent_domain = irq_find_host(np);
722 of_node_put(np);
723
724 if (!irq->parent_domain)
725 return -EPROBE_DEFER;
726 }
727
728 tegra186_gpio_init_route_mapping(gpio);
729
730 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
731 sizeof(*irq->map), GFP_KERNEL);
732 if (!irq->map)
733 return -ENOMEM;
734
735 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
736 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
737
738 for (j = 0; j < port->pins; j++)
739 irq->map[offset + j] = irq->parents[port->bank];
740
741 offset += port->pins;
742 }
743
744 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
745 }
746
747 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
748 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
749 .name = #_name, \
750 .bank = _bank, \
751 .port = _port, \
752 .pins = _pins, \
753 }
754
755 static const struct tegra_gpio_port tegra186_main_ports[] = {
756 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
757 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
758 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
759 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
760 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
761 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
762 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
763 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
764 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
765 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
766 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
767 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
768 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
769 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
770 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
771 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
772 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
773 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
774 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
775 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
776 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
777 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
778 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
779 };
780
781 static const struct tegra_gpio_soc tegra186_main_soc = {
782 .num_ports = ARRAY_SIZE(tegra186_main_ports),
783 .ports = tegra186_main_ports,
784 .name = "tegra186-gpio",
785 .instance = 0,
786 };
787
788 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
789 [TEGRA186_AON_GPIO_PORT_##_name] = { \
790 .name = #_name, \
791 .bank = _bank, \
792 .port = _port, \
793 .pins = _pins, \
794 }
795
796 static const struct tegra_gpio_port tegra186_aon_ports[] = {
797 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
798 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
799 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
800 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
801 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
802 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
803 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
804 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
805 };
806
807 static const struct tegra_gpio_soc tegra186_aon_soc = {
808 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
809 .ports = tegra186_aon_ports,
810 .name = "tegra186-gpio-aon",
811 .instance = 1,
812 };
813
814 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
815 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
816 .name = #_name, \
817 .bank = _bank, \
818 .port = _port, \
819 .pins = _pins, \
820 }
821
822 static const struct tegra_gpio_port tegra194_main_ports[] = {
823 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
824 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
825 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
826 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
827 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
828 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
829 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
830 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
831 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
832 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
833 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
834 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
835 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
836 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
837 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
838 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
839 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
840 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
841 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
842 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
843 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
844 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
845 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
846 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
847 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
848 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
849 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
850 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
851 };
852
853 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
854 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
855 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
856 };
857
858 static const struct tegra_gpio_soc tegra194_main_soc = {
859 .num_ports = ARRAY_SIZE(tegra194_main_ports),
860 .ports = tegra194_main_ports,
861 .name = "tegra194-gpio",
862 .instance = 0,
863 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
864 .pin_ranges = tegra194_main_pin_ranges,
865 .pinmux = "nvidia,tegra194-pinmux",
866 };
867
868 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
869 [TEGRA194_AON_GPIO_PORT_##_name] = { \
870 .name = #_name, \
871 .bank = _bank, \
872 .port = _port, \
873 .pins = _pins, \
874 }
875
876 static const struct tegra_gpio_port tegra194_aon_ports[] = {
877 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
878 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
879 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
880 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
881 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
882 };
883
884 static const struct tegra_gpio_soc tegra194_aon_soc = {
885 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
886 .ports = tegra194_aon_ports,
887 .name = "tegra194-gpio-aon",
888 .instance = 1,
889 };
890
891 static const struct of_device_id tegra186_gpio_of_match[] = {
892 {
893 .compatible = "nvidia,tegra186-gpio",
894 .data = &tegra186_main_soc
895 }, {
896 .compatible = "nvidia,tegra186-gpio-aon",
897 .data = &tegra186_aon_soc
898 }, {
899 .compatible = "nvidia,tegra194-gpio",
900 .data = &tegra194_main_soc
901 }, {
902 .compatible = "nvidia,tegra194-gpio-aon",
903 .data = &tegra194_aon_soc
904 }, {
905 /* sentinel */
906 }
907 };
908 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
909
910 static const struct acpi_device_id tegra186_gpio_acpi_match[] = {
911 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc },
912 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc },
913 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc },
914 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
915 {}
916 };
917 MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);
918
919 static struct platform_driver tegra186_gpio_driver = {
920 .driver = {
921 .name = "tegra186-gpio",
922 .of_match_table = tegra186_gpio_of_match,
923 .acpi_match_table = tegra186_gpio_acpi_match,
924 },
925 .probe = tegra186_gpio_probe,
926 };
927 module_platform_driver(tegra186_gpio_driver);
928
929 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
930 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
931 MODULE_LICENSE("GPL v2");
932