1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dce/dce_8_0_d.h"
29 #include "dce/dce_8_0_sh_mask.h"
30
31 #include "dm_services.h"
32
33 #include "link_encoder.h"
34 #include "stream_encoder.h"
35
36 #include "resource.h"
37 #include "include/irq_service_interface.h"
38 #include "irq/dce80/irq_service_dce80.h"
39 #include "dce110/dce110_timing_generator.h"
40 #include "dce110/dce110_resource.h"
41 #include "dce80/dce80_timing_generator.h"
42 #include "dce/dce_mem_input.h"
43 #include "dce/dce_link_encoder.h"
44 #include "dce/dce_stream_encoder.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_transform.h"
47 #include "dce/dce_opp.h"
48 #include "dce/dce_clock_source.h"
49 #include "dce/dce_audio.h"
50 #include "dce/dce_hwseq.h"
51 #include "dce80/dce80_hw_sequencer.h"
52 #include "dce100/dce100_resource.h"
53 #include "dce/dce_panel_cntl.h"
54
55 #include "reg_helper.h"
56
57 #include "dce/dce_dmcu.h"
58 #include "dce/dce_aux.h"
59 #include "dce/dce_abm.h"
60 #include "dce/dce_i2c.h"
61 /* TODO remove this include */
62
63 #include "dce80_resource.h"
64
65 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
66 #include "gmc/gmc_7_1_d.h"
67 #include "gmc/gmc_7_1_sh_mask.h"
68 #endif
69
70 #ifndef mmDP_DPHY_INTERNAL_CTRL
71 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE
72 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE
73 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE
74 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE
75 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE
76 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE
77 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE
78 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE
79 #endif
80
81
82 #ifndef mmBIOS_SCRATCH_2
83 #define mmBIOS_SCRATCH_2 0x05CB
84 #define mmBIOS_SCRATCH_3 0x05CC
85 #define mmBIOS_SCRATCH_6 0x05CF
86 #endif
87
88 #ifndef mmDP_DPHY_FAST_TRAINING
89 #define mmDP_DPHY_FAST_TRAINING 0x1CCE
90 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE
91 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE
92 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE
93 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE
94 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE
95 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE
96 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE
97 #endif
98
99
100 #ifndef mmHPD_DC_HPD_CONTROL
101 #define mmHPD_DC_HPD_CONTROL 0x189A
102 #define mmHPD0_DC_HPD_CONTROL 0x189A
103 #define mmHPD1_DC_HPD_CONTROL 0x18A2
104 #define mmHPD2_DC_HPD_CONTROL 0x18AA
105 #define mmHPD3_DC_HPD_CONTROL 0x18B2
106 #define mmHPD4_DC_HPD_CONTROL 0x18BA
107 #define mmHPD5_DC_HPD_CONTROL 0x18C2
108 #endif
109
110 #define DCE11_DIG_FE_CNTL 0x4a00
111 #define DCE11_DIG_BE_CNTL 0x4a47
112 #define DCE11_DP_SEC 0x4ac3
113
114 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
115 {
116 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
117 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
118 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
119 - mmDPG_WATERMARK_MASK_CONTROL),
120 },
121 {
122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
124 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
125 - mmDPG_WATERMARK_MASK_CONTROL),
126 },
127 {
128 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
129 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
130 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
131 - mmDPG_WATERMARK_MASK_CONTROL),
132 },
133 {
134 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
135 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
136 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
137 - mmDPG_WATERMARK_MASK_CONTROL),
138 },
139 {
140 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
141 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
142 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
143 - mmDPG_WATERMARK_MASK_CONTROL),
144 },
145 {
146 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
147 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
148 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
149 - mmDPG_WATERMARK_MASK_CONTROL),
150 }
151 };
152
153 /* set register offset */
154 #define SR(reg_name)\
155 .reg_name = mm ## reg_name
156
157 /* set register offset with instance */
158 #define SRI(reg_name, block, id)\
159 .reg_name = mm ## block ## id ## _ ## reg_name
160
161 #define ipp_regs(id)\
162 [id] = {\
163 IPP_COMMON_REG_LIST_DCE_BASE(id)\
164 }
165
166 static const struct dce_ipp_registers ipp_regs[] = {
167 ipp_regs(0),
168 ipp_regs(1),
169 ipp_regs(2),
170 ipp_regs(3),
171 ipp_regs(4),
172 ipp_regs(5)
173 };
174
175 static const struct dce_ipp_shift ipp_shift = {
176 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
177 };
178
179 static const struct dce_ipp_mask ipp_mask = {
180 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
181 };
182
183 #define transform_regs(id)\
184 [id] = {\
185 XFM_COMMON_REG_LIST_DCE80(id)\
186 }
187
188 static const struct dce_transform_registers xfm_regs[] = {
189 transform_regs(0),
190 transform_regs(1),
191 transform_regs(2),
192 transform_regs(3),
193 transform_regs(4),
194 transform_regs(5)
195 };
196
197 static const struct dce_transform_shift xfm_shift = {
198 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
199 };
200
201 static const struct dce_transform_mask xfm_mask = {
202 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
203 };
204
205 #define aux_regs(id)\
206 [id] = {\
207 AUX_REG_LIST(id)\
208 }
209
210 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
211 aux_regs(0),
212 aux_regs(1),
213 aux_regs(2),
214 aux_regs(3),
215 aux_regs(4),
216 aux_regs(5)
217 };
218
219 #define hpd_regs(id)\
220 [id] = {\
221 HPD_REG_LIST(id)\
222 }
223
224 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
225 hpd_regs(0),
226 hpd_regs(1),
227 hpd_regs(2),
228 hpd_regs(3),
229 hpd_regs(4),
230 hpd_regs(5)
231 };
232
233 #define link_regs(id)\
234 [id] = {\
235 LE_DCE80_REG_LIST(id)\
236 }
237
238 static const struct dce110_link_enc_registers link_enc_regs[] = {
239 link_regs(0),
240 link_regs(1),
241 link_regs(2),
242 link_regs(3),
243 link_regs(4),
244 link_regs(5),
245 link_regs(6),
246 };
247
248 #define stream_enc_regs(id)\
249 [id] = {\
250 SE_COMMON_REG_LIST_DCE_BASE(id),\
251 .AFMT_CNTL = 0,\
252 }
253
254 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
255 stream_enc_regs(0),
256 stream_enc_regs(1),
257 stream_enc_regs(2),
258 stream_enc_regs(3),
259 stream_enc_regs(4),
260 stream_enc_regs(5),
261 stream_enc_regs(6)
262 };
263
264 static const struct dce_stream_encoder_shift se_shift = {
265 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
266 };
267
268 static const struct dce_stream_encoder_mask se_mask = {
269 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
270 };
271
272 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
273 { DCE_PANEL_CNTL_REG_LIST() }
274 };
275
276 static const struct dce_panel_cntl_shift panel_cntl_shift = {
277 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
278 };
279
280 static const struct dce_panel_cntl_mask panel_cntl_mask = {
281 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
282 };
283
284 #define opp_regs(id)\
285 [id] = {\
286 OPP_DCE_80_REG_LIST(id),\
287 }
288
289 static const struct dce_opp_registers opp_regs[] = {
290 opp_regs(0),
291 opp_regs(1),
292 opp_regs(2),
293 opp_regs(3),
294 opp_regs(4),
295 opp_regs(5)
296 };
297
298 static const struct dce_opp_shift opp_shift = {
299 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
300 };
301
302 static const struct dce_opp_mask opp_mask = {
303 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
304 };
305
306 static const struct dce110_aux_registers_shift aux_shift = {
307 DCE10_AUX_MASK_SH_LIST(__SHIFT)
308 };
309
310 static const struct dce110_aux_registers_mask aux_mask = {
311 DCE10_AUX_MASK_SH_LIST(_MASK)
312 };
313
314 #define aux_engine_regs(id)\
315 [id] = {\
316 AUX_COMMON_REG_LIST(id), \
317 .AUX_RESET_MASK = 0 \
318 }
319
320 static const struct dce110_aux_registers aux_engine_regs[] = {
321 aux_engine_regs(0),
322 aux_engine_regs(1),
323 aux_engine_regs(2),
324 aux_engine_regs(3),
325 aux_engine_regs(4),
326 aux_engine_regs(5)
327 };
328
329 #define audio_regs(id)\
330 [id] = {\
331 AUD_COMMON_REG_LIST(id)\
332 }
333
334 static const struct dce_audio_registers audio_regs[] = {
335 audio_regs(0),
336 audio_regs(1),
337 audio_regs(2),
338 audio_regs(3),
339 audio_regs(4),
340 audio_regs(5),
341 audio_regs(6),
342 };
343
344 static const struct dce_audio_shift audio_shift = {
345 AUD_COMMON_MASK_SH_LIST(__SHIFT)
346 };
347
348 static const struct dce_audio_mask audio_mask = {
349 AUD_COMMON_MASK_SH_LIST(_MASK)
350 };
351
352 #define clk_src_regs(id)\
353 [id] = {\
354 CS_COMMON_REG_LIST_DCE_80(id),\
355 }
356
357
358 static const struct dce110_clk_src_regs clk_src_regs[] = {
359 clk_src_regs(0),
360 clk_src_regs(1),
361 clk_src_regs(2)
362 };
363
364 static const struct dce110_clk_src_shift cs_shift = {
365 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
366 };
367
368 static const struct dce110_clk_src_mask cs_mask = {
369 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
370 };
371
372 static const struct bios_registers bios_regs = {
373 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
374 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
375 };
376
377 static const struct resource_caps res_cap = {
378 .num_timing_generator = 6,
379 .num_audio = 6,
380 .num_stream_encoder = 6,
381 .num_pll = 3,
382 .num_ddc = 6,
383 };
384
385 static const struct resource_caps res_cap_81 = {
386 .num_timing_generator = 4,
387 .num_audio = 7,
388 .num_stream_encoder = 7,
389 .num_pll = 3,
390 .num_ddc = 6,
391 };
392
393 static const struct resource_caps res_cap_83 = {
394 .num_timing_generator = 2,
395 .num_audio = 6,
396 .num_stream_encoder = 6,
397 .num_pll = 2,
398 .num_ddc = 2,
399 };
400
401 static const struct dc_plane_cap plane_cap = {
402 .type = DC_PLANE_TYPE_DCE_RGB,
403
404 .pixel_format_support = {
405 .argb8888 = true,
406 .nv12 = false,
407 .fp16 = true
408 },
409
410 .max_upscale_factor = {
411 .argb8888 = 16000,
412 .nv12 = 1,
413 .fp16 = 1
414 },
415
416 .max_downscale_factor = {
417 .argb8888 = 250,
418 .nv12 = 1,
419 .fp16 = 1
420 }
421 };
422
423 static const struct dce_dmcu_registers dmcu_regs = {
424 DMCU_DCE80_REG_LIST()
425 };
426
427 static const struct dce_dmcu_shift dmcu_shift = {
428 DMCU_MASK_SH_LIST_DCE80(__SHIFT)
429 };
430
431 static const struct dce_dmcu_mask dmcu_mask = {
432 DMCU_MASK_SH_LIST_DCE80(_MASK)
433 };
434 static const struct dce_abm_registers abm_regs = {
435 ABM_DCE110_COMMON_REG_LIST()
436 };
437
438 static const struct dce_abm_shift abm_shift = {
439 ABM_MASK_SH_LIST_DCE110(__SHIFT)
440 };
441
442 static const struct dce_abm_mask abm_mask = {
443 ABM_MASK_SH_LIST_DCE110(_MASK)
444 };
445
446 #define CTX ctx
447 #define REG(reg) mm ## reg
448
449 #ifndef mmCC_DC_HDMI_STRAPS
450 #define mmCC_DC_HDMI_STRAPS 0x1918
451 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
452 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
453 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
454 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
455 #endif
456
map_transmitter_id_to_phy_instance(enum transmitter transmitter)457 static int map_transmitter_id_to_phy_instance(
458 enum transmitter transmitter)
459 {
460 switch (transmitter) {
461 case TRANSMITTER_UNIPHY_A:
462 return 0;
463 case TRANSMITTER_UNIPHY_B:
464 return 1;
465 case TRANSMITTER_UNIPHY_C:
466 return 2;
467 case TRANSMITTER_UNIPHY_D:
468 return 3;
469 case TRANSMITTER_UNIPHY_E:
470 return 4;
471 case TRANSMITTER_UNIPHY_F:
472 return 5;
473 case TRANSMITTER_UNIPHY_G:
474 return 6;
475 default:
476 ASSERT(0);
477 return 0;
478 }
479 }
480
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)481 static void read_dce_straps(
482 struct dc_context *ctx,
483 struct resource_straps *straps)
484 {
485 REG_GET_2(CC_DC_HDMI_STRAPS,
486 HDMI_DISABLE, &straps->hdmi_disable,
487 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
488
489 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
490 }
491
create_audio(struct dc_context * ctx,unsigned int inst)492 static struct audio *create_audio(
493 struct dc_context *ctx, unsigned int inst)
494 {
495 return dce_audio_create(ctx, inst,
496 &audio_regs[inst], &audio_shift, &audio_mask);
497 }
498
dce80_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)499 static struct timing_generator *dce80_timing_generator_create(
500 struct dc_context *ctx,
501 uint32_t instance,
502 const struct dce110_timing_generator_offsets *offsets)
503 {
504 struct dce110_timing_generator *tg110 =
505 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
506
507 if (!tg110)
508 return NULL;
509
510 dce80_timing_generator_construct(tg110, ctx, instance, offsets);
511 return &tg110->base;
512 }
513
dce80_opp_create(struct dc_context * ctx,uint32_t inst)514 static struct output_pixel_processor *dce80_opp_create(
515 struct dc_context *ctx,
516 uint32_t inst)
517 {
518 struct dce110_opp *opp =
519 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
520
521 if (!opp)
522 return NULL;
523
524 dce110_opp_construct(opp,
525 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
526 return &opp->base;
527 }
528
dce80_aux_engine_create(struct dc_context * ctx,uint32_t inst)529 static struct dce_aux *dce80_aux_engine_create(
530 struct dc_context *ctx,
531 uint32_t inst)
532 {
533 struct aux_engine_dce110 *aux_engine =
534 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
535
536 if (!aux_engine)
537 return NULL;
538
539 dce110_aux_engine_construct(aux_engine, ctx, inst,
540 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
541 &aux_engine_regs[inst],
542 &aux_mask,
543 &aux_shift,
544 ctx->dc->caps.extended_aux_timeout_support);
545
546 return &aux_engine->base;
547 }
548 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
549
550 static const struct dce_i2c_registers i2c_hw_regs[] = {
551 i2c_inst_regs(1),
552 i2c_inst_regs(2),
553 i2c_inst_regs(3),
554 i2c_inst_regs(4),
555 i2c_inst_regs(5),
556 i2c_inst_regs(6),
557 };
558
559 static const struct dce_i2c_shift i2c_shifts = {
560 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
561 };
562
563 static const struct dce_i2c_mask i2c_masks = {
564 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
565 };
566
dce80_i2c_hw_create(struct dc_context * ctx,uint32_t inst)567 static struct dce_i2c_hw *dce80_i2c_hw_create(
568 struct dc_context *ctx,
569 uint32_t inst)
570 {
571 struct dce_i2c_hw *dce_i2c_hw =
572 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
573
574 if (!dce_i2c_hw)
575 return NULL;
576
577 dce_i2c_hw_construct(dce_i2c_hw, ctx, inst,
578 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
579
580 return dce_i2c_hw;
581 }
582
dce80_i2c_sw_create(struct dc_context * ctx)583 static struct dce_i2c_sw *dce80_i2c_sw_create(
584 struct dc_context *ctx)
585 {
586 struct dce_i2c_sw *dce_i2c_sw =
587 kzalloc(sizeof(struct dce_i2c_sw), GFP_KERNEL);
588
589 if (!dce_i2c_sw)
590 return NULL;
591
592 dce_i2c_sw_construct(dce_i2c_sw, ctx);
593
594 return dce_i2c_sw;
595 }
dce80_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)596 static struct stream_encoder *dce80_stream_encoder_create(
597 enum engine_id eng_id,
598 struct dc_context *ctx)
599 {
600 struct dce110_stream_encoder *enc110 =
601 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
602
603 if (!enc110)
604 return NULL;
605
606 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
607 &stream_enc_regs[eng_id],
608 &se_shift, &se_mask);
609 return &enc110->base;
610 }
611
612 #define SRII(reg_name, block, id)\
613 .reg_name[id] = mm ## block ## id ## _ ## reg_name
614
615 static const struct dce_hwseq_registers hwseq_reg = {
616 HWSEQ_DCE8_REG_LIST()
617 };
618
619 static const struct dce_hwseq_shift hwseq_shift = {
620 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
621 };
622
623 static const struct dce_hwseq_mask hwseq_mask = {
624 HWSEQ_DCE8_MASK_SH_LIST(_MASK)
625 };
626
dce80_hwseq_create(struct dc_context * ctx)627 static struct dce_hwseq *dce80_hwseq_create(
628 struct dc_context *ctx)
629 {
630 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
631
632 if (hws) {
633 hws->ctx = ctx;
634 hws->regs = &hwseq_reg;
635 hws->shifts = &hwseq_shift;
636 hws->masks = &hwseq_mask;
637 }
638 return hws;
639 }
640
641 static const struct resource_create_funcs res_create_funcs = {
642 .read_dce_straps = read_dce_straps,
643 .create_audio = create_audio,
644 .create_stream_encoder = dce80_stream_encoder_create,
645 .create_hwseq = dce80_hwseq_create,
646 };
647
648 #define mi_inst_regs(id) { \
649 MI_DCE8_REG_LIST(id), \
650 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
651 }
652 static const struct dce_mem_input_registers mi_regs[] = {
653 mi_inst_regs(0),
654 mi_inst_regs(1),
655 mi_inst_regs(2),
656 mi_inst_regs(3),
657 mi_inst_regs(4),
658 mi_inst_regs(5),
659 };
660
661 static const struct dce_mem_input_shift mi_shifts = {
662 MI_DCE8_MASK_SH_LIST(__SHIFT),
663 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
664 };
665
666 static const struct dce_mem_input_mask mi_masks = {
667 MI_DCE8_MASK_SH_LIST(_MASK),
668 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
669 };
670
dce80_mem_input_create(struct dc_context * ctx,uint32_t inst)671 static struct mem_input *dce80_mem_input_create(
672 struct dc_context *ctx,
673 uint32_t inst)
674 {
675 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
676 GFP_KERNEL);
677
678 if (!dce_mi) {
679 BREAK_TO_DEBUGGER();
680 return NULL;
681 }
682
683 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
684 dce_mi->wa.single_head_rdreq_dmif_limit = 2;
685 return &dce_mi->base;
686 }
687
dce80_transform_destroy(struct transform ** xfm)688 static void dce80_transform_destroy(struct transform **xfm)
689 {
690 kfree(TO_DCE_TRANSFORM(*xfm));
691 *xfm = NULL;
692 }
693
dce80_transform_create(struct dc_context * ctx,uint32_t inst)694 static struct transform *dce80_transform_create(
695 struct dc_context *ctx,
696 uint32_t inst)
697 {
698 struct dce_transform *transform =
699 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
700
701 if (!transform)
702 return NULL;
703
704 dce_transform_construct(transform, ctx, inst,
705 &xfm_regs[inst], &xfm_shift, &xfm_mask);
706 transform->prescaler_on = false;
707 return &transform->base;
708 }
709
710 static const struct encoder_feature_support link_enc_feature = {
711 .max_hdmi_deep_color = COLOR_DEPTH_121212,
712 .max_hdmi_pixel_clock = 297000,
713 .flags.bits.IS_HBR2_CAPABLE = true,
714 .flags.bits.IS_TPS3_CAPABLE = true
715 };
716
dce80_link_encoder_create(const struct encoder_init_data * enc_init_data)717 static struct link_encoder *dce80_link_encoder_create(
718 const struct encoder_init_data *enc_init_data)
719 {
720 struct dce110_link_encoder *enc110 =
721 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
722 int link_regs_id;
723
724 if (!enc110)
725 return NULL;
726
727 link_regs_id =
728 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
729
730 dce110_link_encoder_construct(enc110,
731 enc_init_data,
732 &link_enc_feature,
733 &link_enc_regs[link_regs_id],
734 &link_enc_aux_regs[enc_init_data->channel - 1],
735 &link_enc_hpd_regs[enc_init_data->hpd_source]);
736 return &enc110->base;
737 }
738
dce80_panel_cntl_create(const struct panel_cntl_init_data * init_data)739 static struct panel_cntl *dce80_panel_cntl_create(const struct panel_cntl_init_data *init_data)
740 {
741 struct dce_panel_cntl *panel_cntl =
742 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
743
744 if (!panel_cntl)
745 return NULL;
746
747 dce_panel_cntl_construct(panel_cntl,
748 init_data,
749 &panel_cntl_regs[init_data->inst],
750 &panel_cntl_shift,
751 &panel_cntl_mask);
752
753 return &panel_cntl->base;
754 }
755
dce80_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)756 static struct clock_source *dce80_clock_source_create(
757 struct dc_context *ctx,
758 struct dc_bios *bios,
759 enum clock_source_id id,
760 const struct dce110_clk_src_regs *regs,
761 bool dp_clk_src)
762 {
763 struct dce110_clk_src *clk_src =
764 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
765
766 if (!clk_src)
767 return NULL;
768
769 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
770 regs, &cs_shift, &cs_mask)) {
771 clk_src->base.dp_clk_src = dp_clk_src;
772 return &clk_src->base;
773 }
774
775 kfree(clk_src);
776 BREAK_TO_DEBUGGER();
777 return NULL;
778 }
779
dce80_clock_source_destroy(struct clock_source ** clk_src)780 static void dce80_clock_source_destroy(struct clock_source **clk_src)
781 {
782 kfree(TO_DCE110_CLK_SRC(*clk_src));
783 *clk_src = NULL;
784 }
785
dce80_ipp_create(struct dc_context * ctx,uint32_t inst)786 static struct input_pixel_processor *dce80_ipp_create(
787 struct dc_context *ctx, uint32_t inst)
788 {
789 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
790
791 if (!ipp) {
792 BREAK_TO_DEBUGGER();
793 return NULL;
794 }
795
796 dce_ipp_construct(ipp, ctx, inst,
797 &ipp_regs[inst], &ipp_shift, &ipp_mask);
798 return &ipp->base;
799 }
800
dce80_resource_destruct(struct dce110_resource_pool * pool)801 static void dce80_resource_destruct(struct dce110_resource_pool *pool)
802 {
803 unsigned int i;
804
805 for (i = 0; i < pool->base.pipe_count; i++) {
806 if (pool->base.opps[i] != NULL)
807 dce110_opp_destroy(&pool->base.opps[i]);
808
809 if (pool->base.transforms[i] != NULL)
810 dce80_transform_destroy(&pool->base.transforms[i]);
811
812 if (pool->base.ipps[i] != NULL)
813 dce_ipp_destroy(&pool->base.ipps[i]);
814
815 if (pool->base.mis[i] != NULL) {
816 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
817 pool->base.mis[i] = NULL;
818 }
819
820 if (pool->base.timing_generators[i] != NULL) {
821 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
822 pool->base.timing_generators[i] = NULL;
823 }
824 }
825
826 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
827 if (pool->base.engines[i] != NULL)
828 dce110_engine_destroy(&pool->base.engines[i]);
829 if (pool->base.hw_i2cs[i] != NULL) {
830 kfree(pool->base.hw_i2cs[i]);
831 pool->base.hw_i2cs[i] = NULL;
832 }
833 if (pool->base.sw_i2cs[i] != NULL) {
834 kfree(pool->base.sw_i2cs[i]);
835 pool->base.sw_i2cs[i] = NULL;
836 }
837 }
838
839 for (i = 0; i < pool->base.stream_enc_count; i++) {
840 if (pool->base.stream_enc[i] != NULL)
841 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
842 }
843
844 for (i = 0; i < pool->base.clk_src_count; i++) {
845 if (pool->base.clock_sources[i] != NULL) {
846 dce80_clock_source_destroy(&pool->base.clock_sources[i]);
847 }
848 }
849
850 if (pool->base.abm != NULL)
851 dce_abm_destroy(&pool->base.abm);
852
853 if (pool->base.dmcu != NULL)
854 dce_dmcu_destroy(&pool->base.dmcu);
855
856 if (pool->base.dp_clock_source != NULL)
857 dce80_clock_source_destroy(&pool->base.dp_clock_source);
858
859 for (i = 0; i < pool->base.audio_count; i++) {
860 if (pool->base.audios[i] != NULL) {
861 dce_aud_destroy(&pool->base.audios[i]);
862 }
863 }
864
865 if (pool->base.irqs != NULL) {
866 dal_irq_service_destroy(&pool->base.irqs);
867 }
868 }
869
dce80_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)870 static bool dce80_validate_bandwidth(
871 struct dc *dc,
872 struct dc_state *context,
873 bool fast_validate)
874 {
875 int i;
876 bool at_least_one_pipe = false;
877
878 for (i = 0; i < dc->res_pool->pipe_count; i++) {
879 if (context->res_ctx.pipe_ctx[i].stream)
880 at_least_one_pipe = true;
881 }
882
883 if (at_least_one_pipe) {
884 /* TODO implement when needed but for now hardcode max value*/
885 context->bw_ctx.bw.dce.dispclk_khz = 681000;
886 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
887 } else {
888 context->bw_ctx.bw.dce.dispclk_khz = 0;
889 context->bw_ctx.bw.dce.yclk_khz = 0;
890 }
891
892 return true;
893 }
894
dce80_validate_surface_sets(struct dc_state * context)895 static bool dce80_validate_surface_sets(
896 struct dc_state *context)
897 {
898 int i;
899
900 for (i = 0; i < context->stream_count; i++) {
901 if (context->stream_status[i].plane_count == 0)
902 continue;
903
904 if (context->stream_status[i].plane_count > 1)
905 return false;
906
907 if (context->stream_status[i].plane_states[0]->format
908 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
909 return false;
910 }
911
912 return true;
913 }
914
dce80_validate_global(struct dc * dc,struct dc_state * context)915 static enum dc_status dce80_validate_global(
916 struct dc *dc,
917 struct dc_state *context)
918 {
919 if (!dce80_validate_surface_sets(context))
920 return DC_FAIL_SURFACE_VALIDATE;
921
922 return DC_OK;
923 }
924
dce80_destroy_resource_pool(struct resource_pool ** pool)925 static void dce80_destroy_resource_pool(struct resource_pool **pool)
926 {
927 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
928
929 dce80_resource_destruct(dce110_pool);
930 kfree(dce110_pool);
931 *pool = NULL;
932 }
933
934 static const struct resource_funcs dce80_res_pool_funcs = {
935 .destroy = dce80_destroy_resource_pool,
936 .link_enc_create = dce80_link_encoder_create,
937 .panel_cntl_create = dce80_panel_cntl_create,
938 .validate_bandwidth = dce80_validate_bandwidth,
939 .validate_plane = dce100_validate_plane,
940 .add_stream_to_ctx = dce100_add_stream_to_ctx,
941 .validate_global = dce80_validate_global,
942 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
943 };
944
dce80_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)945 static bool dce80_construct(
946 uint8_t num_virtual_links,
947 struct dc *dc,
948 struct dce110_resource_pool *pool)
949 {
950 unsigned int i;
951 struct dc_context *ctx = dc->ctx;
952 struct dc_bios *bp;
953
954 ctx->dc_bios->regs = &bios_regs;
955
956 pool->base.res_cap = &res_cap;
957 pool->base.funcs = &dce80_res_pool_funcs;
958
959
960 /*************************************************
961 * Resource + asic cap harcoding *
962 *************************************************/
963 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
964 pool->base.pipe_count = res_cap.num_timing_generator;
965 pool->base.timing_generator_count = res_cap.num_timing_generator;
966 dc->caps.max_downscale_ratio = 200;
967 dc->caps.i2c_speed_in_khz = 40;
968 dc->caps.i2c_speed_in_khz_hdcp = 40;
969 dc->caps.max_cursor_size = 128;
970 dc->caps.min_horizontal_blanking_period = 80;
971 dc->caps.dual_link_dvi = true;
972 dc->caps.extended_aux_timeout_support = false;
973
974 /*************************************************
975 * Create resources *
976 *************************************************/
977
978 bp = ctx->dc_bios;
979
980 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
981 pool->base.dp_clock_source =
982 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
983
984 pool->base.clock_sources[0] =
985 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
986 pool->base.clock_sources[1] =
987 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
988 pool->base.clock_sources[2] =
989 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
990 pool->base.clk_src_count = 3;
991
992 } else {
993 pool->base.dp_clock_source =
994 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
995
996 pool->base.clock_sources[0] =
997 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
998 pool->base.clock_sources[1] =
999 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1000 pool->base.clk_src_count = 2;
1001 }
1002
1003 if (pool->base.dp_clock_source == NULL) {
1004 dm_error("DC: failed to create dp clock source!\n");
1005 BREAK_TO_DEBUGGER();
1006 goto res_create_fail;
1007 }
1008
1009 for (i = 0; i < pool->base.clk_src_count; i++) {
1010 if (pool->base.clock_sources[i] == NULL) {
1011 dm_error("DC: failed to create clock sources!\n");
1012 BREAK_TO_DEBUGGER();
1013 goto res_create_fail;
1014 }
1015 }
1016
1017 pool->base.dmcu = dce_dmcu_create(ctx,
1018 &dmcu_regs,
1019 &dmcu_shift,
1020 &dmcu_mask);
1021 if (pool->base.dmcu == NULL) {
1022 dm_error("DC: failed to create dmcu!\n");
1023 BREAK_TO_DEBUGGER();
1024 goto res_create_fail;
1025 }
1026
1027 pool->base.abm = dce_abm_create(ctx,
1028 &abm_regs,
1029 &abm_shift,
1030 &abm_mask);
1031 if (pool->base.abm == NULL) {
1032 dm_error("DC: failed to create abm!\n");
1033 BREAK_TO_DEBUGGER();
1034 goto res_create_fail;
1035 }
1036
1037 {
1038 struct irq_service_init_data init_data;
1039 init_data.ctx = dc->ctx;
1040 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1041 if (!pool->base.irqs)
1042 goto res_create_fail;
1043 }
1044
1045 for (i = 0; i < pool->base.pipe_count; i++) {
1046 pool->base.timing_generators[i] = dce80_timing_generator_create(
1047 ctx, i, &dce80_tg_offsets[i]);
1048 if (pool->base.timing_generators[i] == NULL) {
1049 BREAK_TO_DEBUGGER();
1050 dm_error("DC: failed to create tg!\n");
1051 goto res_create_fail;
1052 }
1053
1054 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1055 if (pool->base.mis[i] == NULL) {
1056 BREAK_TO_DEBUGGER();
1057 dm_error("DC: failed to create memory input!\n");
1058 goto res_create_fail;
1059 }
1060
1061 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1062 if (pool->base.ipps[i] == NULL) {
1063 BREAK_TO_DEBUGGER();
1064 dm_error("DC: failed to create input pixel processor!\n");
1065 goto res_create_fail;
1066 }
1067
1068 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1069 if (pool->base.transforms[i] == NULL) {
1070 BREAK_TO_DEBUGGER();
1071 dm_error("DC: failed to create transform!\n");
1072 goto res_create_fail;
1073 }
1074
1075 pool->base.opps[i] = dce80_opp_create(ctx, i);
1076 if (pool->base.opps[i] == NULL) {
1077 BREAK_TO_DEBUGGER();
1078 dm_error("DC: failed to create output pixel processor!\n");
1079 goto res_create_fail;
1080 }
1081 }
1082
1083 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1084 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1085 if (pool->base.engines[i] == NULL) {
1086 BREAK_TO_DEBUGGER();
1087 dm_error(
1088 "DC:failed to create aux engine!!\n");
1089 goto res_create_fail;
1090 }
1091 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1092 if (pool->base.hw_i2cs[i] == NULL) {
1093 BREAK_TO_DEBUGGER();
1094 dm_error(
1095 "DC:failed to create i2c engine!!\n");
1096 goto res_create_fail;
1097 }
1098 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1099 if (pool->base.sw_i2cs[i] == NULL) {
1100 BREAK_TO_DEBUGGER();
1101 dm_error(
1102 "DC:failed to create sw i2c!!\n");
1103 goto res_create_fail;
1104 }
1105 }
1106
1107 dc->caps.max_planes = pool->base.pipe_count;
1108
1109 for (i = 0; i < dc->caps.max_planes; ++i)
1110 dc->caps.planes[i] = plane_cap;
1111
1112 dc->caps.disable_dp_clk_share = true;
1113
1114 if (!resource_construct(num_virtual_links, dc, &pool->base,
1115 &res_create_funcs))
1116 goto res_create_fail;
1117
1118 /* Create hardware sequencer */
1119 dce80_hw_sequencer_construct(dc);
1120
1121 return true;
1122
1123 res_create_fail:
1124 dce80_resource_destruct(pool);
1125 return false;
1126 }
1127
dce80_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1128 struct resource_pool *dce80_create_resource_pool(
1129 uint8_t num_virtual_links,
1130 struct dc *dc)
1131 {
1132 struct dce110_resource_pool *pool =
1133 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1134
1135 if (!pool)
1136 return NULL;
1137
1138 if (dce80_construct(num_virtual_links, dc, pool))
1139 return &pool->base;
1140
1141 kfree(pool);
1142 BREAK_TO_DEBUGGER();
1143 return NULL;
1144 }
1145
dce81_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1146 static bool dce81_construct(
1147 uint8_t num_virtual_links,
1148 struct dc *dc,
1149 struct dce110_resource_pool *pool)
1150 {
1151 unsigned int i;
1152 struct dc_context *ctx = dc->ctx;
1153 struct dc_bios *bp;
1154
1155 ctx->dc_bios->regs = &bios_regs;
1156
1157 pool->base.res_cap = &res_cap_81;
1158 pool->base.funcs = &dce80_res_pool_funcs;
1159
1160
1161 /*************************************************
1162 * Resource + asic cap harcoding *
1163 *************************************************/
1164 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1165 pool->base.pipe_count = res_cap_81.num_timing_generator;
1166 pool->base.timing_generator_count = res_cap_81.num_timing_generator;
1167 dc->caps.max_downscale_ratio = 200;
1168 dc->caps.i2c_speed_in_khz = 40;
1169 dc->caps.i2c_speed_in_khz_hdcp = 40;
1170 dc->caps.max_cursor_size = 128;
1171 dc->caps.min_horizontal_blanking_period = 80;
1172 dc->caps.is_apu = true;
1173
1174 /*************************************************
1175 * Create resources *
1176 *************************************************/
1177
1178 bp = ctx->dc_bios;
1179
1180 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1181 pool->base.dp_clock_source =
1182 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1183
1184 pool->base.clock_sources[0] =
1185 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1186 pool->base.clock_sources[1] =
1187 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1188 pool->base.clock_sources[2] =
1189 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1190 pool->base.clk_src_count = 3;
1191
1192 } else {
1193 pool->base.dp_clock_source =
1194 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1195
1196 pool->base.clock_sources[0] =
1197 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1198 pool->base.clock_sources[1] =
1199 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1200 pool->base.clk_src_count = 2;
1201 }
1202
1203 if (pool->base.dp_clock_source == NULL) {
1204 dm_error("DC: failed to create dp clock source!\n");
1205 BREAK_TO_DEBUGGER();
1206 goto res_create_fail;
1207 }
1208
1209 for (i = 0; i < pool->base.clk_src_count; i++) {
1210 if (pool->base.clock_sources[i] == NULL) {
1211 dm_error("DC: failed to create clock sources!\n");
1212 BREAK_TO_DEBUGGER();
1213 goto res_create_fail;
1214 }
1215 }
1216
1217 pool->base.dmcu = dce_dmcu_create(ctx,
1218 &dmcu_regs,
1219 &dmcu_shift,
1220 &dmcu_mask);
1221 if (pool->base.dmcu == NULL) {
1222 dm_error("DC: failed to create dmcu!\n");
1223 BREAK_TO_DEBUGGER();
1224 goto res_create_fail;
1225 }
1226
1227 pool->base.abm = dce_abm_create(ctx,
1228 &abm_regs,
1229 &abm_shift,
1230 &abm_mask);
1231 if (pool->base.abm == NULL) {
1232 dm_error("DC: failed to create abm!\n");
1233 BREAK_TO_DEBUGGER();
1234 goto res_create_fail;
1235 }
1236
1237 {
1238 struct irq_service_init_data init_data;
1239 init_data.ctx = dc->ctx;
1240 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1241 if (!pool->base.irqs)
1242 goto res_create_fail;
1243 }
1244
1245 for (i = 0; i < pool->base.pipe_count; i++) {
1246 pool->base.timing_generators[i] = dce80_timing_generator_create(
1247 ctx, i, &dce80_tg_offsets[i]);
1248 if (pool->base.timing_generators[i] == NULL) {
1249 BREAK_TO_DEBUGGER();
1250 dm_error("DC: failed to create tg!\n");
1251 goto res_create_fail;
1252 }
1253
1254 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1255 if (pool->base.mis[i] == NULL) {
1256 BREAK_TO_DEBUGGER();
1257 dm_error("DC: failed to create memory input!\n");
1258 goto res_create_fail;
1259 }
1260
1261 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1262 if (pool->base.ipps[i] == NULL) {
1263 BREAK_TO_DEBUGGER();
1264 dm_error("DC: failed to create input pixel processor!\n");
1265 goto res_create_fail;
1266 }
1267
1268 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1269 if (pool->base.transforms[i] == NULL) {
1270 BREAK_TO_DEBUGGER();
1271 dm_error("DC: failed to create transform!\n");
1272 goto res_create_fail;
1273 }
1274
1275 pool->base.opps[i] = dce80_opp_create(ctx, i);
1276 if (pool->base.opps[i] == NULL) {
1277 BREAK_TO_DEBUGGER();
1278 dm_error("DC: failed to create output pixel processor!\n");
1279 goto res_create_fail;
1280 }
1281 }
1282
1283 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1284 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1285 if (pool->base.engines[i] == NULL) {
1286 BREAK_TO_DEBUGGER();
1287 dm_error(
1288 "DC:failed to create aux engine!!\n");
1289 goto res_create_fail;
1290 }
1291 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1292 if (pool->base.hw_i2cs[i] == NULL) {
1293 BREAK_TO_DEBUGGER();
1294 dm_error(
1295 "DC:failed to create i2c engine!!\n");
1296 goto res_create_fail;
1297 }
1298 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1299 if (pool->base.sw_i2cs[i] == NULL) {
1300 BREAK_TO_DEBUGGER();
1301 dm_error(
1302 "DC:failed to create sw i2c!!\n");
1303 goto res_create_fail;
1304 }
1305 }
1306
1307 dc->caps.max_planes = pool->base.pipe_count;
1308
1309 for (i = 0; i < dc->caps.max_planes; ++i)
1310 dc->caps.planes[i] = plane_cap;
1311
1312 dc->caps.disable_dp_clk_share = true;
1313
1314 if (!resource_construct(num_virtual_links, dc, &pool->base,
1315 &res_create_funcs))
1316 goto res_create_fail;
1317
1318 /* Create hardware sequencer */
1319 dce80_hw_sequencer_construct(dc);
1320
1321 return true;
1322
1323 res_create_fail:
1324 dce80_resource_destruct(pool);
1325 return false;
1326 }
1327
dce81_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1328 struct resource_pool *dce81_create_resource_pool(
1329 uint8_t num_virtual_links,
1330 struct dc *dc)
1331 {
1332 struct dce110_resource_pool *pool =
1333 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1334
1335 if (!pool)
1336 return NULL;
1337
1338 if (dce81_construct(num_virtual_links, dc, pool))
1339 return &pool->base;
1340
1341 kfree(pool);
1342 BREAK_TO_DEBUGGER();
1343 return NULL;
1344 }
1345
dce83_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1346 static bool dce83_construct(
1347 uint8_t num_virtual_links,
1348 struct dc *dc,
1349 struct dce110_resource_pool *pool)
1350 {
1351 unsigned int i;
1352 struct dc_context *ctx = dc->ctx;
1353 struct dc_bios *bp;
1354
1355 ctx->dc_bios->regs = &bios_regs;
1356
1357 pool->base.res_cap = &res_cap_83;
1358 pool->base.funcs = &dce80_res_pool_funcs;
1359
1360
1361 /*************************************************
1362 * Resource + asic cap harcoding *
1363 *************************************************/
1364 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1365 pool->base.pipe_count = res_cap_83.num_timing_generator;
1366 pool->base.timing_generator_count = res_cap_83.num_timing_generator;
1367 dc->caps.max_downscale_ratio = 200;
1368 dc->caps.i2c_speed_in_khz = 40;
1369 dc->caps.i2c_speed_in_khz_hdcp = 40;
1370 dc->caps.max_cursor_size = 128;
1371 dc->caps.min_horizontal_blanking_period = 80;
1372 dc->caps.is_apu = true;
1373
1374 /*************************************************
1375 * Create resources *
1376 *************************************************/
1377
1378 bp = ctx->dc_bios;
1379
1380 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1381 pool->base.dp_clock_source =
1382 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1383
1384 pool->base.clock_sources[0] =
1385 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
1386 pool->base.clock_sources[1] =
1387 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1388 pool->base.clk_src_count = 2;
1389
1390 } else {
1391 pool->base.dp_clock_source =
1392 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
1393
1394 pool->base.clock_sources[0] =
1395 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1396 pool->base.clk_src_count = 1;
1397 }
1398
1399 if (pool->base.dp_clock_source == NULL) {
1400 dm_error("DC: failed to create dp clock source!\n");
1401 BREAK_TO_DEBUGGER();
1402 goto res_create_fail;
1403 }
1404
1405 for (i = 0; i < pool->base.clk_src_count; i++) {
1406 if (pool->base.clock_sources[i] == NULL) {
1407 dm_error("DC: failed to create clock sources!\n");
1408 BREAK_TO_DEBUGGER();
1409 goto res_create_fail;
1410 }
1411 }
1412
1413 pool->base.dmcu = dce_dmcu_create(ctx,
1414 &dmcu_regs,
1415 &dmcu_shift,
1416 &dmcu_mask);
1417 if (pool->base.dmcu == NULL) {
1418 dm_error("DC: failed to create dmcu!\n");
1419 BREAK_TO_DEBUGGER();
1420 goto res_create_fail;
1421 }
1422
1423 pool->base.abm = dce_abm_create(ctx,
1424 &abm_regs,
1425 &abm_shift,
1426 &abm_mask);
1427 if (pool->base.abm == NULL) {
1428 dm_error("DC: failed to create abm!\n");
1429 BREAK_TO_DEBUGGER();
1430 goto res_create_fail;
1431 }
1432
1433 {
1434 struct irq_service_init_data init_data;
1435 init_data.ctx = dc->ctx;
1436 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1437 if (!pool->base.irqs)
1438 goto res_create_fail;
1439 }
1440
1441 for (i = 0; i < pool->base.pipe_count; i++) {
1442 pool->base.timing_generators[i] = dce80_timing_generator_create(
1443 ctx, i, &dce80_tg_offsets[i]);
1444 if (pool->base.timing_generators[i] == NULL) {
1445 BREAK_TO_DEBUGGER();
1446 dm_error("DC: failed to create tg!\n");
1447 goto res_create_fail;
1448 }
1449
1450 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1451 if (pool->base.mis[i] == NULL) {
1452 BREAK_TO_DEBUGGER();
1453 dm_error("DC: failed to create memory input!\n");
1454 goto res_create_fail;
1455 }
1456
1457 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1458 if (pool->base.ipps[i] == NULL) {
1459 BREAK_TO_DEBUGGER();
1460 dm_error("DC: failed to create input pixel processor!\n");
1461 goto res_create_fail;
1462 }
1463
1464 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1465 if (pool->base.transforms[i] == NULL) {
1466 BREAK_TO_DEBUGGER();
1467 dm_error("DC: failed to create transform!\n");
1468 goto res_create_fail;
1469 }
1470
1471 pool->base.opps[i] = dce80_opp_create(ctx, i);
1472 if (pool->base.opps[i] == NULL) {
1473 BREAK_TO_DEBUGGER();
1474 dm_error("DC: failed to create output pixel processor!\n");
1475 goto res_create_fail;
1476 }
1477 }
1478
1479 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1480 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
1481 if (pool->base.engines[i] == NULL) {
1482 BREAK_TO_DEBUGGER();
1483 dm_error(
1484 "DC:failed to create aux engine!!\n");
1485 goto res_create_fail;
1486 }
1487 pool->base.hw_i2cs[i] = dce80_i2c_hw_create(ctx, i);
1488 if (pool->base.hw_i2cs[i] == NULL) {
1489 BREAK_TO_DEBUGGER();
1490 dm_error(
1491 "DC:failed to create i2c engine!!\n");
1492 goto res_create_fail;
1493 }
1494 pool->base.sw_i2cs[i] = dce80_i2c_sw_create(ctx);
1495 if (pool->base.sw_i2cs[i] == NULL) {
1496 BREAK_TO_DEBUGGER();
1497 dm_error(
1498 "DC:failed to create sw i2c!!\n");
1499 goto res_create_fail;
1500 }
1501 }
1502
1503 dc->caps.max_planes = pool->base.pipe_count;
1504
1505 for (i = 0; i < dc->caps.max_planes; ++i)
1506 dc->caps.planes[i] = plane_cap;
1507
1508 dc->caps.disable_dp_clk_share = true;
1509
1510 if (!resource_construct(num_virtual_links, dc, &pool->base,
1511 &res_create_funcs))
1512 goto res_create_fail;
1513
1514 /* Create hardware sequencer */
1515 dce80_hw_sequencer_construct(dc);
1516
1517 return true;
1518
1519 res_create_fail:
1520 dce80_resource_destruct(pool);
1521 return false;
1522 }
1523
dce83_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1524 struct resource_pool *dce83_create_resource_pool(
1525 uint8_t num_virtual_links,
1526 struct dc *dc)
1527 {
1528 struct dce110_resource_pool *pool =
1529 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1530
1531 if (!pool)
1532 return NULL;
1533
1534 if (dce83_construct(num_virtual_links, dc, pool))
1535 return &pool->base;
1536
1537 BREAK_TO_DEBUGGER();
1538 return NULL;
1539 }
1540