1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 /*
29 * Pre-requisites: headers required by header of this unit
30 */
31 #include "include/gpio_types.h"
32
33 /*
34 * Header of this unit
35 */
36
37 #include "hw_translate.h"
38
39 /*
40 * Post-requisites: headers required by this unit
41 */
42
43 #if defined(CONFIG_DRM_AMD_DC_SI)
44 #include "dce60/hw_translate_dce60.h"
45 #endif
46 #include "dce80/hw_translate_dce80.h"
47 #include "dce110/hw_translate_dce110.h"
48 #include "dce120/hw_translate_dce120.h"
49 #if defined(CONFIG_DRM_AMD_DC_DCN)
50 #include "dcn10/hw_translate_dcn10.h"
51 #include "dcn20/hw_translate_dcn20.h"
52 #include "dcn21/hw_translate_dcn21.h"
53 #include "dcn30/hw_translate_dcn30.h"
54 #endif
55
56 #include "diagnostics/hw_translate_diag.h"
57
58 /*
59 * This unit
60 */
61
dal_hw_translate_init(struct hw_translate * translate,enum dce_version dce_version,enum dce_environment dce_environment)62 bool dal_hw_translate_init(
63 struct hw_translate *translate,
64 enum dce_version dce_version,
65 enum dce_environment dce_environment)
66 {
67 if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
68 dal_hw_translate_diag_fpga_init(translate);
69 return true;
70 }
71
72 switch (dce_version) {
73 #if defined(CONFIG_DRM_AMD_DC_SI)
74 case DCE_VERSION_6_0:
75 case DCE_VERSION_6_1:
76 case DCE_VERSION_6_4:
77 dal_hw_translate_dce60_init(translate);
78 return true;
79 #endif
80 case DCE_VERSION_8_0:
81 case DCE_VERSION_8_1:
82 case DCE_VERSION_8_3:
83 dal_hw_translate_dce80_init(translate);
84 return true;
85 case DCE_VERSION_10_0:
86 case DCE_VERSION_11_0:
87 case DCE_VERSION_11_2:
88 case DCE_VERSION_11_22:
89 dal_hw_translate_dce110_init(translate);
90 return true;
91 case DCE_VERSION_12_0:
92 case DCE_VERSION_12_1:
93 dal_hw_translate_dce120_init(translate);
94 return true;
95 #if defined(CONFIG_DRM_AMD_DC_DCN)
96 case DCN_VERSION_1_0:
97 case DCN_VERSION_1_01:
98 dal_hw_translate_dcn10_init(translate);
99 return true;
100 case DCN_VERSION_2_0:
101 dal_hw_translate_dcn20_init(translate);
102 return true;
103 case DCN_VERSION_2_1:
104 dal_hw_translate_dcn21_init(translate);
105 return true;
106 case DCN_VERSION_3_0:
107 case DCN_VERSION_3_01:
108 case DCN_VERSION_3_02:
109 case DCN_VERSION_3_03:
110 case DCN_VERSION_3_1:
111 dal_hw_translate_dcn30_init(translate);
112 return true;
113 #endif
114
115 default:
116 BREAK_TO_DEBUGGER();
117 return false;
118 }
119 }
120