1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_LINK_DP_H__ 27 #define __DC_LINK_DP_H__ 28 29 #define LINK_TRAINING_ATTEMPTS 4 30 #define LINK_TRAINING_RETRY_DELAY 50 /* ms */ 31 #define LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD 3200 /*us*/ 32 #define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/ 33 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50 34 #define TRAINING_AUX_RD_INTERVAL 100 //us 35 36 struct dc_link; 37 struct dc_stream_state; 38 struct dc_link_settings; 39 40 enum { 41 LINK_TRAINING_MAX_RETRY_COUNT = 5, 42 /* to avoid infinite loop where-in the receiver 43 * switches between different VS 44 */ 45 LINK_TRAINING_MAX_CR_RETRY = 100, 46 /* 47 * Some receivers fail to train on first try and are good 48 * on subsequent tries. 2 retries should be plenty. If we 49 * don't have a successful training then we don't expect to 50 * ever get one. 51 */ 52 LINK_TRAINING_MAX_VERIFY_RETRY = 2, 53 PEAK_FACTOR_X1000 = 1006, 54 }; 55 56 bool dp_verify_link_cap( 57 struct dc_link *link, 58 struct dc_link_settings *known_limit_link_setting, 59 int *fail_count); 60 61 bool dp_verify_link_cap_with_retries( 62 struct dc_link *link, 63 struct dc_link_settings *known_limit_link_setting, 64 int attempts); 65 66 bool dp_verify_mst_link_cap( 67 struct dc_link *link); 68 69 bool dp_validate_mode_timing( 70 struct dc_link *link, 71 const struct dc_crtc_timing *timing); 72 73 bool decide_edp_link_settings(struct dc_link *link, 74 struct dc_link_settings *link_setting, 75 uint32_t req_bw); 76 77 void decide_link_settings( 78 struct dc_stream_state *stream, 79 struct dc_link_settings *link_setting); 80 81 bool perform_link_training_with_retries( 82 const struct dc_link_settings *link_setting, 83 bool skip_video_pattern, 84 int attempts, 85 struct pipe_ctx *pipe_ctx, 86 enum signal_type signal, 87 bool do_fallback); 88 89 bool hpd_rx_irq_check_link_loss_status( 90 struct dc_link *link, 91 union hpd_irq_data *hpd_irq_dpcd_data); 92 93 bool is_mst_supported(struct dc_link *link); 94 95 bool detect_dp_sink_caps(struct dc_link *link); 96 97 void detect_edp_sink_caps(struct dc_link *link); 98 99 bool is_dp_active_dongle(const struct dc_link *link); 100 101 bool is_dp_branch_device(const struct dc_link *link); 102 103 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing); 104 105 void dp_enable_mst_on_sink(struct dc_link *link, bool enable); 106 107 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link); 108 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode); 109 110 bool dp_overwrite_extended_receiver_cap(struct dc_link *link); 111 112 void dpcd_set_source_specific_data(struct dc_link *link); 113 /* Write DPCD link configuration data. */ 114 enum dc_status dpcd_set_link_settings( 115 struct dc_link *link, 116 const struct link_training_settings *lt_settings); 117 /* Write DPCD drive settings. */ 118 enum dc_status dpcd_set_lane_settings( 119 struct dc_link *link, 120 const struct link_training_settings *link_training_setting, 121 uint32_t offset); 122 /* Read training status and adjustment requests from DPCD. */ 123 enum dc_status dp_get_lane_status_and_drive_settings( 124 struct dc_link *link, 125 const struct link_training_settings *link_training_setting, 126 union lane_status *ln_status, 127 union lane_align_status_updated *ln_status_updated, 128 struct link_training_settings *req_settings, 129 uint32_t offset); 130 131 void dp_wait_for_training_aux_rd_interval( 132 struct dc_link *link, 133 uint32_t wait_in_micro_secs); 134 135 bool dp_is_cr_done(enum dc_lane_count ln_count, 136 union lane_status *dpcd_lane_status); 137 138 enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count, 139 union lane_status *dpcd_lane_status); 140 141 bool dp_is_ch_eq_done(enum dc_lane_count ln_count, 142 union lane_status *dpcd_lane_status); 143 bool dp_is_symbol_locked(enum dc_lane_count ln_count, 144 union lane_status *dpcd_lane_status); 145 bool dp_is_interlane_aligned(union lane_align_status_updated align_status); 146 147 bool dp_is_max_vs_reached( 148 const struct link_training_settings *lt_settings); 149 150 void dp_update_drive_settings( 151 struct link_training_settings *dest, 152 struct link_training_settings src); 153 154 uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval); 155 156 enum dpcd_training_patterns 157 dc_dp_training_pattern_to_dpcd_training_pattern( 158 struct dc_link *link, 159 enum dc_dp_training_pattern pattern); 160 161 uint8_t dc_dp_initialize_scrambling_data_symbols( 162 struct dc_link *link, 163 enum dc_dp_training_pattern pattern); 164 165 enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready); 166 void dp_set_fec_enable(struct dc_link *link, bool enable); 167 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable); 168 bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable); 169 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable); 170 bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx); 171 bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable); 172 173 /* Initialize output parameter lt_settings. */ 174 void dp_decide_training_settings( 175 struct dc_link *link, 176 const struct dc_link_settings *link_setting, 177 struct link_training_settings *lt_settings); 178 179 /* Convert PHY repeater count read from DPCD uint8_t. */ 180 uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count); 181 182 /* Check DPCD training status registers to detect link loss. */ 183 enum link_training_result dp_check_link_loss_status( 184 struct dc_link *link, 185 const struct link_training_settings *link_training_setting); 186 187 enum dc_status dpcd_configure_lttpr_mode( 188 struct dc_link *link, 189 struct link_training_settings *lt_settings); 190 191 enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings); 192 bool dp_retrieve_lttpr_cap(struct dc_link *link); 193 #endif /* __DC_LINK_DP_H__ */ 194