1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include <linux/vga_switcheroo.h>
26
27 #include <drm/drm_drv.h>
28 #include <drm/i915_pciids.h>
29
30 #include "i915_drv.h"
31 #include "i915_pci.h"
32
33 #define PLATFORM(x) .platform = (x)
34 #define GEN(x) \
35 .graphics_ver = (x), \
36 .media_ver = (x), \
37 .display.ver = (x)
38
39 #define I845_PIPE_OFFSETS \
40 .pipe_offsets = { \
41 [TRANSCODER_A] = PIPE_A_OFFSET, \
42 }, \
43 .trans_offsets = { \
44 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
45 }
46
47 #define I9XX_PIPE_OFFSETS \
48 .pipe_offsets = { \
49 [TRANSCODER_A] = PIPE_A_OFFSET, \
50 [TRANSCODER_B] = PIPE_B_OFFSET, \
51 }, \
52 .trans_offsets = { \
53 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
54 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
55 }
56
57 #define IVB_PIPE_OFFSETS \
58 .pipe_offsets = { \
59 [TRANSCODER_A] = PIPE_A_OFFSET, \
60 [TRANSCODER_B] = PIPE_B_OFFSET, \
61 [TRANSCODER_C] = PIPE_C_OFFSET, \
62 }, \
63 .trans_offsets = { \
64 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
65 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
66 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
67 }
68
69 #define HSW_PIPE_OFFSETS \
70 .pipe_offsets = { \
71 [TRANSCODER_A] = PIPE_A_OFFSET, \
72 [TRANSCODER_B] = PIPE_B_OFFSET, \
73 [TRANSCODER_C] = PIPE_C_OFFSET, \
74 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
75 }, \
76 .trans_offsets = { \
77 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
78 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
79 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
80 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
81 }
82
83 #define CHV_PIPE_OFFSETS \
84 .pipe_offsets = { \
85 [TRANSCODER_A] = PIPE_A_OFFSET, \
86 [TRANSCODER_B] = PIPE_B_OFFSET, \
87 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
88 }, \
89 .trans_offsets = { \
90 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
91 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
92 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
93 }
94
95 #define I845_CURSOR_OFFSETS \
96 .cursor_offsets = { \
97 [PIPE_A] = CURSOR_A_OFFSET, \
98 }
99
100 #define I9XX_CURSOR_OFFSETS \
101 .cursor_offsets = { \
102 [PIPE_A] = CURSOR_A_OFFSET, \
103 [PIPE_B] = CURSOR_B_OFFSET, \
104 }
105
106 #define CHV_CURSOR_OFFSETS \
107 .cursor_offsets = { \
108 [PIPE_A] = CURSOR_A_OFFSET, \
109 [PIPE_B] = CURSOR_B_OFFSET, \
110 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
111 }
112
113 #define IVB_CURSOR_OFFSETS \
114 .cursor_offsets = { \
115 [PIPE_A] = CURSOR_A_OFFSET, \
116 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
117 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
118 }
119
120 #define TGL_CURSOR_OFFSETS \
121 .cursor_offsets = { \
122 [PIPE_A] = CURSOR_A_OFFSET, \
123 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
124 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
125 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
126 }
127
128 #define I9XX_COLORS \
129 .color = { .gamma_lut_size = 256 }
130 #define I965_COLORS \
131 .color = { .gamma_lut_size = 129, \
132 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
133 }
134 #define ILK_COLORS \
135 .color = { .gamma_lut_size = 1024 }
136 #define IVB_COLORS \
137 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
138 #define CHV_COLORS \
139 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
140 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
141 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
142 }
143 #define GLK_COLORS \
144 .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
145 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
146 DRM_COLOR_LUT_EQUAL_CHANNELS, \
147 }
148
149 /* Keep in gen based order, and chronological order within a gen */
150
151 #define GEN_DEFAULT_PAGE_SIZES \
152 .page_sizes = I915_GTT_PAGE_SIZE_4K
153
154 #define GEN_DEFAULT_REGIONS \
155 .memory_regions = REGION_SMEM | REGION_STOLEN_SMEM
156
157 #define I830_FEATURES \
158 GEN(2), \
159 .is_mobile = 1, \
160 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
161 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
162 .display.has_overlay = 1, \
163 .display.cursor_needs_physical = 1, \
164 .display.overlay_needs_physical = 1, \
165 .display.has_gmch = 1, \
166 .gpu_reset_clobbers_display = true, \
167 .hws_needs_physical = 1, \
168 .unfenced_needs_alignment = 1, \
169 .platform_engine_mask = BIT(RCS0), \
170 .has_snoop = true, \
171 .has_coherent_ggtt = false, \
172 .dma_mask_size = 32, \
173 I9XX_PIPE_OFFSETS, \
174 I9XX_CURSOR_OFFSETS, \
175 I9XX_COLORS, \
176 GEN_DEFAULT_PAGE_SIZES, \
177 GEN_DEFAULT_REGIONS
178
179 #define I845_FEATURES \
180 GEN(2), \
181 .pipe_mask = BIT(PIPE_A), \
182 .cpu_transcoder_mask = BIT(TRANSCODER_A), \
183 .display.has_overlay = 1, \
184 .display.overlay_needs_physical = 1, \
185 .display.has_gmch = 1, \
186 .gpu_reset_clobbers_display = true, \
187 .hws_needs_physical = 1, \
188 .unfenced_needs_alignment = 1, \
189 .platform_engine_mask = BIT(RCS0), \
190 .has_snoop = true, \
191 .has_coherent_ggtt = false, \
192 .dma_mask_size = 32, \
193 I845_PIPE_OFFSETS, \
194 I845_CURSOR_OFFSETS, \
195 I9XX_COLORS, \
196 GEN_DEFAULT_PAGE_SIZES, \
197 GEN_DEFAULT_REGIONS
198
199 static const struct intel_device_info i830_info = {
200 I830_FEATURES,
201 PLATFORM(INTEL_I830),
202 };
203
204 static const struct intel_device_info i845g_info = {
205 I845_FEATURES,
206 PLATFORM(INTEL_I845G),
207 };
208
209 static const struct intel_device_info i85x_info = {
210 I830_FEATURES,
211 PLATFORM(INTEL_I85X),
212 .display.has_fbc = 1,
213 };
214
215 static const struct intel_device_info i865g_info = {
216 I845_FEATURES,
217 PLATFORM(INTEL_I865G),
218 .display.has_fbc = 1,
219 };
220
221 #define GEN3_FEATURES \
222 GEN(3), \
223 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
224 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
225 .display.has_gmch = 1, \
226 .gpu_reset_clobbers_display = true, \
227 .platform_engine_mask = BIT(RCS0), \
228 .has_snoop = true, \
229 .has_coherent_ggtt = true, \
230 .dma_mask_size = 32, \
231 I9XX_PIPE_OFFSETS, \
232 I9XX_CURSOR_OFFSETS, \
233 I9XX_COLORS, \
234 GEN_DEFAULT_PAGE_SIZES, \
235 GEN_DEFAULT_REGIONS
236
237 static const struct intel_device_info i915g_info = {
238 GEN3_FEATURES,
239 PLATFORM(INTEL_I915G),
240 .has_coherent_ggtt = false,
241 .display.cursor_needs_physical = 1,
242 .display.has_overlay = 1,
243 .display.overlay_needs_physical = 1,
244 .hws_needs_physical = 1,
245 .unfenced_needs_alignment = 1,
246 };
247
248 static const struct intel_device_info i915gm_info = {
249 GEN3_FEATURES,
250 PLATFORM(INTEL_I915GM),
251 .is_mobile = 1,
252 .display.cursor_needs_physical = 1,
253 .display.has_overlay = 1,
254 .display.overlay_needs_physical = 1,
255 .display.supports_tv = 1,
256 .display.has_fbc = 1,
257 .hws_needs_physical = 1,
258 .unfenced_needs_alignment = 1,
259 };
260
261 static const struct intel_device_info i945g_info = {
262 GEN3_FEATURES,
263 PLATFORM(INTEL_I945G),
264 .display.has_hotplug = 1,
265 .display.cursor_needs_physical = 1,
266 .display.has_overlay = 1,
267 .display.overlay_needs_physical = 1,
268 .hws_needs_physical = 1,
269 .unfenced_needs_alignment = 1,
270 };
271
272 static const struct intel_device_info i945gm_info = {
273 GEN3_FEATURES,
274 PLATFORM(INTEL_I945GM),
275 .is_mobile = 1,
276 .display.has_hotplug = 1,
277 .display.cursor_needs_physical = 1,
278 .display.has_overlay = 1,
279 .display.overlay_needs_physical = 1,
280 .display.supports_tv = 1,
281 .display.has_fbc = 1,
282 .hws_needs_physical = 1,
283 .unfenced_needs_alignment = 1,
284 };
285
286 static const struct intel_device_info g33_info = {
287 GEN3_FEATURES,
288 PLATFORM(INTEL_G33),
289 .display.has_hotplug = 1,
290 .display.has_overlay = 1,
291 .dma_mask_size = 36,
292 };
293
294 static const struct intel_device_info pnv_g_info = {
295 GEN3_FEATURES,
296 PLATFORM(INTEL_PINEVIEW),
297 .display.has_hotplug = 1,
298 .display.has_overlay = 1,
299 .dma_mask_size = 36,
300 };
301
302 static const struct intel_device_info pnv_m_info = {
303 GEN3_FEATURES,
304 PLATFORM(INTEL_PINEVIEW),
305 .is_mobile = 1,
306 .display.has_hotplug = 1,
307 .display.has_overlay = 1,
308 .dma_mask_size = 36,
309 };
310
311 #define GEN4_FEATURES \
312 GEN(4), \
313 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
314 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
315 .display.has_hotplug = 1, \
316 .display.has_gmch = 1, \
317 .gpu_reset_clobbers_display = true, \
318 .platform_engine_mask = BIT(RCS0), \
319 .has_snoop = true, \
320 .has_coherent_ggtt = true, \
321 .dma_mask_size = 36, \
322 I9XX_PIPE_OFFSETS, \
323 I9XX_CURSOR_OFFSETS, \
324 I965_COLORS, \
325 GEN_DEFAULT_PAGE_SIZES, \
326 GEN_DEFAULT_REGIONS
327
328 static const struct intel_device_info i965g_info = {
329 GEN4_FEATURES,
330 PLATFORM(INTEL_I965G),
331 .display.has_overlay = 1,
332 .hws_needs_physical = 1,
333 .has_snoop = false,
334 };
335
336 static const struct intel_device_info i965gm_info = {
337 GEN4_FEATURES,
338 PLATFORM(INTEL_I965GM),
339 .is_mobile = 1,
340 .display.has_fbc = 1,
341 .display.has_overlay = 1,
342 .display.supports_tv = 1,
343 .hws_needs_physical = 1,
344 .has_snoop = false,
345 };
346
347 static const struct intel_device_info g45_info = {
348 GEN4_FEATURES,
349 PLATFORM(INTEL_G45),
350 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
351 .gpu_reset_clobbers_display = false,
352 };
353
354 static const struct intel_device_info gm45_info = {
355 GEN4_FEATURES,
356 PLATFORM(INTEL_GM45),
357 .is_mobile = 1,
358 .display.has_fbc = 1,
359 .display.supports_tv = 1,
360 .platform_engine_mask = BIT(RCS0) | BIT(VCS0),
361 .gpu_reset_clobbers_display = false,
362 };
363
364 #define GEN5_FEATURES \
365 GEN(5), \
366 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
367 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
368 .display.has_hotplug = 1, \
369 .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
370 .has_snoop = true, \
371 .has_coherent_ggtt = true, \
372 /* ilk does support rc6, but we do not implement [power] contexts */ \
373 .has_rc6 = 0, \
374 .dma_mask_size = 36, \
375 I9XX_PIPE_OFFSETS, \
376 I9XX_CURSOR_OFFSETS, \
377 ILK_COLORS, \
378 GEN_DEFAULT_PAGE_SIZES, \
379 GEN_DEFAULT_REGIONS
380
381 static const struct intel_device_info ilk_d_info = {
382 GEN5_FEATURES,
383 PLATFORM(INTEL_IRONLAKE),
384 };
385
386 static const struct intel_device_info ilk_m_info = {
387 GEN5_FEATURES,
388 PLATFORM(INTEL_IRONLAKE),
389 .is_mobile = 1,
390 .has_rps = true,
391 .display.has_fbc = 1,
392 };
393
394 #define GEN6_FEATURES \
395 GEN(6), \
396 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
397 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
398 .display.has_hotplug = 1, \
399 .display.has_fbc = 1, \
400 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
401 .has_coherent_ggtt = true, \
402 .has_llc = 1, \
403 .has_rc6 = 1, \
404 /* snb does support rc6p, but enabling it causes various issues */ \
405 .has_rc6p = 0, \
406 .has_rps = true, \
407 .dma_mask_size = 40, \
408 .ppgtt_type = INTEL_PPGTT_ALIASING, \
409 .ppgtt_size = 31, \
410 I9XX_PIPE_OFFSETS, \
411 I9XX_CURSOR_OFFSETS, \
412 ILK_COLORS, \
413 GEN_DEFAULT_PAGE_SIZES, \
414 GEN_DEFAULT_REGIONS
415
416 #define SNB_D_PLATFORM \
417 GEN6_FEATURES, \
418 PLATFORM(INTEL_SANDYBRIDGE)
419
420 static const struct intel_device_info snb_d_gt1_info = {
421 SNB_D_PLATFORM,
422 .gt = 1,
423 };
424
425 static const struct intel_device_info snb_d_gt2_info = {
426 SNB_D_PLATFORM,
427 .gt = 2,
428 };
429
430 #define SNB_M_PLATFORM \
431 GEN6_FEATURES, \
432 PLATFORM(INTEL_SANDYBRIDGE), \
433 .is_mobile = 1
434
435
436 static const struct intel_device_info snb_m_gt1_info = {
437 SNB_M_PLATFORM,
438 .gt = 1,
439 };
440
441 static const struct intel_device_info snb_m_gt2_info = {
442 SNB_M_PLATFORM,
443 .gt = 2,
444 };
445
446 #define GEN7_FEATURES \
447 GEN(7), \
448 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
449 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
450 .display.has_hotplug = 1, \
451 .display.has_fbc = 1, \
452 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
453 .has_coherent_ggtt = true, \
454 .has_llc = 1, \
455 .has_rc6 = 1, \
456 .has_rc6p = 1, \
457 .has_reset_engine = true, \
458 .has_rps = true, \
459 .dma_mask_size = 40, \
460 .ppgtt_type = INTEL_PPGTT_ALIASING, \
461 .ppgtt_size = 31, \
462 IVB_PIPE_OFFSETS, \
463 IVB_CURSOR_OFFSETS, \
464 IVB_COLORS, \
465 GEN_DEFAULT_PAGE_SIZES, \
466 GEN_DEFAULT_REGIONS
467
468 #define IVB_D_PLATFORM \
469 GEN7_FEATURES, \
470 PLATFORM(INTEL_IVYBRIDGE), \
471 .has_l3_dpf = 1
472
473 static const struct intel_device_info ivb_d_gt1_info = {
474 IVB_D_PLATFORM,
475 .gt = 1,
476 };
477
478 static const struct intel_device_info ivb_d_gt2_info = {
479 IVB_D_PLATFORM,
480 .gt = 2,
481 };
482
483 #define IVB_M_PLATFORM \
484 GEN7_FEATURES, \
485 PLATFORM(INTEL_IVYBRIDGE), \
486 .is_mobile = 1, \
487 .has_l3_dpf = 1
488
489 static const struct intel_device_info ivb_m_gt1_info = {
490 IVB_M_PLATFORM,
491 .gt = 1,
492 };
493
494 static const struct intel_device_info ivb_m_gt2_info = {
495 IVB_M_PLATFORM,
496 .gt = 2,
497 };
498
499 static const struct intel_device_info ivb_q_info = {
500 GEN7_FEATURES,
501 PLATFORM(INTEL_IVYBRIDGE),
502 .gt = 2,
503 .pipe_mask = 0, /* legal, last one wins */
504 .cpu_transcoder_mask = 0,
505 .has_l3_dpf = 1,
506 };
507
508 static const struct intel_device_info vlv_info = {
509 PLATFORM(INTEL_VALLEYVIEW),
510 GEN(7),
511 .is_lp = 1,
512 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
513 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
514 .has_runtime_pm = 1,
515 .has_rc6 = 1,
516 .has_reset_engine = true,
517 .has_rps = true,
518 .display.has_gmch = 1,
519 .display.has_hotplug = 1,
520 .dma_mask_size = 40,
521 .ppgtt_type = INTEL_PPGTT_ALIASING,
522 .ppgtt_size = 31,
523 .has_snoop = true,
524 .has_coherent_ggtt = false,
525 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
526 .display_mmio_offset = VLV_DISPLAY_BASE,
527 I9XX_PIPE_OFFSETS,
528 I9XX_CURSOR_OFFSETS,
529 I965_COLORS,
530 GEN_DEFAULT_PAGE_SIZES,
531 GEN_DEFAULT_REGIONS,
532 };
533
534 #define G75_FEATURES \
535 GEN7_FEATURES, \
536 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
537 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
538 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
539 .display.has_ddi = 1, \
540 .display.has_fpga_dbg = 1, \
541 .display.has_psr = 1, \
542 .display.has_psr_hw_tracking = 1, \
543 .display.has_dp_mst = 1, \
544 .has_rc6p = 0 /* RC6p removed-by HSW */, \
545 HSW_PIPE_OFFSETS, \
546 .has_runtime_pm = 1
547
548 #define HSW_PLATFORM \
549 G75_FEATURES, \
550 PLATFORM(INTEL_HASWELL), \
551 .has_l3_dpf = 1
552
553 static const struct intel_device_info hsw_gt1_info = {
554 HSW_PLATFORM,
555 .gt = 1,
556 };
557
558 static const struct intel_device_info hsw_gt2_info = {
559 HSW_PLATFORM,
560 .gt = 2,
561 };
562
563 static const struct intel_device_info hsw_gt3_info = {
564 HSW_PLATFORM,
565 .gt = 3,
566 };
567
568 #define GEN8_FEATURES \
569 G75_FEATURES, \
570 GEN(8), \
571 .has_logical_ring_contexts = 1, \
572 .dma_mask_size = 39, \
573 .ppgtt_type = INTEL_PPGTT_FULL, \
574 .ppgtt_size = 48, \
575 .has_64bit_reloc = 1
576
577 #define BDW_PLATFORM \
578 GEN8_FEATURES, \
579 PLATFORM(INTEL_BROADWELL)
580
581 static const struct intel_device_info bdw_gt1_info = {
582 BDW_PLATFORM,
583 .gt = 1,
584 };
585
586 static const struct intel_device_info bdw_gt2_info = {
587 BDW_PLATFORM,
588 .gt = 2,
589 };
590
591 static const struct intel_device_info bdw_rsvd_info = {
592 BDW_PLATFORM,
593 .gt = 3,
594 /* According to the device ID those devices are GT3, they were
595 * previously treated as not GT3, keep it like that.
596 */
597 };
598
599 static const struct intel_device_info bdw_gt3_info = {
600 BDW_PLATFORM,
601 .gt = 3,
602 .platform_engine_mask =
603 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
604 };
605
606 static const struct intel_device_info chv_info = {
607 PLATFORM(INTEL_CHERRYVIEW),
608 GEN(8),
609 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
610 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
611 .display.has_hotplug = 1,
612 .is_lp = 1,
613 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
614 .has_64bit_reloc = 1,
615 .has_runtime_pm = 1,
616 .has_rc6 = 1,
617 .has_rps = true,
618 .has_logical_ring_contexts = 1,
619 .display.has_gmch = 1,
620 .dma_mask_size = 39,
621 .ppgtt_type = INTEL_PPGTT_FULL,
622 .ppgtt_size = 32,
623 .has_reset_engine = 1,
624 .has_snoop = true,
625 .has_coherent_ggtt = false,
626 .display_mmio_offset = VLV_DISPLAY_BASE,
627 CHV_PIPE_OFFSETS,
628 CHV_CURSOR_OFFSETS,
629 CHV_COLORS,
630 GEN_DEFAULT_PAGE_SIZES,
631 GEN_DEFAULT_REGIONS,
632 };
633
634 #define GEN9_DEFAULT_PAGE_SIZES \
635 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
636 I915_GTT_PAGE_SIZE_64K
637
638 #define GEN9_FEATURES \
639 GEN8_FEATURES, \
640 GEN(9), \
641 GEN9_DEFAULT_PAGE_SIZES, \
642 .display.has_dmc = 1, \
643 .has_gt_uc = 1, \
644 .display.has_hdcp = 1, \
645 .display.has_ipc = 1, \
646 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
647 .dbuf.slice_mask = BIT(DBUF_S1)
648
649 #define SKL_PLATFORM \
650 GEN9_FEATURES, \
651 PLATFORM(INTEL_SKYLAKE)
652
653 static const struct intel_device_info skl_gt1_info = {
654 SKL_PLATFORM,
655 .gt = 1,
656 };
657
658 static const struct intel_device_info skl_gt2_info = {
659 SKL_PLATFORM,
660 .gt = 2,
661 };
662
663 #define SKL_GT3_PLUS_PLATFORM \
664 SKL_PLATFORM, \
665 .platform_engine_mask = \
666 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
667
668
669 static const struct intel_device_info skl_gt3_info = {
670 SKL_GT3_PLUS_PLATFORM,
671 .gt = 3,
672 };
673
674 static const struct intel_device_info skl_gt4_info = {
675 SKL_GT3_PLUS_PLATFORM,
676 .gt = 4,
677 };
678
679 #define GEN9_LP_FEATURES \
680 GEN(9), \
681 .is_lp = 1, \
682 .dbuf.slice_mask = BIT(DBUF_S1), \
683 .display.has_hotplug = 1, \
684 .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
685 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
686 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
687 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
688 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
689 .has_64bit_reloc = 1, \
690 .display.has_ddi = 1, \
691 .display.has_fpga_dbg = 1, \
692 .display.has_fbc = 1, \
693 .display.has_hdcp = 1, \
694 .display.has_psr = 1, \
695 .display.has_psr_hw_tracking = 1, \
696 .has_runtime_pm = 1, \
697 .display.has_dmc = 1, \
698 .has_rc6 = 1, \
699 .has_rps = true, \
700 .display.has_dp_mst = 1, \
701 .has_logical_ring_contexts = 1, \
702 .has_gt_uc = 1, \
703 .dma_mask_size = 39, \
704 .ppgtt_type = INTEL_PPGTT_FULL, \
705 .ppgtt_size = 48, \
706 .has_reset_engine = 1, \
707 .has_snoop = true, \
708 .has_coherent_ggtt = false, \
709 .display.has_ipc = 1, \
710 HSW_PIPE_OFFSETS, \
711 IVB_CURSOR_OFFSETS, \
712 IVB_COLORS, \
713 GEN9_DEFAULT_PAGE_SIZES, \
714 GEN_DEFAULT_REGIONS
715
716 static const struct intel_device_info bxt_info = {
717 GEN9_LP_FEATURES,
718 PLATFORM(INTEL_BROXTON),
719 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
720 };
721
722 static const struct intel_device_info glk_info = {
723 GEN9_LP_FEATURES,
724 PLATFORM(INTEL_GEMINILAKE),
725 .display.ver = 10,
726 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
727 GLK_COLORS,
728 };
729
730 #define KBL_PLATFORM \
731 GEN9_FEATURES, \
732 PLATFORM(INTEL_KABYLAKE)
733
734 static const struct intel_device_info kbl_gt1_info = {
735 KBL_PLATFORM,
736 .gt = 1,
737 };
738
739 static const struct intel_device_info kbl_gt2_info = {
740 KBL_PLATFORM,
741 .gt = 2,
742 };
743
744 static const struct intel_device_info kbl_gt3_info = {
745 KBL_PLATFORM,
746 .gt = 3,
747 .platform_engine_mask =
748 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
749 };
750
751 #define CFL_PLATFORM \
752 GEN9_FEATURES, \
753 PLATFORM(INTEL_COFFEELAKE)
754
755 static const struct intel_device_info cfl_gt1_info = {
756 CFL_PLATFORM,
757 .gt = 1,
758 };
759
760 static const struct intel_device_info cfl_gt2_info = {
761 CFL_PLATFORM,
762 .gt = 2,
763 };
764
765 static const struct intel_device_info cfl_gt3_info = {
766 CFL_PLATFORM,
767 .gt = 3,
768 .platform_engine_mask =
769 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
770 };
771
772 #define CML_PLATFORM \
773 GEN9_FEATURES, \
774 PLATFORM(INTEL_COMETLAKE)
775
776 static const struct intel_device_info cml_gt1_info = {
777 CML_PLATFORM,
778 .gt = 1,
779 };
780
781 static const struct intel_device_info cml_gt2_info = {
782 CML_PLATFORM,
783 .gt = 2,
784 };
785
786 #define GEN11_DEFAULT_PAGE_SIZES \
787 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
788 I915_GTT_PAGE_SIZE_64K | \
789 I915_GTT_PAGE_SIZE_2M
790
791 #define GEN11_FEATURES \
792 GEN9_FEATURES, \
793 GEN11_DEFAULT_PAGE_SIZES, \
794 .abox_mask = BIT(0), \
795 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
796 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
797 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
798 .pipe_offsets = { \
799 [TRANSCODER_A] = PIPE_A_OFFSET, \
800 [TRANSCODER_B] = PIPE_B_OFFSET, \
801 [TRANSCODER_C] = PIPE_C_OFFSET, \
802 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
803 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
804 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
805 }, \
806 .trans_offsets = { \
807 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
808 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
809 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
810 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
811 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
812 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
813 }, \
814 GEN(11), \
815 .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }, \
816 .dbuf.size = 2048, \
817 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
818 .display.has_dsc = 1, \
819 .has_coherent_ggtt = false, \
820 .has_logical_ring_elsq = 1
821
822 static const struct intel_device_info icl_info = {
823 GEN11_FEATURES,
824 PLATFORM(INTEL_ICELAKE),
825 .platform_engine_mask =
826 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
827 };
828
829 static const struct intel_device_info ehl_info = {
830 GEN11_FEATURES,
831 PLATFORM(INTEL_ELKHARTLAKE),
832 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
833 .ppgtt_size = 36,
834 };
835
836 static const struct intel_device_info jsl_info = {
837 GEN11_FEATURES,
838 PLATFORM(INTEL_JASPERLAKE),
839 .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
840 .ppgtt_size = 36,
841 };
842
843 #define GEN12_FEATURES \
844 GEN11_FEATURES, \
845 GEN(12), \
846 .abox_mask = GENMASK(2, 1), \
847 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
848 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
849 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
850 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
851 .pipe_offsets = { \
852 [TRANSCODER_A] = PIPE_A_OFFSET, \
853 [TRANSCODER_B] = PIPE_B_OFFSET, \
854 [TRANSCODER_C] = PIPE_C_OFFSET, \
855 [TRANSCODER_D] = PIPE_D_OFFSET, \
856 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
857 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
858 }, \
859 .trans_offsets = { \
860 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
861 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
862 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
863 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
864 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
865 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
866 }, \
867 TGL_CURSOR_OFFSETS, \
868 .has_global_mocs = 1, \
869 .display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */
870
871 static const struct intel_device_info tgl_info = {
872 GEN12_FEATURES,
873 PLATFORM(INTEL_TIGERLAKE),
874 .display.has_modular_fia = 1,
875 .platform_engine_mask =
876 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
877 };
878
879 static const struct intel_device_info rkl_info = {
880 GEN12_FEATURES,
881 PLATFORM(INTEL_ROCKETLAKE),
882 .abox_mask = BIT(0),
883 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
884 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
885 BIT(TRANSCODER_C),
886 .display.has_hti = 1,
887 .display.has_psr_hw_tracking = 0,
888 .platform_engine_mask =
889 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
890 };
891
892 #define DGFX_FEATURES \
893 .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \
894 .has_llc = 0, \
895 .has_snoop = 1, \
896 .is_dgfx = 1
897
898 static const struct intel_device_info dg1_info __maybe_unused = {
899 GEN12_FEATURES,
900 DGFX_FEATURES,
901 .graphics_rel = 10,
902 PLATFORM(INTEL_DG1),
903 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
904 .require_force_probe = 1,
905 .platform_engine_mask =
906 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
907 BIT(VCS0) | BIT(VCS2),
908 /* Wa_16011227922 */
909 .ppgtt_size = 47,
910 };
911
912 static const struct intel_device_info adl_s_info = {
913 GEN12_FEATURES,
914 PLATFORM(INTEL_ALDERLAKE_S),
915 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
916 .require_force_probe = 1,
917 .display.has_hti = 1,
918 .display.has_psr_hw_tracking = 0,
919 .platform_engine_mask =
920 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
921 .dma_mask_size = 39,
922 };
923
924 #define XE_LPD_CURSOR_OFFSETS \
925 .cursor_offsets = { \
926 [PIPE_A] = CURSOR_A_OFFSET, \
927 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
928 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
929 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
930 }
931
932 #define XE_LPD_FEATURES \
933 .abox_mask = GENMASK(1, 0), \
934 .color = { .degamma_lut_size = 0, .gamma_lut_size = 0 }, \
935 .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
936 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
937 .dbuf.size = 4096, \
938 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
939 BIT(DBUF_S4), \
940 .display.has_ddi = 1, \
941 .display.has_dmc = 1, \
942 .display.has_dp_mst = 1, \
943 .display.has_dsb = 1, \
944 .display.has_dsc = 1, \
945 .display.has_fbc = 1, \
946 .display.has_fpga_dbg = 1, \
947 .display.has_hdcp = 1, \
948 .display.has_hotplug = 1, \
949 .display.has_ipc = 1, \
950 .display.has_psr = 1, \
951 .display.ver = 13, \
952 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
953 .pipe_offsets = { \
954 [TRANSCODER_A] = PIPE_A_OFFSET, \
955 [TRANSCODER_B] = PIPE_B_OFFSET, \
956 [TRANSCODER_C] = PIPE_C_OFFSET, \
957 [TRANSCODER_D] = PIPE_D_OFFSET, \
958 }, \
959 .trans_offsets = { \
960 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
961 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
962 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
963 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
964 }, \
965 XE_LPD_CURSOR_OFFSETS
966
967 static const struct intel_device_info adl_p_info = {
968 GEN12_FEATURES,
969 XE_LPD_FEATURES,
970 PLATFORM(INTEL_ALDERLAKE_P),
971 .require_force_probe = 1,
972 .display.has_cdclk_crawl = 1,
973 .display.has_modular_fia = 1,
974 .display.has_psr_hw_tracking = 0,
975 .platform_engine_mask =
976 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
977 .ppgtt_size = 48,
978 .dma_mask_size = 39,
979 };
980
981 #undef GEN
982
983 #define XE_HP_PAGE_SIZES \
984 .page_sizes = I915_GTT_PAGE_SIZE_4K | \
985 I915_GTT_PAGE_SIZE_64K | \
986 I915_GTT_PAGE_SIZE_2M
987
988 #define XE_HP_FEATURES \
989 .graphics_ver = 12, \
990 .graphics_rel = 50, \
991 XE_HP_PAGE_SIZES, \
992 .dma_mask_size = 46, \
993 .has_64bit_reloc = 1, \
994 .has_global_mocs = 1, \
995 .has_gt_uc = 1, \
996 .has_llc = 1, \
997 .has_logical_ring_contexts = 1, \
998 .has_logical_ring_elsq = 1, \
999 .has_mslices = 1, \
1000 .has_rc6 = 1, \
1001 .has_reset_engine = 1, \
1002 .has_rps = 1, \
1003 .has_runtime_pm = 1, \
1004 .ppgtt_size = 48, \
1005 .ppgtt_type = INTEL_PPGTT_FULL
1006
1007 #define XE_HPM_FEATURES \
1008 .media_ver = 12, \
1009 .media_rel = 50
1010
1011 __maybe_unused
1012 static const struct intel_device_info xehpsdv_info = {
1013 XE_HP_FEATURES,
1014 XE_HPM_FEATURES,
1015 DGFX_FEATURES,
1016 PLATFORM(INTEL_XEHPSDV),
1017 .display = { },
1018 .pipe_mask = 0,
1019 .platform_engine_mask =
1020 BIT(RCS0) | BIT(BCS0) |
1021 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
1022 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
1023 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7),
1024 .require_force_probe = 1,
1025 };
1026
1027 __maybe_unused
1028 static const struct intel_device_info dg2_info = {
1029 XE_HP_FEATURES,
1030 XE_HPM_FEATURES,
1031 XE_LPD_FEATURES,
1032 DGFX_FEATURES,
1033 .graphics_rel = 55,
1034 .media_rel = 55,
1035 PLATFORM(INTEL_DG2),
1036 .platform_engine_mask =
1037 BIT(RCS0) | BIT(BCS0) |
1038 BIT(VECS0) | BIT(VECS1) |
1039 BIT(VCS0) | BIT(VCS2),
1040 .require_force_probe = 1,
1041 };
1042
1043 #undef PLATFORM
1044
1045 /*
1046 * Make sure any device matches here are from most specific to most
1047 * general. For example, since the Quanta match is based on the subsystem
1048 * and subvendor IDs, we need it to come before the more general IVB
1049 * PCI ID matches, otherwise we'll use the wrong info struct above.
1050 */
1051 static const struct pci_device_id pciidlist[] = {
1052 INTEL_I830_IDS(&i830_info),
1053 INTEL_I845G_IDS(&i845g_info),
1054 INTEL_I85X_IDS(&i85x_info),
1055 INTEL_I865G_IDS(&i865g_info),
1056 INTEL_I915G_IDS(&i915g_info),
1057 INTEL_I915GM_IDS(&i915gm_info),
1058 INTEL_I945G_IDS(&i945g_info),
1059 INTEL_I945GM_IDS(&i945gm_info),
1060 INTEL_I965G_IDS(&i965g_info),
1061 INTEL_G33_IDS(&g33_info),
1062 INTEL_I965GM_IDS(&i965gm_info),
1063 INTEL_GM45_IDS(&gm45_info),
1064 INTEL_G45_IDS(&g45_info),
1065 INTEL_PINEVIEW_G_IDS(&pnv_g_info),
1066 INTEL_PINEVIEW_M_IDS(&pnv_m_info),
1067 INTEL_IRONLAKE_D_IDS(&ilk_d_info),
1068 INTEL_IRONLAKE_M_IDS(&ilk_m_info),
1069 INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info),
1070 INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info),
1071 INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info),
1072 INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info),
1073 INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */
1074 INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info),
1075 INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info),
1076 INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info),
1077 INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info),
1078 INTEL_HSW_GT1_IDS(&hsw_gt1_info),
1079 INTEL_HSW_GT2_IDS(&hsw_gt2_info),
1080 INTEL_HSW_GT3_IDS(&hsw_gt3_info),
1081 INTEL_VLV_IDS(&vlv_info),
1082 INTEL_BDW_GT1_IDS(&bdw_gt1_info),
1083 INTEL_BDW_GT2_IDS(&bdw_gt2_info),
1084 INTEL_BDW_GT3_IDS(&bdw_gt3_info),
1085 INTEL_BDW_RSVD_IDS(&bdw_rsvd_info),
1086 INTEL_CHV_IDS(&chv_info),
1087 INTEL_SKL_GT1_IDS(&skl_gt1_info),
1088 INTEL_SKL_GT2_IDS(&skl_gt2_info),
1089 INTEL_SKL_GT3_IDS(&skl_gt3_info),
1090 INTEL_SKL_GT4_IDS(&skl_gt4_info),
1091 INTEL_BXT_IDS(&bxt_info),
1092 INTEL_GLK_IDS(&glk_info),
1093 INTEL_KBL_GT1_IDS(&kbl_gt1_info),
1094 INTEL_KBL_GT2_IDS(&kbl_gt2_info),
1095 INTEL_KBL_GT3_IDS(&kbl_gt3_info),
1096 INTEL_KBL_GT4_IDS(&kbl_gt3_info),
1097 INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info),
1098 INTEL_CFL_S_GT1_IDS(&cfl_gt1_info),
1099 INTEL_CFL_S_GT2_IDS(&cfl_gt2_info),
1100 INTEL_CFL_H_GT1_IDS(&cfl_gt1_info),
1101 INTEL_CFL_H_GT2_IDS(&cfl_gt2_info),
1102 INTEL_CFL_U_GT2_IDS(&cfl_gt2_info),
1103 INTEL_CFL_U_GT3_IDS(&cfl_gt3_info),
1104 INTEL_WHL_U_GT1_IDS(&cfl_gt1_info),
1105 INTEL_WHL_U_GT2_IDS(&cfl_gt2_info),
1106 INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info),
1107 INTEL_WHL_U_GT3_IDS(&cfl_gt3_info),
1108 INTEL_CML_GT1_IDS(&cml_gt1_info),
1109 INTEL_CML_GT2_IDS(&cml_gt2_info),
1110 INTEL_CML_U_GT1_IDS(&cml_gt1_info),
1111 INTEL_CML_U_GT2_IDS(&cml_gt2_info),
1112 INTEL_ICL_11_IDS(&icl_info),
1113 INTEL_EHL_IDS(&ehl_info),
1114 INTEL_JSL_IDS(&jsl_info),
1115 INTEL_TGL_12_IDS(&tgl_info),
1116 INTEL_RKL_IDS(&rkl_info),
1117 INTEL_ADLS_IDS(&adl_s_info),
1118 INTEL_ADLP_IDS(&adl_p_info),
1119 {0, 0, 0}
1120 };
1121 MODULE_DEVICE_TABLE(pci, pciidlist);
1122
i915_pci_remove(struct pci_dev * pdev)1123 static void i915_pci_remove(struct pci_dev *pdev)
1124 {
1125 struct drm_i915_private *i915;
1126
1127 i915 = pci_get_drvdata(pdev);
1128 if (!i915) /* driver load aborted, nothing to cleanup */
1129 return;
1130
1131 i915_driver_remove(i915);
1132 pci_set_drvdata(pdev, NULL);
1133 }
1134
1135 /* is device_id present in comma separated list of ids */
force_probe(u16 device_id,const char * devices)1136 static bool force_probe(u16 device_id, const char *devices)
1137 {
1138 char *s, *p, *tok;
1139 bool ret;
1140
1141 if (!devices || !*devices)
1142 return false;
1143
1144 /* match everything */
1145 if (strcmp(devices, "*") == 0)
1146 return true;
1147
1148 s = kstrdup(devices, GFP_KERNEL);
1149 if (!s)
1150 return false;
1151
1152 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
1153 u16 val;
1154
1155 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
1156 ret = true;
1157 break;
1158 }
1159 }
1160
1161 kfree(s);
1162
1163 return ret;
1164 }
1165
i915_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1166 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1167 {
1168 struct intel_device_info *intel_info =
1169 (struct intel_device_info *) ent->driver_data;
1170 int err;
1171
1172 if (intel_info->require_force_probe &&
1173 !force_probe(pdev->device, i915_modparams.force_probe)) {
1174 dev_info(&pdev->dev,
1175 "Your graphics device %04x is not properly supported by the driver in this\n"
1176 "kernel version. To force driver probe anyway, use i915.force_probe=%04x\n"
1177 "module parameter or CONFIG_DRM_I915_FORCE_PROBE=%04x configuration option,\n"
1178 "or (recommended) check for kernel updates.\n",
1179 pdev->device, pdev->device, pdev->device);
1180 return -ENODEV;
1181 }
1182
1183 /* Only bind to function 0 of the device. Early generations
1184 * used function 1 as a placeholder for multi-head. This causes
1185 * us confusion instead, especially on the systems where both
1186 * functions have the same PCI-ID!
1187 */
1188 if (PCI_FUNC(pdev->devfn))
1189 return -ENODEV;
1190
1191 /*
1192 * apple-gmux is needed on dual GPU MacBook Pro
1193 * to probe the panel if we're the inactive GPU.
1194 */
1195 if (vga_switcheroo_client_probe_defer(pdev))
1196 return -EPROBE_DEFER;
1197
1198 err = i915_driver_probe(pdev, ent);
1199 if (err)
1200 return err;
1201
1202 if (i915_inject_probe_failure(pci_get_drvdata(pdev))) {
1203 i915_pci_remove(pdev);
1204 return -ENODEV;
1205 }
1206
1207 err = i915_live_selftests(pdev);
1208 if (err) {
1209 i915_pci_remove(pdev);
1210 return err > 0 ? -ENOTTY : err;
1211 }
1212
1213 err = i915_perf_selftests(pdev);
1214 if (err) {
1215 i915_pci_remove(pdev);
1216 return err > 0 ? -ENOTTY : err;
1217 }
1218
1219 return 0;
1220 }
1221
i915_pci_shutdown(struct pci_dev * pdev)1222 static void i915_pci_shutdown(struct pci_dev *pdev)
1223 {
1224 struct drm_i915_private *i915 = pci_get_drvdata(pdev);
1225
1226 i915_driver_shutdown(i915);
1227 }
1228
1229 static struct pci_driver i915_pci_driver = {
1230 .name = DRIVER_NAME,
1231 .id_table = pciidlist,
1232 .probe = i915_pci_probe,
1233 .remove = i915_pci_remove,
1234 .shutdown = i915_pci_shutdown,
1235 .driver.pm = &i915_pm_ops,
1236 };
1237
i915_register_pci_driver(void)1238 int i915_register_pci_driver(void)
1239 {
1240 return pci_register_driver(&i915_pci_driver);
1241 }
1242
i915_unregister_pci_driver(void)1243 void i915_unregister_pci_driver(void)
1244 {
1245 pci_unregister_driver(&i915_pci_driver);
1246 }
1247