1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef _DPU_HW_TOP_H 6 #define _DPU_HW_TOP_H 7 8 #include "dpu_hw_catalog.h" 9 #include "dpu_hw_mdss.h" 10 #include "dpu_hw_util.h" 11 #include "dpu_hw_blk.h" 12 13 struct dpu_hw_mdp; 14 15 /** 16 * struct traffic_shaper_cfg: traffic shaper configuration 17 * @en : enable/disable traffic shaper 18 * @rd_client : true if read client; false if write client 19 * @client_id : client identifier 20 * @bpc_denom : denominator of byte per clk 21 * @bpc_numer : numerator of byte per clk 22 */ 23 struct traffic_shaper_cfg { 24 bool en; 25 bool rd_client; 26 u32 client_id; 27 u32 bpc_denom; 28 u64 bpc_numer; 29 }; 30 31 /** 32 * struct split_pipe_cfg - pipe configuration for dual display panels 33 * @en : Enable/disable dual pipe configuration 34 * @mode : Panel interface mode 35 * @intf : Interface id for main control path 36 * @split_flush_en: Allows both the paths to be flushed when master path is 37 * flushed 38 */ 39 struct split_pipe_cfg { 40 bool en; 41 enum dpu_intf_mode mode; 42 enum dpu_intf intf; 43 bool split_flush_en; 44 }; 45 46 /** 47 * struct dpu_danger_safe_status: danger and safe status signals 48 * @mdp: top level status 49 * @sspp: source pipe status 50 */ 51 struct dpu_danger_safe_status { 52 u8 mdp; 53 u8 sspp[SSPP_MAX]; 54 }; 55 56 /** 57 * struct dpu_vsync_source_cfg - configure vsync source and configure the 58 * watchdog timers if required. 59 * @pp_count: number of ping pongs active 60 * @frame_rate: Display frame rate 61 * @ppnumber: ping pong index array 62 * @vsync_source: vsync source selection 63 */ 64 struct dpu_vsync_source_cfg { 65 u32 pp_count; 66 u32 frame_rate; 67 u32 ppnumber[PINGPONG_MAX]; 68 u32 vsync_source; 69 }; 70 71 /** 72 * struct dpu_hw_mdp_ops - interface to the MDP TOP Hw driver functions 73 * Assumption is these functions will be called after clocks are enabled. 74 * @setup_split_pipe : Programs the pipe control registers 75 * @setup_pp_split : Programs the pp split control registers 76 * @setup_traffic_shaper : programs traffic shaper control 77 */ 78 struct dpu_hw_mdp_ops { 79 /** setup_split_pipe() : Registers are not double buffered, thisk 80 * function should be called before timing control enable 81 * @mdp : mdp top context driver 82 * @cfg : upper and lower part of pipe configuration 83 */ 84 void (*setup_split_pipe)(struct dpu_hw_mdp *mdp, 85 struct split_pipe_cfg *p); 86 87 /** 88 * setup_traffic_shaper() : Setup traffic shaper control 89 * @mdp : mdp top context driver 90 * @cfg : traffic shaper configuration 91 */ 92 void (*setup_traffic_shaper)(struct dpu_hw_mdp *mdp, 93 struct traffic_shaper_cfg *cfg); 94 95 /** 96 * setup_clk_force_ctrl - set clock force control 97 * @mdp: mdp top context driver 98 * @clk_ctrl: clock to be controlled 99 * @enable: force on enable 100 * @return: if the clock is forced-on by this function 101 */ 102 bool (*setup_clk_force_ctrl)(struct dpu_hw_mdp *mdp, 103 enum dpu_clk_ctrl_type clk_ctrl, bool enable); 104 105 /** 106 * get_danger_status - get danger status 107 * @mdp: mdp top context driver 108 * @status: Pointer to danger safe status 109 */ 110 void (*get_danger_status)(struct dpu_hw_mdp *mdp, 111 struct dpu_danger_safe_status *status); 112 113 /** 114 * setup_vsync_source - setup vsync source configuration details 115 * @mdp: mdp top context driver 116 * @cfg: vsync source selection configuration 117 */ 118 void (*setup_vsync_source)(struct dpu_hw_mdp *mdp, 119 struct dpu_vsync_source_cfg *cfg); 120 121 /** 122 * get_safe_status - get safe status 123 * @mdp: mdp top context driver 124 * @status: Pointer to danger safe status 125 */ 126 void (*get_safe_status)(struct dpu_hw_mdp *mdp, 127 struct dpu_danger_safe_status *status); 128 129 /** 130 * intf_audio_select - select the external interface for audio 131 * @mdp: mdp top context driver 132 */ 133 void (*intf_audio_select)(struct dpu_hw_mdp *mdp); 134 }; 135 136 struct dpu_hw_mdp { 137 struct dpu_hw_blk base; 138 struct dpu_hw_blk_reg_map hw; 139 140 /* top */ 141 enum dpu_mdp idx; 142 const struct dpu_mdp_cfg *caps; 143 144 /* ops */ 145 struct dpu_hw_mdp_ops ops; 146 }; 147 148 /** 149 * dpu_hw_mdptop_init - initializes the top driver for the passed idx 150 * @idx: Interface index for which driver object is required 151 * @addr: Mapped register io address of MDP 152 * @m: Pointer to mdss catalog data 153 */ 154 struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, 155 void __iomem *addr, 156 const struct dpu_mdss_cfg *m); 157 158 void dpu_hw_mdp_destroy(struct dpu_hw_mdp *mdp); 159 160 #endif /*_DPU_HW_TOP_H */ 161