1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7 #include <linux/adreno-smmu-priv.h>
8 #include <linux/io-pgtable.h>
9 #include "msm_drv.h"
10 #include "msm_mmu.h"
11
12 struct msm_iommu {
13 struct msm_mmu base;
14 struct iommu_domain *domain;
15 atomic_t pagetables;
16 };
17
18 #define to_msm_iommu(x) container_of(x, struct msm_iommu, base)
19
20 struct msm_iommu_pagetable {
21 struct msm_mmu base;
22 struct msm_mmu *parent;
23 struct io_pgtable_ops *pgtbl_ops;
24 phys_addr_t ttbr;
25 u32 asid;
26 };
to_pagetable(struct msm_mmu * mmu)27 static struct msm_iommu_pagetable *to_pagetable(struct msm_mmu *mmu)
28 {
29 return container_of(mmu, struct msm_iommu_pagetable, base);
30 }
31
msm_iommu_pagetable_unmap(struct msm_mmu * mmu,u64 iova,size_t size)32 static int msm_iommu_pagetable_unmap(struct msm_mmu *mmu, u64 iova,
33 size_t size)
34 {
35 struct msm_iommu_pagetable *pagetable = to_pagetable(mmu);
36 struct io_pgtable_ops *ops = pagetable->pgtbl_ops;
37 size_t unmapped = 0;
38
39 /* Unmap the block one page at a time */
40 while (size) {
41 unmapped += ops->unmap(ops, iova, 4096, NULL);
42 iova += 4096;
43 size -= 4096;
44 }
45
46 iommu_flush_iotlb_all(to_msm_iommu(pagetable->parent)->domain);
47
48 return (unmapped == size) ? 0 : -EINVAL;
49 }
50
msm_iommu_pagetable_map(struct msm_mmu * mmu,u64 iova,struct sg_table * sgt,size_t len,int prot)51 static int msm_iommu_pagetable_map(struct msm_mmu *mmu, u64 iova,
52 struct sg_table *sgt, size_t len, int prot)
53 {
54 struct msm_iommu_pagetable *pagetable = to_pagetable(mmu);
55 struct io_pgtable_ops *ops = pagetable->pgtbl_ops;
56 struct scatterlist *sg;
57 size_t mapped = 0;
58 u64 addr = iova;
59 unsigned int i;
60
61 for_each_sgtable_sg(sgt, sg, i) {
62 size_t size = sg->length;
63 phys_addr_t phys = sg_phys(sg);
64
65 /* Map the block one page at a time */
66 while (size) {
67 if (ops->map(ops, addr, phys, 4096, prot, GFP_KERNEL)) {
68 msm_iommu_pagetable_unmap(mmu, iova, mapped);
69 return -EINVAL;
70 }
71
72 phys += 4096;
73 addr += 4096;
74 size -= 4096;
75 mapped += 4096;
76 }
77 }
78
79 return 0;
80 }
81
msm_iommu_pagetable_destroy(struct msm_mmu * mmu)82 static void msm_iommu_pagetable_destroy(struct msm_mmu *mmu)
83 {
84 struct msm_iommu_pagetable *pagetable = to_pagetable(mmu);
85 struct msm_iommu *iommu = to_msm_iommu(pagetable->parent);
86 struct adreno_smmu_priv *adreno_smmu =
87 dev_get_drvdata(pagetable->parent->dev);
88
89 /*
90 * If this is the last attached pagetable for the parent,
91 * disable TTBR0 in the arm-smmu driver
92 */
93 if (atomic_dec_return(&iommu->pagetables) == 0)
94 adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, NULL);
95
96 free_io_pgtable_ops(pagetable->pgtbl_ops);
97 kfree(pagetable);
98 }
99
msm_iommu_pagetable_params(struct msm_mmu * mmu,phys_addr_t * ttbr,int * asid)100 int msm_iommu_pagetable_params(struct msm_mmu *mmu,
101 phys_addr_t *ttbr, int *asid)
102 {
103 struct msm_iommu_pagetable *pagetable;
104
105 if (mmu->type != MSM_MMU_IOMMU_PAGETABLE)
106 return -EINVAL;
107
108 pagetable = to_pagetable(mmu);
109
110 if (ttbr)
111 *ttbr = pagetable->ttbr;
112
113 if (asid)
114 *asid = pagetable->asid;
115
116 return 0;
117 }
118
119 static const struct msm_mmu_funcs pagetable_funcs = {
120 .map = msm_iommu_pagetable_map,
121 .unmap = msm_iommu_pagetable_unmap,
122 .destroy = msm_iommu_pagetable_destroy,
123 };
124
msm_iommu_tlb_flush_all(void * cookie)125 static void msm_iommu_tlb_flush_all(void *cookie)
126 {
127 }
128
msm_iommu_tlb_flush_walk(unsigned long iova,size_t size,size_t granule,void * cookie)129 static void msm_iommu_tlb_flush_walk(unsigned long iova, size_t size,
130 size_t granule, void *cookie)
131 {
132 }
133
msm_iommu_tlb_add_page(struct iommu_iotlb_gather * gather,unsigned long iova,size_t granule,void * cookie)134 static void msm_iommu_tlb_add_page(struct iommu_iotlb_gather *gather,
135 unsigned long iova, size_t granule, void *cookie)
136 {
137 }
138
139 static const struct iommu_flush_ops null_tlb_ops = {
140 .tlb_flush_all = msm_iommu_tlb_flush_all,
141 .tlb_flush_walk = msm_iommu_tlb_flush_walk,
142 .tlb_add_page = msm_iommu_tlb_add_page,
143 };
144
145 static int msm_fault_handler(struct iommu_domain *domain, struct device *dev,
146 unsigned long iova, int flags, void *arg);
147
msm_iommu_pagetable_create(struct msm_mmu * parent)148 struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent)
149 {
150 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(parent->dev);
151 struct msm_iommu *iommu = to_msm_iommu(parent);
152 struct msm_iommu_pagetable *pagetable;
153 const struct io_pgtable_cfg *ttbr1_cfg = NULL;
154 struct io_pgtable_cfg ttbr0_cfg;
155 int ret;
156
157 /* Get the pagetable configuration from the domain */
158 if (adreno_smmu->cookie)
159 ttbr1_cfg = adreno_smmu->get_ttbr1_cfg(adreno_smmu->cookie);
160
161 /*
162 * If you hit this WARN_ONCE() you are probably missing an entry in
163 * qcom_smmu_impl_of_match[] in arm-smmu-qcom.c
164 */
165 if (WARN_ONCE(!ttbr1_cfg, "No per-process page tables"))
166 return ERR_PTR(-ENODEV);
167
168 /*
169 * Defer setting the fault handler until we have a valid adreno_smmu
170 * to avoid accidentially installing a GPU specific fault handler for
171 * the display's iommu
172 */
173 iommu_set_fault_handler(iommu->domain, msm_fault_handler, iommu);
174
175 pagetable = kzalloc(sizeof(*pagetable), GFP_KERNEL);
176 if (!pagetable)
177 return ERR_PTR(-ENOMEM);
178
179 msm_mmu_init(&pagetable->base, parent->dev, &pagetable_funcs,
180 MSM_MMU_IOMMU_PAGETABLE);
181
182 /* Clone the TTBR1 cfg as starting point for TTBR0 cfg: */
183 ttbr0_cfg = *ttbr1_cfg;
184
185 /* The incoming cfg will have the TTBR1 quirk enabled */
186 ttbr0_cfg.quirks &= ~IO_PGTABLE_QUIRK_ARM_TTBR1;
187 ttbr0_cfg.tlb = &null_tlb_ops;
188
189 pagetable->pgtbl_ops = alloc_io_pgtable_ops(ARM_64_LPAE_S1,
190 &ttbr0_cfg, iommu->domain);
191
192 if (!pagetable->pgtbl_ops) {
193 kfree(pagetable);
194 return ERR_PTR(-ENOMEM);
195 }
196
197 /*
198 * If this is the first pagetable that we've allocated, send it back to
199 * the arm-smmu driver as a trigger to set up TTBR0
200 */
201 if (atomic_inc_return(&iommu->pagetables) == 1) {
202 /* Enable stall on iommu fault: */
203 adreno_smmu->set_stall(adreno_smmu->cookie, true);
204
205 ret = adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, &ttbr0_cfg);
206 if (ret) {
207 free_io_pgtable_ops(pagetable->pgtbl_ops);
208 kfree(pagetable);
209 return ERR_PTR(ret);
210 }
211 }
212
213 /* Needed later for TLB flush */
214 pagetable->parent = parent;
215 pagetable->ttbr = ttbr0_cfg.arm_lpae_s1_cfg.ttbr;
216
217 /*
218 * TODO we would like each set of page tables to have a unique ASID
219 * to optimize TLB invalidation. But iommu_flush_iotlb_all() will
220 * end up flushing the ASID used for TTBR1 pagetables, which is not
221 * what we want. So for now just use the same ASID as TTBR1.
222 */
223 pagetable->asid = 0;
224
225 return &pagetable->base;
226 }
227
msm_fault_handler(struct iommu_domain * domain,struct device * dev,unsigned long iova,int flags,void * arg)228 static int msm_fault_handler(struct iommu_domain *domain, struct device *dev,
229 unsigned long iova, int flags, void *arg)
230 {
231 struct msm_iommu *iommu = arg;
232 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(iommu->base.dev);
233 struct adreno_smmu_fault_info info, *ptr = NULL;
234
235 if (adreno_smmu->get_fault_info) {
236 adreno_smmu->get_fault_info(adreno_smmu->cookie, &info);
237 ptr = &info;
238 }
239
240 if (iommu->base.handler)
241 return iommu->base.handler(iommu->base.arg, iova, flags, ptr);
242
243 pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags);
244 return 0;
245 }
246
msm_iommu_resume_translation(struct msm_mmu * mmu)247 static void msm_iommu_resume_translation(struct msm_mmu *mmu)
248 {
249 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(mmu->dev);
250
251 adreno_smmu->resume_translation(adreno_smmu->cookie, true);
252 }
253
msm_iommu_detach(struct msm_mmu * mmu)254 static void msm_iommu_detach(struct msm_mmu *mmu)
255 {
256 struct msm_iommu *iommu = to_msm_iommu(mmu);
257
258 iommu_detach_device(iommu->domain, mmu->dev);
259 }
260
msm_iommu_map(struct msm_mmu * mmu,uint64_t iova,struct sg_table * sgt,size_t len,int prot)261 static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova,
262 struct sg_table *sgt, size_t len, int prot)
263 {
264 struct msm_iommu *iommu = to_msm_iommu(mmu);
265 size_t ret;
266
267 /* The arm-smmu driver expects the addresses to be sign extended */
268 if (iova & BIT_ULL(48))
269 iova |= GENMASK_ULL(63, 49);
270
271 ret = iommu_map_sgtable(iommu->domain, iova, sgt, prot);
272 WARN_ON(!ret);
273
274 return (ret == len) ? 0 : -EINVAL;
275 }
276
msm_iommu_unmap(struct msm_mmu * mmu,uint64_t iova,size_t len)277 static int msm_iommu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len)
278 {
279 struct msm_iommu *iommu = to_msm_iommu(mmu);
280
281 if (iova & BIT_ULL(48))
282 iova |= GENMASK_ULL(63, 49);
283
284 iommu_unmap(iommu->domain, iova, len);
285
286 return 0;
287 }
288
msm_iommu_destroy(struct msm_mmu * mmu)289 static void msm_iommu_destroy(struct msm_mmu *mmu)
290 {
291 struct msm_iommu *iommu = to_msm_iommu(mmu);
292 iommu_domain_free(iommu->domain);
293 kfree(iommu);
294 }
295
296 static const struct msm_mmu_funcs funcs = {
297 .detach = msm_iommu_detach,
298 .map = msm_iommu_map,
299 .unmap = msm_iommu_unmap,
300 .destroy = msm_iommu_destroy,
301 .resume_translation = msm_iommu_resume_translation,
302 };
303
msm_iommu_new(struct device * dev,struct iommu_domain * domain)304 struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain)
305 {
306 struct msm_iommu *iommu;
307 int ret;
308
309 if (!domain)
310 return ERR_PTR(-ENODEV);
311
312 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
313 if (!iommu)
314 return ERR_PTR(-ENOMEM);
315
316 iommu->domain = domain;
317 msm_mmu_init(&iommu->base, dev, &funcs, MSM_MMU_IOMMU);
318
319 atomic_set(&iommu->pagetables, 0);
320
321 ret = iommu_attach_device(iommu->domain, dev);
322 if (ret) {
323 kfree(iommu);
324 return ERR_PTR(ret);
325 }
326
327 return &iommu->base;
328 }
329