1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/component.h>
9 #include <linux/delay.h>
10 #include <linux/iopoll.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/overflow.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/reset.h>
19
20 #include <drm/drm.h>
21 #include <drm/drm_atomic.h>
22 #include <drm/drm_atomic_uapi.h>
23 #include <drm/drm_crtc.h>
24 #include <drm/drm_flip_work.h>
25 #include <drm/drm_fourcc.h>
26 #include <drm/drm_gem_atomic_helper.h>
27 #include <drm/drm_gem_framebuffer_helper.h>
28 #include <drm/drm_plane_helper.h>
29 #include <drm/drm_probe_helper.h>
30 #include <drm/drm_self_refresh_helper.h>
31 #include <drm/drm_vblank.h>
32
33 #ifdef CONFIG_DRM_ANALOGIX_DP
34 #include <drm/bridge/analogix_dp.h>
35 #endif
36
37 #include "rockchip_drm_drv.h"
38 #include "rockchip_drm_gem.h"
39 #include "rockchip_drm_fb.h"
40 #include "rockchip_drm_vop.h"
41 #include "rockchip_rgb.h"
42
43 #define VOP_WIN_SET(vop, win, name, v) \
44 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
45 #define VOP_SCL_SET(vop, win, name, v) \
46 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
47 #define VOP_SCL_SET_EXT(vop, win, name, v) \
48 vop_reg_set(vop, &win->phy->scl->ext->name, \
49 win->base, ~0, v, #name)
50
51 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \
52 do { \
53 if (win_yuv2yuv && win_yuv2yuv->name.mask) \
54 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
55 } while (0)
56
57 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \
58 do { \
59 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \
60 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
61 } while (0)
62
63 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
64 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
65
66 #define VOP_REG_SET(vop, group, name, v) \
67 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
68
69 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
70 do { \
71 int i, reg = 0, mask = 0; \
72 for (i = 0; i < vop->data->intr->nintrs; i++) { \
73 if (vop->data->intr->intrs[i] & type) { \
74 reg |= (v) << i; \
75 mask |= 1 << i; \
76 } \
77 } \
78 VOP_INTR_SET_MASK(vop, name, mask, reg); \
79 } while (0)
80 #define VOP_INTR_GET_TYPE(vop, name, type) \
81 vop_get_intr_type(vop, &vop->data->intr->name, type)
82
83 #define VOP_WIN_GET(vop, win, name) \
84 vop_read_reg(vop, win->base, &win->phy->name)
85
86 #define VOP_WIN_HAS_REG(win, name) \
87 (!!(win->phy->name.mask))
88
89 #define VOP_WIN_GET_YRGBADDR(vop, win) \
90 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
91
92 #define VOP_WIN_TO_INDEX(vop_win) \
93 ((vop_win) - (vop_win)->vop->win)
94
95 #define VOP_AFBC_SET(vop, name, v) \
96 do { \
97 if ((vop)->data->afbc) \
98 vop_reg_set((vop), &(vop)->data->afbc->name, \
99 0, ~0, v, #name); \
100 } while (0)
101
102 #define to_vop(x) container_of(x, struct vop, crtc)
103 #define to_vop_win(x) container_of(x, struct vop_win, base)
104
105 #define AFBC_FMT_RGB565 0x0
106 #define AFBC_FMT_U8U8U8U8 0x5
107 #define AFBC_FMT_U8U8U8 0x4
108
109 #define AFBC_TILE_16x16 BIT(4)
110
111 /*
112 * The coefficients of the following matrix are all fixed points.
113 * The format is S2.10 for the 3x3 part of the matrix, and S9.12 for the offsets.
114 * They are all represented in two's complement.
115 */
116 static const uint32_t bt601_yuv2rgb[] = {
117 0x4A8, 0x0, 0x662,
118 0x4A8, 0x1E6F, 0x1CBF,
119 0x4A8, 0x812, 0x0,
120 0x321168, 0x0877CF, 0x2EB127
121 };
122
123 enum vop_pending {
124 VOP_PENDING_FB_UNREF,
125 };
126
127 struct vop_win {
128 struct drm_plane base;
129 const struct vop_win_data *data;
130 const struct vop_win_yuv2yuv_data *yuv2yuv_data;
131 struct vop *vop;
132 };
133
134 struct rockchip_rgb;
135 struct vop {
136 struct drm_crtc crtc;
137 struct device *dev;
138 struct drm_device *drm_dev;
139 bool is_enabled;
140
141 struct completion dsp_hold_completion;
142 unsigned int win_enabled;
143
144 /* protected by dev->event_lock */
145 struct drm_pending_vblank_event *event;
146
147 struct drm_flip_work fb_unref_work;
148 unsigned long pending;
149
150 struct completion line_flag_completion;
151
152 const struct vop_data *data;
153
154 uint32_t *regsbak;
155 void __iomem *regs;
156 void __iomem *lut_regs;
157
158 /* physical map length of vop register */
159 uint32_t len;
160
161 /* one time only one process allowed to config the register */
162 spinlock_t reg_lock;
163 /* lock vop irq reg */
164 spinlock_t irq_lock;
165 /* protects crtc enable/disable */
166 struct mutex vop_lock;
167
168 unsigned int irq;
169
170 /* vop AHP clk */
171 struct clk *hclk;
172 /* vop dclk */
173 struct clk *dclk;
174 /* vop share memory frequency */
175 struct clk *aclk;
176
177 /* vop dclk reset */
178 struct reset_control *dclk_rst;
179
180 /* optional internal rgb encoder */
181 struct rockchip_rgb *rgb;
182
183 struct vop_win win[];
184 };
185
vop_writel(struct vop * vop,uint32_t offset,uint32_t v)186 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
187 {
188 writel(v, vop->regs + offset);
189 vop->regsbak[offset >> 2] = v;
190 }
191
vop_readl(struct vop * vop,uint32_t offset)192 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
193 {
194 return readl(vop->regs + offset);
195 }
196
vop_read_reg(struct vop * vop,uint32_t base,const struct vop_reg * reg)197 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
198 const struct vop_reg *reg)
199 {
200 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
201 }
202
vop_reg_set(struct vop * vop,const struct vop_reg * reg,uint32_t _offset,uint32_t _mask,uint32_t v,const char * reg_name)203 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
204 uint32_t _offset, uint32_t _mask, uint32_t v,
205 const char *reg_name)
206 {
207 int offset, mask, shift;
208
209 if (!reg || !reg->mask) {
210 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
211 return;
212 }
213
214 offset = reg->offset + _offset;
215 mask = reg->mask & _mask;
216 shift = reg->shift;
217
218 if (reg->write_mask) {
219 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
220 } else {
221 uint32_t cached_val = vop->regsbak[offset >> 2];
222
223 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
224 vop->regsbak[offset >> 2] = v;
225 }
226
227 if (reg->relaxed)
228 writel_relaxed(v, vop->regs + offset);
229 else
230 writel(v, vop->regs + offset);
231 }
232
vop_get_intr_type(struct vop * vop,const struct vop_reg * reg,int type)233 static inline uint32_t vop_get_intr_type(struct vop *vop,
234 const struct vop_reg *reg, int type)
235 {
236 uint32_t i, ret = 0;
237 uint32_t regs = vop_read_reg(vop, 0, reg);
238
239 for (i = 0; i < vop->data->intr->nintrs; i++) {
240 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
241 ret |= vop->data->intr->intrs[i];
242 }
243
244 return ret;
245 }
246
vop_cfg_done(struct vop * vop)247 static inline void vop_cfg_done(struct vop *vop)
248 {
249 VOP_REG_SET(vop, common, cfg_done, 1);
250 }
251
has_rb_swapped(uint32_t version,uint32_t format)252 static bool has_rb_swapped(uint32_t version, uint32_t format)
253 {
254 switch (format) {
255 case DRM_FORMAT_XBGR8888:
256 case DRM_FORMAT_ABGR8888:
257 case DRM_FORMAT_BGR565:
258 return true;
259 /*
260 * full framework (IP version 3.x) only need rb swapped for RGB888 and
261 * little framework (IP version 2.x) only need rb swapped for BGR888,
262 * check for 3.x to also only rb swap BGR888 for unknown vop version
263 */
264 case DRM_FORMAT_RGB888:
265 return VOP_MAJOR(version) == 3;
266 case DRM_FORMAT_BGR888:
267 return VOP_MAJOR(version) != 3;
268 default:
269 return false;
270 }
271 }
272
vop_convert_format(uint32_t format)273 static enum vop_data_format vop_convert_format(uint32_t format)
274 {
275 switch (format) {
276 case DRM_FORMAT_XRGB8888:
277 case DRM_FORMAT_ARGB8888:
278 case DRM_FORMAT_XBGR8888:
279 case DRM_FORMAT_ABGR8888:
280 return VOP_FMT_ARGB8888;
281 case DRM_FORMAT_RGB888:
282 case DRM_FORMAT_BGR888:
283 return VOP_FMT_RGB888;
284 case DRM_FORMAT_RGB565:
285 case DRM_FORMAT_BGR565:
286 return VOP_FMT_RGB565;
287 case DRM_FORMAT_NV12:
288 return VOP_FMT_YUV420SP;
289 case DRM_FORMAT_NV16:
290 return VOP_FMT_YUV422SP;
291 case DRM_FORMAT_NV24:
292 return VOP_FMT_YUV444SP;
293 default:
294 DRM_ERROR("unsupported format[%08x]\n", format);
295 return -EINVAL;
296 }
297 }
298
vop_convert_afbc_format(uint32_t format)299 static int vop_convert_afbc_format(uint32_t format)
300 {
301 switch (format) {
302 case DRM_FORMAT_XRGB8888:
303 case DRM_FORMAT_ARGB8888:
304 case DRM_FORMAT_XBGR8888:
305 case DRM_FORMAT_ABGR8888:
306 return AFBC_FMT_U8U8U8U8;
307 case DRM_FORMAT_RGB888:
308 case DRM_FORMAT_BGR888:
309 return AFBC_FMT_U8U8U8;
310 case DRM_FORMAT_RGB565:
311 case DRM_FORMAT_BGR565:
312 return AFBC_FMT_RGB565;
313 /* either of the below should not be reachable */
314 default:
315 DRM_WARN_ONCE("unsupported AFBC format[%08x]\n", format);
316 return -EINVAL;
317 }
318
319 return -EINVAL;
320 }
321
scl_vop_cal_scale(enum scale_mode mode,uint32_t src,uint32_t dst,bool is_horizontal,int vsu_mode,int * vskiplines)322 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
323 uint32_t dst, bool is_horizontal,
324 int vsu_mode, int *vskiplines)
325 {
326 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
327
328 if (vskiplines)
329 *vskiplines = 0;
330
331 if (is_horizontal) {
332 if (mode == SCALE_UP)
333 val = GET_SCL_FT_BIC(src, dst);
334 else if (mode == SCALE_DOWN)
335 val = GET_SCL_FT_BILI_DN(src, dst);
336 } else {
337 if (mode == SCALE_UP) {
338 if (vsu_mode == SCALE_UP_BIL)
339 val = GET_SCL_FT_BILI_UP(src, dst);
340 else
341 val = GET_SCL_FT_BIC(src, dst);
342 } else if (mode == SCALE_DOWN) {
343 if (vskiplines) {
344 *vskiplines = scl_get_vskiplines(src, dst);
345 val = scl_get_bili_dn_vskip(src, dst,
346 *vskiplines);
347 } else {
348 val = GET_SCL_FT_BILI_DN(src, dst);
349 }
350 }
351 }
352
353 return val;
354 }
355
scl_vop_cal_scl_fac(struct vop * vop,const struct vop_win_data * win,uint32_t src_w,uint32_t src_h,uint32_t dst_w,uint32_t dst_h,const struct drm_format_info * info)356 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
357 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
358 uint32_t dst_h, const struct drm_format_info *info)
359 {
360 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
361 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
362 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
363 bool is_yuv = false;
364 uint16_t cbcr_src_w = src_w / info->hsub;
365 uint16_t cbcr_src_h = src_h / info->vsub;
366 uint16_t vsu_mode;
367 uint16_t lb_mode;
368 uint32_t val;
369 int vskiplines;
370
371 if (info->is_yuv)
372 is_yuv = true;
373
374 if (dst_w > 3840) {
375 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
376 return;
377 }
378
379 if (!win->phy->scl->ext) {
380 VOP_SCL_SET(vop, win, scale_yrgb_x,
381 scl_cal_scale2(src_w, dst_w));
382 VOP_SCL_SET(vop, win, scale_yrgb_y,
383 scl_cal_scale2(src_h, dst_h));
384 if (is_yuv) {
385 VOP_SCL_SET(vop, win, scale_cbcr_x,
386 scl_cal_scale2(cbcr_src_w, dst_w));
387 VOP_SCL_SET(vop, win, scale_cbcr_y,
388 scl_cal_scale2(cbcr_src_h, dst_h));
389 }
390 return;
391 }
392
393 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
394 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
395
396 if (is_yuv) {
397 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
398 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
399 if (cbcr_hor_scl_mode == SCALE_DOWN)
400 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
401 else
402 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
403 } else {
404 if (yrgb_hor_scl_mode == SCALE_DOWN)
405 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
406 else
407 lb_mode = scl_vop_cal_lb_mode(src_w, false);
408 }
409
410 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
411 if (lb_mode == LB_RGB_3840X2) {
412 if (yrgb_ver_scl_mode != SCALE_NONE) {
413 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
414 return;
415 }
416 if (cbcr_ver_scl_mode != SCALE_NONE) {
417 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
418 return;
419 }
420 vsu_mode = SCALE_UP_BIL;
421 } else if (lb_mode == LB_RGB_2560X4) {
422 vsu_mode = SCALE_UP_BIL;
423 } else {
424 vsu_mode = SCALE_UP_BIC;
425 }
426
427 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
428 true, 0, NULL);
429 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
430 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
431 false, vsu_mode, &vskiplines);
432 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
433
434 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
435 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
436
437 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
438 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
439 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
440 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
441 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
442 if (is_yuv) {
443 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
444 dst_w, true, 0, NULL);
445 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
446 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
447 dst_h, false, vsu_mode, &vskiplines);
448 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
449
450 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
451 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
452 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
453 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
454 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
455 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
456 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
457 }
458 }
459
vop_dsp_hold_valid_irq_enable(struct vop * vop)460 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
461 {
462 unsigned long flags;
463
464 if (WARN_ON(!vop->is_enabled))
465 return;
466
467 spin_lock_irqsave(&vop->irq_lock, flags);
468
469 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
470 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
471
472 spin_unlock_irqrestore(&vop->irq_lock, flags);
473 }
474
vop_dsp_hold_valid_irq_disable(struct vop * vop)475 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
476 {
477 unsigned long flags;
478
479 if (WARN_ON(!vop->is_enabled))
480 return;
481
482 spin_lock_irqsave(&vop->irq_lock, flags);
483
484 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
485
486 spin_unlock_irqrestore(&vop->irq_lock, flags);
487 }
488
489 /*
490 * (1) each frame starts at the start of the Vsync pulse which is signaled by
491 * the "FRAME_SYNC" interrupt.
492 * (2) the active data region of each frame ends at dsp_vact_end
493 * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
494 * to get "LINE_FLAG" interrupt at the end of the active on screen data.
495 *
496 * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
497 * Interrupts
498 * LINE_FLAG -------------------------------+
499 * FRAME_SYNC ----+ |
500 * | |
501 * v v
502 * | Vsync | Vbp | Vactive | Vfp |
503 * ^ ^ ^ ^
504 * | | | |
505 * | | | |
506 * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
507 * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
508 * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
509 * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
510 */
vop_line_flag_irq_is_enabled(struct vop * vop)511 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
512 {
513 uint32_t line_flag_irq;
514 unsigned long flags;
515
516 spin_lock_irqsave(&vop->irq_lock, flags);
517
518 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
519
520 spin_unlock_irqrestore(&vop->irq_lock, flags);
521
522 return !!line_flag_irq;
523 }
524
vop_line_flag_irq_enable(struct vop * vop)525 static void vop_line_flag_irq_enable(struct vop *vop)
526 {
527 unsigned long flags;
528
529 if (WARN_ON(!vop->is_enabled))
530 return;
531
532 spin_lock_irqsave(&vop->irq_lock, flags);
533
534 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
535 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
536
537 spin_unlock_irqrestore(&vop->irq_lock, flags);
538 }
539
vop_line_flag_irq_disable(struct vop * vop)540 static void vop_line_flag_irq_disable(struct vop *vop)
541 {
542 unsigned long flags;
543
544 if (WARN_ON(!vop->is_enabled))
545 return;
546
547 spin_lock_irqsave(&vop->irq_lock, flags);
548
549 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
550
551 spin_unlock_irqrestore(&vop->irq_lock, flags);
552 }
553
vop_core_clks_enable(struct vop * vop)554 static int vop_core_clks_enable(struct vop *vop)
555 {
556 int ret;
557
558 ret = clk_enable(vop->hclk);
559 if (ret < 0)
560 return ret;
561
562 ret = clk_enable(vop->aclk);
563 if (ret < 0)
564 goto err_disable_hclk;
565
566 return 0;
567
568 err_disable_hclk:
569 clk_disable(vop->hclk);
570 return ret;
571 }
572
vop_core_clks_disable(struct vop * vop)573 static void vop_core_clks_disable(struct vop *vop)
574 {
575 clk_disable(vop->aclk);
576 clk_disable(vop->hclk);
577 }
578
vop_win_disable(struct vop * vop,const struct vop_win * vop_win)579 static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win)
580 {
581 const struct vop_win_data *win = vop_win->data;
582
583 if (win->phy->scl && win->phy->scl->ext) {
584 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
585 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
586 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
587 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
588 }
589
590 VOP_WIN_SET(vop, win, enable, 0);
591 vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win));
592 }
593
vop_enable(struct drm_crtc * crtc,struct drm_crtc_state * old_state)594 static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state)
595 {
596 struct vop *vop = to_vop(crtc);
597 int ret, i;
598
599 ret = pm_runtime_get_sync(vop->dev);
600 if (ret < 0) {
601 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
602 return ret;
603 }
604
605 ret = vop_core_clks_enable(vop);
606 if (WARN_ON(ret < 0))
607 goto err_put_pm_runtime;
608
609 ret = clk_enable(vop->dclk);
610 if (WARN_ON(ret < 0))
611 goto err_disable_core;
612
613 /*
614 * Slave iommu shares power, irq and clock with vop. It was associated
615 * automatically with this master device via common driver code.
616 * Now that we have enabled the clock we attach it to the shared drm
617 * mapping.
618 */
619 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
620 if (ret) {
621 DRM_DEV_ERROR(vop->dev,
622 "failed to attach dma mapping, %d\n", ret);
623 goto err_disable_dclk;
624 }
625
626 spin_lock(&vop->reg_lock);
627 for (i = 0; i < vop->len; i += 4)
628 writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
629
630 /*
631 * We need to make sure that all windows are disabled before we
632 * enable the crtc. Otherwise we might try to scan from a destroyed
633 * buffer later.
634 *
635 * In the case of enable-after-PSR, we don't need to worry about this
636 * case since the buffer is guaranteed to be valid and disabling the
637 * window will result in screen glitches on PSR exit.
638 */
639 if (!old_state || !old_state->self_refresh_active) {
640 for (i = 0; i < vop->data->win_size; i++) {
641 struct vop_win *vop_win = &vop->win[i];
642
643 vop_win_disable(vop, vop_win);
644 }
645 }
646
647 if (vop->data->afbc) {
648 struct rockchip_crtc_state *s;
649 /*
650 * Disable AFBC and forget there was a vop window with AFBC
651 */
652 VOP_AFBC_SET(vop, enable, 0);
653 s = to_rockchip_crtc_state(crtc->state);
654 s->enable_afbc = false;
655 }
656
657 vop_cfg_done(vop);
658
659 spin_unlock(&vop->reg_lock);
660
661 /*
662 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
663 */
664 vop->is_enabled = true;
665
666 spin_lock(&vop->reg_lock);
667
668 VOP_REG_SET(vop, common, standby, 1);
669
670 spin_unlock(&vop->reg_lock);
671
672 drm_crtc_vblank_on(crtc);
673
674 return 0;
675
676 err_disable_dclk:
677 clk_disable(vop->dclk);
678 err_disable_core:
679 vop_core_clks_disable(vop);
680 err_put_pm_runtime:
681 pm_runtime_put_sync(vop->dev);
682 return ret;
683 }
684
rockchip_drm_set_win_enabled(struct drm_crtc * crtc,bool enabled)685 static void rockchip_drm_set_win_enabled(struct drm_crtc *crtc, bool enabled)
686 {
687 struct vop *vop = to_vop(crtc);
688 int i;
689
690 spin_lock(&vop->reg_lock);
691
692 for (i = 0; i < vop->data->win_size; i++) {
693 struct vop_win *vop_win = &vop->win[i];
694 const struct vop_win_data *win = vop_win->data;
695
696 VOP_WIN_SET(vop, win, enable,
697 enabled && (vop->win_enabled & BIT(i)));
698 }
699 vop_cfg_done(vop);
700
701 spin_unlock(&vop->reg_lock);
702 }
703
vop_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)704 static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
705 struct drm_atomic_state *state)
706 {
707 struct vop *vop = to_vop(crtc);
708
709 WARN_ON(vop->event);
710
711 if (crtc->state->self_refresh_active)
712 rockchip_drm_set_win_enabled(crtc, false);
713
714 if (crtc->state->self_refresh_active)
715 goto out;
716
717 mutex_lock(&vop->vop_lock);
718
719 drm_crtc_vblank_off(crtc);
720
721 /*
722 * Vop standby will take effect at end of current frame,
723 * if dsp hold valid irq happen, it means standby complete.
724 *
725 * we must wait standby complete when we want to disable aclk,
726 * if not, memory bus maybe dead.
727 */
728 reinit_completion(&vop->dsp_hold_completion);
729 vop_dsp_hold_valid_irq_enable(vop);
730
731 spin_lock(&vop->reg_lock);
732
733 VOP_REG_SET(vop, common, standby, 1);
734
735 spin_unlock(&vop->reg_lock);
736
737 wait_for_completion(&vop->dsp_hold_completion);
738
739 vop_dsp_hold_valid_irq_disable(vop);
740
741 vop->is_enabled = false;
742
743 /*
744 * vop standby complete, so iommu detach is safe.
745 */
746 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
747
748 clk_disable(vop->dclk);
749 vop_core_clks_disable(vop);
750 pm_runtime_put(vop->dev);
751
752 mutex_unlock(&vop->vop_lock);
753
754 out:
755 if (crtc->state->event && !crtc->state->active) {
756 spin_lock_irq(&crtc->dev->event_lock);
757 drm_crtc_send_vblank_event(crtc, crtc->state->event);
758 spin_unlock_irq(&crtc->dev->event_lock);
759
760 crtc->state->event = NULL;
761 }
762 }
763
vop_plane_destroy(struct drm_plane * plane)764 static void vop_plane_destroy(struct drm_plane *plane)
765 {
766 drm_plane_cleanup(plane);
767 }
768
rockchip_afbc(u64 modifier)769 static inline bool rockchip_afbc(u64 modifier)
770 {
771 return modifier == ROCKCHIP_AFBC_MOD;
772 }
773
rockchip_mod_supported(struct drm_plane * plane,u32 format,u64 modifier)774 static bool rockchip_mod_supported(struct drm_plane *plane,
775 u32 format, u64 modifier)
776 {
777 if (modifier == DRM_FORMAT_MOD_LINEAR)
778 return true;
779
780 if (!rockchip_afbc(modifier)) {
781 DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier);
782
783 return false;
784 }
785
786 return vop_convert_afbc_format(format) >= 0;
787 }
788
vop_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)789 static int vop_plane_atomic_check(struct drm_plane *plane,
790 struct drm_atomic_state *state)
791 {
792 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
793 plane);
794 struct drm_crtc *crtc = new_plane_state->crtc;
795 struct drm_crtc_state *crtc_state;
796 struct drm_framebuffer *fb = new_plane_state->fb;
797 struct vop_win *vop_win = to_vop_win(plane);
798 const struct vop_win_data *win = vop_win->data;
799 int ret;
800 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
801 DRM_PLANE_HELPER_NO_SCALING;
802 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
803 DRM_PLANE_HELPER_NO_SCALING;
804
805 if (!crtc || WARN_ON(!fb))
806 return 0;
807
808 crtc_state = drm_atomic_get_existing_crtc_state(state,
809 crtc);
810 if (WARN_ON(!crtc_state))
811 return -EINVAL;
812
813 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
814 min_scale, max_scale,
815 true, true);
816 if (ret)
817 return ret;
818
819 if (!new_plane_state->visible)
820 return 0;
821
822 ret = vop_convert_format(fb->format->format);
823 if (ret < 0)
824 return ret;
825
826 /*
827 * Src.x1 can be odd when do clip, but yuv plane start point
828 * need align with 2 pixel.
829 */
830 if (fb->format->is_yuv && ((new_plane_state->src.x1 >> 16) % 2)) {
831 DRM_DEBUG_KMS("Invalid Source: Yuv format not support odd xpos\n");
832 return -EINVAL;
833 }
834
835 if (fb->format->is_yuv && new_plane_state->rotation & DRM_MODE_REFLECT_Y) {
836 DRM_DEBUG_KMS("Invalid Source: Yuv format does not support this rotation\n");
837 return -EINVAL;
838 }
839
840 if (rockchip_afbc(fb->modifier)) {
841 struct vop *vop = to_vop(crtc);
842
843 if (!vop->data->afbc) {
844 DRM_DEBUG_KMS("vop does not support AFBC\n");
845 return -EINVAL;
846 }
847
848 ret = vop_convert_afbc_format(fb->format->format);
849 if (ret < 0)
850 return ret;
851
852 if (new_plane_state->src.x1 || new_plane_state->src.y1) {
853 DRM_DEBUG_KMS("AFBC does not support offset display, " \
854 "xpos=%d, ypos=%d, offset=%d\n",
855 new_plane_state->src.x1, new_plane_state->src.y1,
856 fb->offsets[0]);
857 return -EINVAL;
858 }
859
860 if (new_plane_state->rotation && new_plane_state->rotation != DRM_MODE_ROTATE_0) {
861 DRM_DEBUG_KMS("No rotation support in AFBC, rotation=%d\n",
862 new_plane_state->rotation);
863 return -EINVAL;
864 }
865 }
866
867 return 0;
868 }
869
vop_plane_atomic_disable(struct drm_plane * plane,struct drm_atomic_state * state)870 static void vop_plane_atomic_disable(struct drm_plane *plane,
871 struct drm_atomic_state *state)
872 {
873 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
874 plane);
875 struct vop_win *vop_win = to_vop_win(plane);
876 struct vop *vop = to_vop(old_state->crtc);
877
878 if (!old_state->crtc)
879 return;
880
881 spin_lock(&vop->reg_lock);
882
883 vop_win_disable(vop, vop_win);
884
885 spin_unlock(&vop->reg_lock);
886 }
887
vop_plane_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)888 static void vop_plane_atomic_update(struct drm_plane *plane,
889 struct drm_atomic_state *state)
890 {
891 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
892 plane);
893 struct drm_crtc *crtc = new_state->crtc;
894 struct vop_win *vop_win = to_vop_win(plane);
895 const struct vop_win_data *win = vop_win->data;
896 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data;
897 struct vop *vop = to_vop(new_state->crtc);
898 struct drm_framebuffer *fb = new_state->fb;
899 unsigned int actual_w, actual_h;
900 unsigned int dsp_stx, dsp_sty;
901 uint32_t act_info, dsp_info, dsp_st;
902 struct drm_rect *src = &new_state->src;
903 struct drm_rect *dest = &new_state->dst;
904 struct drm_gem_object *obj, *uv_obj;
905 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
906 unsigned long offset;
907 dma_addr_t dma_addr;
908 uint32_t val;
909 bool rb_swap;
910 int win_index = VOP_WIN_TO_INDEX(vop_win);
911 int format;
912 int is_yuv = fb->format->is_yuv;
913 int i;
914
915 /*
916 * can't update plane when vop is disabled.
917 */
918 if (WARN_ON(!crtc))
919 return;
920
921 if (WARN_ON(!vop->is_enabled))
922 return;
923
924 if (!new_state->visible) {
925 vop_plane_atomic_disable(plane, state);
926 return;
927 }
928
929 obj = fb->obj[0];
930 rk_obj = to_rockchip_obj(obj);
931
932 actual_w = drm_rect_width(src) >> 16;
933 actual_h = drm_rect_height(src) >> 16;
934 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
935
936 dsp_info = (drm_rect_height(dest) - 1) << 16;
937 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
938
939 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
940 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
941 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
942
943 offset = (src->x1 >> 16) * fb->format->cpp[0];
944 offset += (src->y1 >> 16) * fb->pitches[0];
945 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
946
947 /*
948 * For y-mirroring we need to move address
949 * to the beginning of the last line.
950 */
951 if (new_state->rotation & DRM_MODE_REFLECT_Y)
952 dma_addr += (actual_h - 1) * fb->pitches[0];
953
954 format = vop_convert_format(fb->format->format);
955
956 spin_lock(&vop->reg_lock);
957
958 if (rockchip_afbc(fb->modifier)) {
959 int afbc_format = vop_convert_afbc_format(fb->format->format);
960
961 VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16);
962 VOP_AFBC_SET(vop, hreg_block_split, 0);
963 VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win));
964 VOP_AFBC_SET(vop, hdr_ptr, dma_addr);
965 VOP_AFBC_SET(vop, pic_size, act_info);
966 }
967
968 VOP_WIN_SET(vop, win, format, format);
969 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
970 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
971 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
972 VOP_WIN_SET(vop, win, y_mir_en,
973 (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
974 VOP_WIN_SET(vop, win, x_mir_en,
975 (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
976
977 if (is_yuv) {
978 int hsub = fb->format->hsub;
979 int vsub = fb->format->vsub;
980 int bpp = fb->format->cpp[1];
981
982 uv_obj = fb->obj[1];
983 rk_uv_obj = to_rockchip_obj(uv_obj);
984
985 offset = (src->x1 >> 16) * bpp / hsub;
986 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
987
988 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
989 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
990 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
991
992 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
993 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
994 win_yuv2yuv,
995 y2r_coefficients[i],
996 bt601_yuv2rgb[i]);
997 }
998 }
999
1000 if (win->phy->scl)
1001 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1002 drm_rect_width(dest), drm_rect_height(dest),
1003 fb->format);
1004
1005 VOP_WIN_SET(vop, win, act_info, act_info);
1006 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1007 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1008
1009 rb_swap = has_rb_swapped(vop->data->version, fb->format->format);
1010 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1011
1012 /*
1013 * Blending win0 with the background color doesn't seem to work
1014 * correctly. We only get the background color, no matter the contents
1015 * of the win0 framebuffer. However, blending pre-multiplied color
1016 * with the default opaque black default background color is a no-op,
1017 * so we can just disable blending to get the correct result.
1018 */
1019 if (fb->format->has_alpha && win_index > 0) {
1020 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1021 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
1022 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
1023 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
1024 SRC_BLEND_M0(ALPHA_PER_PIX) |
1025 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
1026 SRC_FACTOR_M0(ALPHA_ONE);
1027 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1028
1029 VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL);
1030 VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);
1031 VOP_WIN_SET(vop, win, alpha_en, 1);
1032 } else {
1033 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1034 VOP_WIN_SET(vop, win, alpha_en, 0);
1035 }
1036
1037 VOP_WIN_SET(vop, win, enable, 1);
1038 vop->win_enabled |= BIT(win_index);
1039 spin_unlock(&vop->reg_lock);
1040 }
1041
vop_plane_atomic_async_check(struct drm_plane * plane,struct drm_atomic_state * state)1042 static int vop_plane_atomic_async_check(struct drm_plane *plane,
1043 struct drm_atomic_state *state)
1044 {
1045 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1046 plane);
1047 struct vop_win *vop_win = to_vop_win(plane);
1048 const struct vop_win_data *win = vop_win->data;
1049 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
1050 DRM_PLANE_HELPER_NO_SCALING;
1051 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
1052 DRM_PLANE_HELPER_NO_SCALING;
1053 struct drm_crtc_state *crtc_state;
1054
1055 if (plane != new_plane_state->crtc->cursor)
1056 return -EINVAL;
1057
1058 if (!plane->state)
1059 return -EINVAL;
1060
1061 if (!plane->state->fb)
1062 return -EINVAL;
1063
1064 if (state)
1065 crtc_state = drm_atomic_get_existing_crtc_state(state,
1066 new_plane_state->crtc);
1067 else /* Special case for asynchronous cursor updates. */
1068 crtc_state = plane->crtc->state;
1069
1070 return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
1071 min_scale, max_scale,
1072 true, true);
1073 }
1074
vop_plane_atomic_async_update(struct drm_plane * plane,struct drm_atomic_state * state)1075 static void vop_plane_atomic_async_update(struct drm_plane *plane,
1076 struct drm_atomic_state *state)
1077 {
1078 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
1079 plane);
1080 struct vop *vop = to_vop(plane->state->crtc);
1081 struct drm_framebuffer *old_fb = plane->state->fb;
1082
1083 plane->state->crtc_x = new_state->crtc_x;
1084 plane->state->crtc_y = new_state->crtc_y;
1085 plane->state->crtc_h = new_state->crtc_h;
1086 plane->state->crtc_w = new_state->crtc_w;
1087 plane->state->src_x = new_state->src_x;
1088 plane->state->src_y = new_state->src_y;
1089 plane->state->src_h = new_state->src_h;
1090 plane->state->src_w = new_state->src_w;
1091 swap(plane->state->fb, new_state->fb);
1092
1093 if (vop->is_enabled) {
1094 vop_plane_atomic_update(plane, state);
1095 spin_lock(&vop->reg_lock);
1096 vop_cfg_done(vop);
1097 spin_unlock(&vop->reg_lock);
1098
1099 /*
1100 * A scanout can still be occurring, so we can't drop the
1101 * reference to the old framebuffer. To solve this we get a
1102 * reference to old_fb and set a worker to release it later.
1103 * FIXME: if we perform 500 async_update calls before the
1104 * vblank, then we can have 500 different framebuffers waiting
1105 * to be released.
1106 */
1107 if (old_fb && plane->state->fb != old_fb) {
1108 drm_framebuffer_get(old_fb);
1109 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
1110 drm_flip_work_queue(&vop->fb_unref_work, old_fb);
1111 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1112 }
1113 }
1114 }
1115
1116 static const struct drm_plane_helper_funcs plane_helper_funcs = {
1117 .atomic_check = vop_plane_atomic_check,
1118 .atomic_update = vop_plane_atomic_update,
1119 .atomic_disable = vop_plane_atomic_disable,
1120 .atomic_async_check = vop_plane_atomic_async_check,
1121 .atomic_async_update = vop_plane_atomic_async_update,
1122 };
1123
1124 static const struct drm_plane_funcs vop_plane_funcs = {
1125 .update_plane = drm_atomic_helper_update_plane,
1126 .disable_plane = drm_atomic_helper_disable_plane,
1127 .destroy = vop_plane_destroy,
1128 .reset = drm_atomic_helper_plane_reset,
1129 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1130 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1131 .format_mod_supported = rockchip_mod_supported,
1132 };
1133
vop_crtc_enable_vblank(struct drm_crtc * crtc)1134 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
1135 {
1136 struct vop *vop = to_vop(crtc);
1137 unsigned long flags;
1138
1139 if (WARN_ON(!vop->is_enabled))
1140 return -EPERM;
1141
1142 spin_lock_irqsave(&vop->irq_lock, flags);
1143
1144 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1145 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1146
1147 spin_unlock_irqrestore(&vop->irq_lock, flags);
1148
1149 return 0;
1150 }
1151
vop_crtc_disable_vblank(struct drm_crtc * crtc)1152 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
1153 {
1154 struct vop *vop = to_vop(crtc);
1155 unsigned long flags;
1156
1157 if (WARN_ON(!vop->is_enabled))
1158 return;
1159
1160 spin_lock_irqsave(&vop->irq_lock, flags);
1161
1162 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1163
1164 spin_unlock_irqrestore(&vop->irq_lock, flags);
1165 }
1166
vop_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1167 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1168 const struct drm_display_mode *mode,
1169 struct drm_display_mode *adjusted_mode)
1170 {
1171 struct vop *vop = to_vop(crtc);
1172 unsigned long rate;
1173
1174 /*
1175 * Clock craziness.
1176 *
1177 * Key points:
1178 *
1179 * - DRM works in in kHz.
1180 * - Clock framework works in Hz.
1181 * - Rockchip's clock driver picks the clock rate that is the
1182 * same _OR LOWER_ than the one requested.
1183 *
1184 * Action plan:
1185 *
1186 * 1. Try to set the exact rate first, and confirm the clock framework
1187 * can provide it.
1188 *
1189 * 2. If the clock framework cannot provide the exact rate, we should
1190 * add 999 Hz to the requested rate. That way if the clock we need
1191 * is 60000001 Hz (~60 MHz) and DRM tells us to make 60000 kHz then
1192 * the clock framework will actually give us the right clock.
1193 *
1194 * 3. Get the clock framework to round the rate for us to tell us
1195 * what it will actually make.
1196 *
1197 * 4. Store the rounded up rate so that we don't need to worry about
1198 * this in the actual clk_set_rate().
1199 */
1200 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000);
1201 if (rate / 1000 != adjusted_mode->clock)
1202 rate = clk_round_rate(vop->dclk,
1203 adjusted_mode->clock * 1000 + 999);
1204 adjusted_mode->clock = DIV_ROUND_UP(rate, 1000);
1205
1206 return true;
1207 }
1208
vop_dsp_lut_is_enabled(struct vop * vop)1209 static bool vop_dsp_lut_is_enabled(struct vop *vop)
1210 {
1211 return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en);
1212 }
1213
vop_crtc_write_gamma_lut(struct vop * vop,struct drm_crtc * crtc)1214 static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc)
1215 {
1216 struct drm_color_lut *lut = crtc->state->gamma_lut->data;
1217 unsigned int i;
1218
1219 for (i = 0; i < crtc->gamma_size; i++) {
1220 u32 word;
1221
1222 word = (drm_color_lut_extract(lut[i].red, 10) << 20) |
1223 (drm_color_lut_extract(lut[i].green, 10) << 10) |
1224 drm_color_lut_extract(lut[i].blue, 10);
1225 writel(word, vop->lut_regs + i * 4);
1226 }
1227 }
1228
vop_crtc_gamma_set(struct vop * vop,struct drm_crtc * crtc,struct drm_crtc_state * old_state)1229 static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc,
1230 struct drm_crtc_state *old_state)
1231 {
1232 struct drm_crtc_state *state = crtc->state;
1233 unsigned int idle;
1234 int ret;
1235
1236 if (!vop->lut_regs)
1237 return;
1238 /*
1239 * To disable gamma (gamma_lut is null) or to write
1240 * an update to the LUT, clear dsp_lut_en.
1241 */
1242 spin_lock(&vop->reg_lock);
1243 VOP_REG_SET(vop, common, dsp_lut_en, 0);
1244 vop_cfg_done(vop);
1245 spin_unlock(&vop->reg_lock);
1246
1247 /*
1248 * In order to write the LUT to the internal memory,
1249 * we need to first make sure the dsp_lut_en bit is cleared.
1250 */
1251 ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop,
1252 idle, !idle, 5, 30 * 1000);
1253 if (ret) {
1254 DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n");
1255 return;
1256 }
1257
1258 if (!state->gamma_lut)
1259 return;
1260
1261 spin_lock(&vop->reg_lock);
1262 vop_crtc_write_gamma_lut(vop, crtc);
1263 VOP_REG_SET(vop, common, dsp_lut_en, 1);
1264 vop_cfg_done(vop);
1265 spin_unlock(&vop->reg_lock);
1266 }
1267
vop_crtc_atomic_begin(struct drm_crtc * crtc,struct drm_atomic_state * state)1268 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1269 struct drm_atomic_state *state)
1270 {
1271 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1272 crtc);
1273 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1274 crtc);
1275 struct vop *vop = to_vop(crtc);
1276
1277 /*
1278 * Only update GAMMA if the 'active' flag is not changed,
1279 * otherwise it's updated by .atomic_enable.
1280 */
1281 if (crtc_state->color_mgmt_changed &&
1282 !crtc_state->active_changed)
1283 vop_crtc_gamma_set(vop, crtc, old_crtc_state);
1284 }
1285
vop_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)1286 static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
1287 struct drm_atomic_state *state)
1288 {
1289 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
1290 crtc);
1291 struct vop *vop = to_vop(crtc);
1292 const struct vop_data *vop_data = vop->data;
1293 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1294 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1295 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1296 u16 hdisplay = adjusted_mode->hdisplay;
1297 u16 htotal = adjusted_mode->htotal;
1298 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1299 u16 hact_end = hact_st + hdisplay;
1300 u16 vdisplay = adjusted_mode->vdisplay;
1301 u16 vtotal = adjusted_mode->vtotal;
1302 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1303 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1304 u16 vact_end = vact_st + vdisplay;
1305 uint32_t pin_pol, val;
1306 int dither_bpc = s->output_bpc ? s->output_bpc : 10;
1307 int ret;
1308
1309 if (old_state && old_state->self_refresh_active) {
1310 drm_crtc_vblank_on(crtc);
1311 rockchip_drm_set_win_enabled(crtc, true);
1312 return;
1313 }
1314
1315 /*
1316 * If we have a GAMMA LUT in the state, then let's make sure
1317 * it's updated. We might be coming out of suspend,
1318 * which means the LUT internal memory needs to be re-written.
1319 */
1320 if (crtc->state->gamma_lut)
1321 vop_crtc_gamma_set(vop, crtc, old_state);
1322
1323 mutex_lock(&vop->vop_lock);
1324
1325 WARN_ON(vop->event);
1326
1327 ret = vop_enable(crtc, old_state);
1328 if (ret) {
1329 mutex_unlock(&vop->vop_lock);
1330 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
1331 return;
1332 }
1333 pin_pol = (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
1334 BIT(HSYNC_POSITIVE) : 0;
1335 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
1336 BIT(VSYNC_POSITIVE) : 0;
1337 VOP_REG_SET(vop, output, pin_pol, pin_pol);
1338 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);
1339
1340 switch (s->output_type) {
1341 case DRM_MODE_CONNECTOR_LVDS:
1342 VOP_REG_SET(vop, output, rgb_dclk_pol, 1);
1343 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
1344 VOP_REG_SET(vop, output, rgb_en, 1);
1345 break;
1346 case DRM_MODE_CONNECTOR_eDP:
1347 VOP_REG_SET(vop, output, edp_dclk_pol, 1);
1348 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
1349 VOP_REG_SET(vop, output, edp_en, 1);
1350 break;
1351 case DRM_MODE_CONNECTOR_HDMIA:
1352 VOP_REG_SET(vop, output, hdmi_dclk_pol, 1);
1353 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
1354 VOP_REG_SET(vop, output, hdmi_en, 1);
1355 break;
1356 case DRM_MODE_CONNECTOR_DSI:
1357 VOP_REG_SET(vop, output, mipi_dclk_pol, 1);
1358 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
1359 VOP_REG_SET(vop, output, mipi_en, 1);
1360 VOP_REG_SET(vop, output, mipi_dual_channel_en,
1361 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL));
1362 break;
1363 case DRM_MODE_CONNECTOR_DisplayPort:
1364 VOP_REG_SET(vop, output, dp_dclk_pol, 0);
1365 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
1366 VOP_REG_SET(vop, output, dp_en, 1);
1367 break;
1368 default:
1369 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
1370 s->output_type);
1371 }
1372
1373 /*
1374 * if vop is not support RGB10 output, need force RGB10 to RGB888.
1375 */
1376 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1377 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
1378 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1379
1380 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
1381 VOP_REG_SET(vop, common, pre_dither_down, 1);
1382 else
1383 VOP_REG_SET(vop, common, pre_dither_down, 0);
1384
1385 if (dither_bpc == 6) {
1386 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO);
1387 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666);
1388 VOP_REG_SET(vop, common, dither_down_en, 1);
1389 } else {
1390 VOP_REG_SET(vop, common, dither_down_en, 0);
1391 }
1392
1393 VOP_REG_SET(vop, common, out_mode, s->output_mode);
1394
1395 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
1396 val = hact_st << 16;
1397 val |= hact_end;
1398 VOP_REG_SET(vop, modeset, hact_st_end, val);
1399 VOP_REG_SET(vop, modeset, hpost_st_end, val);
1400
1401 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
1402 val = vact_st << 16;
1403 val |= vact_end;
1404 VOP_REG_SET(vop, modeset, vact_st_end, val);
1405 VOP_REG_SET(vop, modeset, vpost_st_end, val);
1406
1407 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
1408
1409 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1410
1411 VOP_REG_SET(vop, common, standby, 0);
1412 mutex_unlock(&vop->vop_lock);
1413 }
1414
vop_fs_irq_is_pending(struct vop * vop)1415 static bool vop_fs_irq_is_pending(struct vop *vop)
1416 {
1417 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1418 }
1419
vop_wait_for_irq_handler(struct vop * vop)1420 static void vop_wait_for_irq_handler(struct vop *vop)
1421 {
1422 bool pending;
1423 int ret;
1424
1425 /*
1426 * Spin until frame start interrupt status bit goes low, which means
1427 * that interrupt handler was invoked and cleared it. The timeout of
1428 * 10 msecs is really too long, but it is just a safety measure if
1429 * something goes really wrong. The wait will only happen in the very
1430 * unlikely case of a vblank happening exactly at the same time and
1431 * shouldn't exceed microseconds range.
1432 */
1433 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1434 !pending, 0, 10 * 1000);
1435 if (ret)
1436 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1437
1438 synchronize_irq(vop->irq);
1439 }
1440
vop_crtc_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)1441 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1442 struct drm_atomic_state *state)
1443 {
1444 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1445 crtc);
1446 struct vop *vop = to_vop(crtc);
1447 struct drm_plane *plane;
1448 struct drm_plane_state *plane_state;
1449 struct rockchip_crtc_state *s;
1450 int afbc_planes = 0;
1451
1452 if (vop->lut_regs && crtc_state->color_mgmt_changed &&
1453 crtc_state->gamma_lut) {
1454 unsigned int len;
1455
1456 len = drm_color_lut_size(crtc_state->gamma_lut);
1457 if (len != crtc->gamma_size) {
1458 DRM_DEBUG_KMS("Invalid LUT size; got %d, expected %d\n",
1459 len, crtc->gamma_size);
1460 return -EINVAL;
1461 }
1462 }
1463
1464 drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
1465 plane_state =
1466 drm_atomic_get_plane_state(crtc_state->state, plane);
1467 if (IS_ERR(plane_state)) {
1468 DRM_DEBUG_KMS("Cannot get plane state for plane %s\n",
1469 plane->name);
1470 return PTR_ERR(plane_state);
1471 }
1472
1473 if (drm_is_afbc(plane_state->fb->modifier))
1474 ++afbc_planes;
1475 }
1476
1477 if (afbc_planes > 1) {
1478 DRM_DEBUG_KMS("Invalid number of AFBC planes; got %d, expected at most 1\n", afbc_planes);
1479 return -EINVAL;
1480 }
1481
1482 s = to_rockchip_crtc_state(crtc_state);
1483 s->enable_afbc = afbc_planes > 0;
1484
1485 return 0;
1486 }
1487
vop_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_atomic_state * state)1488 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1489 struct drm_atomic_state *state)
1490 {
1491 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1492 crtc);
1493 struct drm_atomic_state *old_state = old_crtc_state->state;
1494 struct drm_plane_state *old_plane_state, *new_plane_state;
1495 struct vop *vop = to_vop(crtc);
1496 struct drm_plane *plane;
1497 struct rockchip_crtc_state *s;
1498 int i;
1499
1500 if (WARN_ON(!vop->is_enabled))
1501 return;
1502
1503 spin_lock(&vop->reg_lock);
1504
1505 /* Enable AFBC if there is some AFBC window, disable otherwise. */
1506 s = to_rockchip_crtc_state(crtc->state);
1507 VOP_AFBC_SET(vop, enable, s->enable_afbc);
1508 vop_cfg_done(vop);
1509
1510 spin_unlock(&vop->reg_lock);
1511
1512 /*
1513 * There is a (rather unlikely) possiblity that a vblank interrupt
1514 * fired before we set the cfg_done bit. To avoid spuriously
1515 * signalling flip completion we need to wait for it to finish.
1516 */
1517 vop_wait_for_irq_handler(vop);
1518
1519 spin_lock_irq(&crtc->dev->event_lock);
1520 if (crtc->state->event) {
1521 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1522 WARN_ON(vop->event);
1523
1524 vop->event = crtc->state->event;
1525 crtc->state->event = NULL;
1526 }
1527 spin_unlock_irq(&crtc->dev->event_lock);
1528
1529 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1530 new_plane_state, i) {
1531 if (!old_plane_state->fb)
1532 continue;
1533
1534 if (old_plane_state->fb == new_plane_state->fb)
1535 continue;
1536
1537 drm_framebuffer_get(old_plane_state->fb);
1538 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1539 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1540 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1541 }
1542 }
1543
1544 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1545 .mode_fixup = vop_crtc_mode_fixup,
1546 .atomic_check = vop_crtc_atomic_check,
1547 .atomic_begin = vop_crtc_atomic_begin,
1548 .atomic_flush = vop_crtc_atomic_flush,
1549 .atomic_enable = vop_crtc_atomic_enable,
1550 .atomic_disable = vop_crtc_atomic_disable,
1551 };
1552
vop_crtc_destroy(struct drm_crtc * crtc)1553 static void vop_crtc_destroy(struct drm_crtc *crtc)
1554 {
1555 drm_crtc_cleanup(crtc);
1556 }
1557
vop_crtc_duplicate_state(struct drm_crtc * crtc)1558 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1559 {
1560 struct rockchip_crtc_state *rockchip_state;
1561
1562 if (WARN_ON(!crtc->state))
1563 return NULL;
1564
1565 rockchip_state = kmemdup(to_rockchip_crtc_state(crtc->state),
1566 sizeof(*rockchip_state), GFP_KERNEL);
1567 if (!rockchip_state)
1568 return NULL;
1569
1570 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1571 return &rockchip_state->base;
1572 }
1573
vop_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)1574 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1575 struct drm_crtc_state *state)
1576 {
1577 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1578
1579 __drm_atomic_helper_crtc_destroy_state(&s->base);
1580 kfree(s);
1581 }
1582
vop_crtc_reset(struct drm_crtc * crtc)1583 static void vop_crtc_reset(struct drm_crtc *crtc)
1584 {
1585 struct rockchip_crtc_state *crtc_state =
1586 kzalloc(sizeof(*crtc_state), GFP_KERNEL);
1587
1588 if (crtc->state)
1589 vop_crtc_destroy_state(crtc, crtc->state);
1590
1591 if (crtc_state)
1592 __drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);
1593 else
1594 __drm_atomic_helper_crtc_reset(crtc, NULL);
1595 }
1596
1597 #ifdef CONFIG_DRM_ANALOGIX_DP
vop_get_edp_connector(struct vop * vop)1598 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1599 {
1600 struct drm_connector *connector;
1601 struct drm_connector_list_iter conn_iter;
1602
1603 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1604 drm_for_each_connector_iter(connector, &conn_iter) {
1605 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1606 drm_connector_list_iter_end(&conn_iter);
1607 return connector;
1608 }
1609 }
1610 drm_connector_list_iter_end(&conn_iter);
1611
1612 return NULL;
1613 }
1614
vop_crtc_set_crc_source(struct drm_crtc * crtc,const char * source_name)1615 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1616 const char *source_name)
1617 {
1618 struct vop *vop = to_vop(crtc);
1619 struct drm_connector *connector;
1620 int ret;
1621
1622 connector = vop_get_edp_connector(vop);
1623 if (!connector)
1624 return -EINVAL;
1625
1626 if (source_name && strcmp(source_name, "auto") == 0)
1627 ret = analogix_dp_start_crc(connector);
1628 else if (!source_name)
1629 ret = analogix_dp_stop_crc(connector);
1630 else
1631 ret = -EINVAL;
1632
1633 return ret;
1634 }
1635
1636 static int
vop_crtc_verify_crc_source(struct drm_crtc * crtc,const char * source_name,size_t * values_cnt)1637 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1638 size_t *values_cnt)
1639 {
1640 if (source_name && strcmp(source_name, "auto") != 0)
1641 return -EINVAL;
1642
1643 *values_cnt = 3;
1644 return 0;
1645 }
1646
1647 #else
vop_crtc_set_crc_source(struct drm_crtc * crtc,const char * source_name)1648 static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1649 const char *source_name)
1650 {
1651 return -ENODEV;
1652 }
1653
1654 static int
vop_crtc_verify_crc_source(struct drm_crtc * crtc,const char * source_name,size_t * values_cnt)1655 vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1656 size_t *values_cnt)
1657 {
1658 return -ENODEV;
1659 }
1660 #endif
1661
1662 static const struct drm_crtc_funcs vop_crtc_funcs = {
1663 .set_config = drm_atomic_helper_set_config,
1664 .page_flip = drm_atomic_helper_page_flip,
1665 .destroy = vop_crtc_destroy,
1666 .reset = vop_crtc_reset,
1667 .atomic_duplicate_state = vop_crtc_duplicate_state,
1668 .atomic_destroy_state = vop_crtc_destroy_state,
1669 .enable_vblank = vop_crtc_enable_vblank,
1670 .disable_vblank = vop_crtc_disable_vblank,
1671 .set_crc_source = vop_crtc_set_crc_source,
1672 .verify_crc_source = vop_crtc_verify_crc_source,
1673 };
1674
vop_fb_unref_worker(struct drm_flip_work * work,void * val)1675 static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1676 {
1677 struct vop *vop = container_of(work, struct vop, fb_unref_work);
1678 struct drm_framebuffer *fb = val;
1679
1680 drm_crtc_vblank_put(&vop->crtc);
1681 drm_framebuffer_put(fb);
1682 }
1683
vop_handle_vblank(struct vop * vop)1684 static void vop_handle_vblank(struct vop *vop)
1685 {
1686 struct drm_device *drm = vop->drm_dev;
1687 struct drm_crtc *crtc = &vop->crtc;
1688
1689 spin_lock(&drm->event_lock);
1690 if (vop->event) {
1691 drm_crtc_send_vblank_event(crtc, vop->event);
1692 drm_crtc_vblank_put(crtc);
1693 vop->event = NULL;
1694 }
1695 spin_unlock(&drm->event_lock);
1696
1697 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1698 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1699 }
1700
vop_isr(int irq,void * data)1701 static irqreturn_t vop_isr(int irq, void *data)
1702 {
1703 struct vop *vop = data;
1704 struct drm_crtc *crtc = &vop->crtc;
1705 uint32_t active_irqs;
1706 int ret = IRQ_NONE;
1707
1708 /*
1709 * The irq is shared with the iommu. If the runtime-pm state of the
1710 * vop-device is disabled the irq has to be targeted at the iommu.
1711 */
1712 if (!pm_runtime_get_if_in_use(vop->dev))
1713 return IRQ_NONE;
1714
1715 if (vop_core_clks_enable(vop)) {
1716 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");
1717 goto out;
1718 }
1719
1720 /*
1721 * interrupt register has interrupt status, enable and clear bits, we
1722 * must hold irq_lock to avoid a race with enable/disable_vblank().
1723 */
1724 spin_lock(&vop->irq_lock);
1725
1726 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1727 /* Clear all active interrupt sources */
1728 if (active_irqs)
1729 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1730
1731 spin_unlock(&vop->irq_lock);
1732
1733 /* This is expected for vop iommu irqs, since the irq is shared */
1734 if (!active_irqs)
1735 goto out_disable;
1736
1737 if (active_irqs & DSP_HOLD_VALID_INTR) {
1738 complete(&vop->dsp_hold_completion);
1739 active_irqs &= ~DSP_HOLD_VALID_INTR;
1740 ret = IRQ_HANDLED;
1741 }
1742
1743 if (active_irqs & LINE_FLAG_INTR) {
1744 complete(&vop->line_flag_completion);
1745 active_irqs &= ~LINE_FLAG_INTR;
1746 ret = IRQ_HANDLED;
1747 }
1748
1749 if (active_irqs & FS_INTR) {
1750 drm_crtc_handle_vblank(crtc);
1751 vop_handle_vblank(vop);
1752 active_irqs &= ~FS_INTR;
1753 ret = IRQ_HANDLED;
1754 }
1755
1756 /* Unhandled irqs are spurious. */
1757 if (active_irqs)
1758 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1759 active_irqs);
1760
1761 out_disable:
1762 vop_core_clks_disable(vop);
1763 out:
1764 pm_runtime_put(vop->dev);
1765 return ret;
1766 }
1767
vop_plane_add_properties(struct drm_plane * plane,const struct vop_win_data * win_data)1768 static void vop_plane_add_properties(struct drm_plane *plane,
1769 const struct vop_win_data *win_data)
1770 {
1771 unsigned int flags = 0;
1772
1773 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0;
1774 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0;
1775 if (flags)
1776 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1777 DRM_MODE_ROTATE_0 | flags);
1778 }
1779
vop_create_crtc(struct vop * vop)1780 static int vop_create_crtc(struct vop *vop)
1781 {
1782 const struct vop_data *vop_data = vop->data;
1783 struct device *dev = vop->dev;
1784 struct drm_device *drm_dev = vop->drm_dev;
1785 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1786 struct drm_crtc *crtc = &vop->crtc;
1787 struct device_node *port;
1788 int ret;
1789 int i;
1790
1791 /*
1792 * Create drm_plane for primary and cursor planes first, since we need
1793 * to pass them to drm_crtc_init_with_planes, which sets the
1794 * "possible_crtcs" to the newly initialized crtc.
1795 */
1796 for (i = 0; i < vop_data->win_size; i++) {
1797 struct vop_win *vop_win = &vop->win[i];
1798 const struct vop_win_data *win_data = vop_win->data;
1799
1800 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1801 win_data->type != DRM_PLANE_TYPE_CURSOR)
1802 continue;
1803
1804 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1805 0, &vop_plane_funcs,
1806 win_data->phy->data_formats,
1807 win_data->phy->nformats,
1808 win_data->phy->format_modifiers,
1809 win_data->type, NULL);
1810 if (ret) {
1811 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1812 ret);
1813 goto err_cleanup_planes;
1814 }
1815
1816 plane = &vop_win->base;
1817 drm_plane_helper_add(plane, &plane_helper_funcs);
1818 vop_plane_add_properties(plane, win_data);
1819 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1820 primary = plane;
1821 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1822 cursor = plane;
1823 }
1824
1825 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1826 &vop_crtc_funcs, NULL);
1827 if (ret)
1828 goto err_cleanup_planes;
1829
1830 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1831 if (vop->lut_regs) {
1832 drm_mode_crtc_set_gamma_size(crtc, vop_data->lut_size);
1833 drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size);
1834 }
1835
1836 /*
1837 * Create drm_planes for overlay windows with possible_crtcs restricted
1838 * to the newly created crtc.
1839 */
1840 for (i = 0; i < vop_data->win_size; i++) {
1841 struct vop_win *vop_win = &vop->win[i];
1842 const struct vop_win_data *win_data = vop_win->data;
1843 unsigned long possible_crtcs = drm_crtc_mask(crtc);
1844
1845 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1846 continue;
1847
1848 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1849 possible_crtcs,
1850 &vop_plane_funcs,
1851 win_data->phy->data_formats,
1852 win_data->phy->nformats,
1853 win_data->phy->format_modifiers,
1854 win_data->type, NULL);
1855 if (ret) {
1856 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1857 ret);
1858 goto err_cleanup_crtc;
1859 }
1860 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1861 vop_plane_add_properties(&vop_win->base, win_data);
1862 }
1863
1864 port = of_get_child_by_name(dev->of_node, "port");
1865 if (!port) {
1866 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1867 dev->of_node);
1868 ret = -ENOENT;
1869 goto err_cleanup_crtc;
1870 }
1871
1872 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1873 vop_fb_unref_worker);
1874
1875 init_completion(&vop->dsp_hold_completion);
1876 init_completion(&vop->line_flag_completion);
1877 crtc->port = port;
1878
1879 ret = drm_self_refresh_helper_init(crtc);
1880 if (ret)
1881 DRM_DEV_DEBUG_KMS(vop->dev,
1882 "Failed to init %s with SR helpers %d, ignoring\n",
1883 crtc->name, ret);
1884
1885 return 0;
1886
1887 err_cleanup_crtc:
1888 drm_crtc_cleanup(crtc);
1889 err_cleanup_planes:
1890 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1891 head)
1892 drm_plane_cleanup(plane);
1893 return ret;
1894 }
1895
vop_destroy_crtc(struct vop * vop)1896 static void vop_destroy_crtc(struct vop *vop)
1897 {
1898 struct drm_crtc *crtc = &vop->crtc;
1899 struct drm_device *drm_dev = vop->drm_dev;
1900 struct drm_plane *plane, *tmp;
1901
1902 drm_self_refresh_helper_cleanup(crtc);
1903
1904 of_node_put(crtc->port);
1905
1906 /*
1907 * We need to cleanup the planes now. Why?
1908 *
1909 * The planes are "&vop->win[i].base". That means the memory is
1910 * all part of the big "struct vop" chunk of memory. That memory
1911 * was devm allocated and associated with this component. We need to
1912 * free it ourselves before vop_unbind() finishes.
1913 */
1914 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1915 head)
1916 vop_plane_destroy(plane);
1917
1918 /*
1919 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1920 * references the CRTC.
1921 */
1922 drm_crtc_cleanup(crtc);
1923 drm_flip_work_cleanup(&vop->fb_unref_work);
1924 }
1925
vop_initial(struct vop * vop)1926 static int vop_initial(struct vop *vop)
1927 {
1928 struct reset_control *ahb_rst;
1929 int i, ret;
1930
1931 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1932 if (IS_ERR(vop->hclk)) {
1933 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
1934 return PTR_ERR(vop->hclk);
1935 }
1936 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1937 if (IS_ERR(vop->aclk)) {
1938 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
1939 return PTR_ERR(vop->aclk);
1940 }
1941 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1942 if (IS_ERR(vop->dclk)) {
1943 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
1944 return PTR_ERR(vop->dclk);
1945 }
1946
1947 ret = pm_runtime_get_sync(vop->dev);
1948 if (ret < 0) {
1949 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
1950 return ret;
1951 }
1952
1953 ret = clk_prepare(vop->dclk);
1954 if (ret < 0) {
1955 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
1956 goto err_put_pm_runtime;
1957 }
1958
1959 /* Enable both the hclk and aclk to setup the vop */
1960 ret = clk_prepare_enable(vop->hclk);
1961 if (ret < 0) {
1962 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
1963 goto err_unprepare_dclk;
1964 }
1965
1966 ret = clk_prepare_enable(vop->aclk);
1967 if (ret < 0) {
1968 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
1969 goto err_disable_hclk;
1970 }
1971
1972 /*
1973 * do hclk_reset, reset all vop registers.
1974 */
1975 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1976 if (IS_ERR(ahb_rst)) {
1977 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
1978 ret = PTR_ERR(ahb_rst);
1979 goto err_disable_aclk;
1980 }
1981 reset_control_assert(ahb_rst);
1982 usleep_range(10, 20);
1983 reset_control_deassert(ahb_rst);
1984
1985 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
1986 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
1987
1988 for (i = 0; i < vop->len; i += sizeof(u32))
1989 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
1990
1991 VOP_REG_SET(vop, misc, global_regdone_en, 1);
1992 VOP_REG_SET(vop, common, dsp_blank, 0);
1993
1994 for (i = 0; i < vop->data->win_size; i++) {
1995 struct vop_win *vop_win = &vop->win[i];
1996 const struct vop_win_data *win = vop_win->data;
1997 int channel = i * 2 + 1;
1998
1999 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
2000 vop_win_disable(vop, vop_win);
2001 VOP_WIN_SET(vop, win, gate, 1);
2002 }
2003
2004 vop_cfg_done(vop);
2005
2006 /*
2007 * do dclk_reset, let all config take affect.
2008 */
2009 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
2010 if (IS_ERR(vop->dclk_rst)) {
2011 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
2012 ret = PTR_ERR(vop->dclk_rst);
2013 goto err_disable_aclk;
2014 }
2015 reset_control_assert(vop->dclk_rst);
2016 usleep_range(10, 20);
2017 reset_control_deassert(vop->dclk_rst);
2018
2019 clk_disable(vop->hclk);
2020 clk_disable(vop->aclk);
2021
2022 vop->is_enabled = false;
2023
2024 pm_runtime_put_sync(vop->dev);
2025
2026 return 0;
2027
2028 err_disable_aclk:
2029 clk_disable_unprepare(vop->aclk);
2030 err_disable_hclk:
2031 clk_disable_unprepare(vop->hclk);
2032 err_unprepare_dclk:
2033 clk_unprepare(vop->dclk);
2034 err_put_pm_runtime:
2035 pm_runtime_put_sync(vop->dev);
2036 return ret;
2037 }
2038
2039 /*
2040 * Initialize the vop->win array elements.
2041 */
vop_win_init(struct vop * vop)2042 static void vop_win_init(struct vop *vop)
2043 {
2044 const struct vop_data *vop_data = vop->data;
2045 unsigned int i;
2046
2047 for (i = 0; i < vop_data->win_size; i++) {
2048 struct vop_win *vop_win = &vop->win[i];
2049 const struct vop_win_data *win_data = &vop_data->win[i];
2050
2051 vop_win->data = win_data;
2052 vop_win->vop = vop;
2053
2054 if (vop_data->win_yuv2yuv)
2055 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i];
2056 }
2057 }
2058
2059 /**
2060 * rockchip_drm_wait_vact_end
2061 * @crtc: CRTC to enable line flag
2062 * @mstimeout: millisecond for timeout
2063 *
2064 * Wait for vact_end line flag irq or timeout.
2065 *
2066 * Returns:
2067 * Zero on success, negative errno on failure.
2068 */
rockchip_drm_wait_vact_end(struct drm_crtc * crtc,unsigned int mstimeout)2069 int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
2070 {
2071 struct vop *vop = to_vop(crtc);
2072 unsigned long jiffies_left;
2073 int ret = 0;
2074
2075 if (!crtc || !vop->is_enabled)
2076 return -ENODEV;
2077
2078 mutex_lock(&vop->vop_lock);
2079 if (mstimeout <= 0) {
2080 ret = -EINVAL;
2081 goto out;
2082 }
2083
2084 if (vop_line_flag_irq_is_enabled(vop)) {
2085 ret = -EBUSY;
2086 goto out;
2087 }
2088
2089 reinit_completion(&vop->line_flag_completion);
2090 vop_line_flag_irq_enable(vop);
2091
2092 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2093 msecs_to_jiffies(mstimeout));
2094 vop_line_flag_irq_disable(vop);
2095
2096 if (jiffies_left == 0) {
2097 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
2098 ret = -ETIMEDOUT;
2099 goto out;
2100 }
2101
2102 out:
2103 mutex_unlock(&vop->vop_lock);
2104 return ret;
2105 }
2106 EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
2107
vop_bind(struct device * dev,struct device * master,void * data)2108 static int vop_bind(struct device *dev, struct device *master, void *data)
2109 {
2110 struct platform_device *pdev = to_platform_device(dev);
2111 const struct vop_data *vop_data;
2112 struct drm_device *drm_dev = data;
2113 struct vop *vop;
2114 struct resource *res;
2115 int ret, irq;
2116
2117 vop_data = of_device_get_match_data(dev);
2118 if (!vop_data)
2119 return -ENODEV;
2120
2121 /* Allocate vop struct and its vop_win array */
2122 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size),
2123 GFP_KERNEL);
2124 if (!vop)
2125 return -ENOMEM;
2126
2127 vop->dev = dev;
2128 vop->data = vop_data;
2129 vop->drm_dev = drm_dev;
2130 dev_set_drvdata(dev, vop);
2131
2132 vop_win_init(vop);
2133
2134 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2135 vop->regs = devm_ioremap_resource(dev, res);
2136 if (IS_ERR(vop->regs))
2137 return PTR_ERR(vop->regs);
2138 vop->len = resource_size(res);
2139
2140 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2141 if (res) {
2142 if (!vop_data->lut_size) {
2143 DRM_DEV_ERROR(dev, "no gamma LUT size defined\n");
2144 return -EINVAL;
2145 }
2146 vop->lut_regs = devm_ioremap_resource(dev, res);
2147 if (IS_ERR(vop->lut_regs))
2148 return PTR_ERR(vop->lut_regs);
2149 }
2150
2151 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2152 if (!vop->regsbak)
2153 return -ENOMEM;
2154
2155 irq = platform_get_irq(pdev, 0);
2156 if (irq < 0) {
2157 DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
2158 return irq;
2159 }
2160 vop->irq = (unsigned int)irq;
2161
2162 spin_lock_init(&vop->reg_lock);
2163 spin_lock_init(&vop->irq_lock);
2164 mutex_init(&vop->vop_lock);
2165
2166 ret = vop_create_crtc(vop);
2167 if (ret)
2168 return ret;
2169
2170 pm_runtime_enable(&pdev->dev);
2171
2172 ret = vop_initial(vop);
2173 if (ret < 0) {
2174 DRM_DEV_ERROR(&pdev->dev,
2175 "cannot initial vop dev - err %d\n", ret);
2176 goto err_disable_pm_runtime;
2177 }
2178
2179 ret = devm_request_irq(dev, vop->irq, vop_isr,
2180 IRQF_SHARED, dev_name(dev), vop);
2181 if (ret)
2182 goto err_disable_pm_runtime;
2183
2184 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) {
2185 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev);
2186 if (IS_ERR(vop->rgb)) {
2187 ret = PTR_ERR(vop->rgb);
2188 goto err_disable_pm_runtime;
2189 }
2190 }
2191
2192 return 0;
2193
2194 err_disable_pm_runtime:
2195 pm_runtime_disable(&pdev->dev);
2196 vop_destroy_crtc(vop);
2197 return ret;
2198 }
2199
vop_unbind(struct device * dev,struct device * master,void * data)2200 static void vop_unbind(struct device *dev, struct device *master, void *data)
2201 {
2202 struct vop *vop = dev_get_drvdata(dev);
2203
2204 if (vop->rgb)
2205 rockchip_rgb_fini(vop->rgb);
2206
2207 pm_runtime_disable(dev);
2208 vop_destroy_crtc(vop);
2209
2210 clk_unprepare(vop->aclk);
2211 clk_unprepare(vop->hclk);
2212 clk_unprepare(vop->dclk);
2213 }
2214
2215 const struct component_ops vop_component_ops = {
2216 .bind = vop_bind,
2217 .unbind = vop_unbind,
2218 };
2219 EXPORT_SYMBOL_GPL(vop_component_ops);
2220